Posts Tagged ‘accellera’
IEEE 1801™-2013 UPF Standard Is Published
Download the standard now – at no charge
The IEEE Standards Association (IEEE-SA) has published the latest UPF 2.1 standard, officially called IEEE Standard for Design and Verification of Low-Power Integrated Circuits, many refer to it as IEEE 1801 or UPF for the Unified Power Format as this was the name Accellera had given it prior to transferring standardization responsibility and ongoing maintenance and enhancement to the IEEE. Further – Courtesy of Accellera – the standard is available for download without charge directly from the IEEE.
The latest update to IEEE 1801 is ready for download. It joins other EDA standards, like SystemVerilog and SystemC in the IEEE Get™ program that grants public access to view and download current individual standards at no charge as a PDF. (If you wish to have an older, superseded and withdrawn version of the standard or if you wish to have a printed copy or have it in a CD-ROM format, you can purchase older and alternate formats from IEEE for a fee.)
The official IEEE announcement on the standard’s publication can be found here. And the official Accellera announcement that it has partnered with the IEEE-SA to offer the standard to all at no charge can be found here. This revision of the standard had one of the largest number of IEEE-SA entity members of any corporate standards program. Participation from the IEEE-SA global community of entity participants ensures the needs of a broad set of companies are captured to support this worldwide standard.
Just In Time For DAC
DAC 2013 has many events that will allow you to learn more about the new standard and how to use it to your maximum benefit. And for those who cannot attend DAC, visit the Verification Academy, you will find the Low Power sessions cover the new standard as well. [Registration required; restrictions apply.]
Sunday
Topic: DAC Workshop: Low-Power Design with the New IEEE 1801-2013 Standard
Date: 2 June 2013
Time: 1:00 p.m. – 5:00 p.m.
Location: Convention Center: Room 18C
Registration: Official DAC Workshop registration required ($). For more information and to register, click here.
Monday
Accellera Breakfast & Town Hall Meeting
Topic: The Standard for Low Power Design and Verification is here! What’s next?
Date: 3 June 2013
Time: 7:00 a.m. – 8:45 a.m.
Location: Convention Center: Ballroom D
Registration: This is a free Accellera event, but registration is required. Form more information click here and to register, click here.
Monday
Verification Academy
Topic: “Low Power Monday”
Date: 3 June 2013
Time: 11:00 a.m. – 6:00 p.m.
Location: Tradeshow Floor – Booth 1215
Registration: The DAC Tradeshow floor is open to all DAC registrants. Visit www.dac.com to register.
The Verification Academy is open to all DAC registrants. There are no restrictions and we invite everyone to visit booth 1215 for Low Power sessions that may be of interest to you on Monday. To help judge attendance, please feel free to pre-register at here. I look forward to see you there as you will find me here most of the time Monday-Wednesday.
| Time | Description | Presenter | |
| 11:00 a.m. – 12:00 p.m. | Low Power Verification | Tim Jordon MicroChip Technlogy |
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| 1:00 p.m. – 2:00 p.m | What’s New in UPF 2.1? | Erich Marschner IEEE 1801 Vice-chair Mentor Graphics |
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| 2:00 p.m. – 3:00 p.m. | UPF-Based Verification for Cypress PSOC | Ellie Burns Mentor Graphics |
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| 4:00 p.m. – 5:00 p.m. | Optimizing for Power Efficient Design | Abhishek Ranjan Calypto |
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| 5:00 p.m. – 6:00 p.m. | IEEE 1801 UPF Commands and Methodology | John Biggs ARM IEEE 1801 Chair |
If you are coming to DAC and participating in the DAC Low Power Workshop on Sunday, or in other events, download your person copy of the new IEEE 1800-2013 standard today. The PDF form allows you to take it with you and read it using your favorite e-reader or i-device. Let’s me know what you think of the standard. And – See you at DAC!
Tags: accellera, dac, IEEE 1801, IEEE Get, ieee standards association, Low Power, Standards, upf
Part 1: The 2012 Wilson Research Group Functional Verification Study
Design Trends
In my previous blog, I introduced the 2012 Wilson Research Group Functional Verification Study (click here). The objective of my previous blog was to provide background on this large, worldwide industry study. I will present the key findings from this study in a set of upcoming blogs.
This blog begins the process of revealing the 2012 Wilson Research Group study findings by first focusing on current design trends. Let’s begin by examining process geometry adoption trends, as shown in Figure 1. Here, you will see trend comparisons between the 2007 Far West Research study (gray line), the 2010 Wilson Research Group study (blue line), and the 2012 Wilson Research Group study (green line).
Figure 1. Process geometry trends
Worldwide, the median process geometry size from the 2007 Far West Research study was about 90nm, while the median process geometry size is about 65nm in 2010. Today, the mean process geometry size for a typical project is about 45nm—although you can see that over a third of projects today are designing below 32nm.
In addition to the industry moving to smaller process geometries, the industry is also moving to larger design sizes as measured in number of gates of logic and datapath, excluding memories (which should not be a surprise). Figure 2 compares design sizes from the 2002 Collett study (dark blue line), the 2007 Far West Research study (gray line), the 2010 Wilson Research Group study (light blue line), and the 2012 Wilson Research Group study (green line).
Figure 2. Number of gates of logic and datapath trends, excluding memories
The study revealed that about a third of the non-FPGA designs today are less than 5M gates, while a third range in size between 5M to 20M gates, and about a third of all designs are larger than 20M gates.
It’s important to note here that the data on the mean design size trends does not reflect volume in terms of semiconductor production. For example, you could have fewer projects designing at a small geometry, yet they have higher volume in terms of production.
In Figure 3, I show the mean design size trends between the 2002 Collett study (dark blue line), the 2007 Far West Research study (gray line), the 2010 Wilson Research Group study (light blue line), and the 2012 Wilson Research Group study (green line). Obviously, gate counts have increased over the years, yet a significant number of designs continue to be developed with smaller (and larger) gate counts as indicated by the mean calculation. Another observation is that, as you would expect, the mean gate count trend is essentially following Moore’s law.
Figure 3. Mean design size trends
Figure 4 presents the current design implementation trends for non-FPGAs as identified by the survey participants.
Figure 4. Non-FPGA current design implementation trends
The data in Figure 4 presents trends in design implementation approaches for non-FPGA designs, ranging from the 2002 Collett study (dark blue bar), the 2004 Collet study (dark green bar), the 2007 Far West Research study (gray bar), the 2010 Wilson Research Group study (blue bar), and the 2012 Wilson Research Group study (green bar). Note that the study seems to indicate that there is a downward trend in standard cell design implementation.
Figure 5. FPGA design implementation trends
For the 2012 study, we decided that we wanted to get a sense of the percentage of FPGA projects that target the very complex programmable SoC FPGAs that have recently emerged, which is shown in Figure 5. Examples of these programmable SoC FPGAs include: Xilinx’s Zynq, Altera’s Arria/Cydone, and Microsemi’s SmarFusion.
In my next blog (click here), I’ll continue discussing current design trends, focusing specifically on embedded processors, power, and clock domains.
Tags: accellera, functional verification, IEEE, IEEE 1800, Verification, Verification Academy
Prologue: The 2012 Wilson Research Group Functional Verification Study
This is the first in a series of blogs that presents the results from the 2012 Wilson Research Group Functional Verification Study.
Study Overview
In 2002 and 2004, Ron Collett International, Inc. conducted its well known ASIC/IC functional verification studies, which provided invaluable insight into the state of the electronic industry and its trends in design and verification. However, after the 2004 study, no other industry studies were conducted, which left a void in identifying industry trends.
To address this void, Mentor Graphics commissioned Far West Research to conduct an industry study on functional verification in the fall of 2007. Then in the fall of 2010, Mentor commissioned Wilson Research Group to conduct another functional verification study. Both of these studies were conducted as blind studies to avoid influencing the results. This means that the survey participants did not know that the study was commissioned by Mentor Graphics. In addition, to support trend analysis on the data, both studies followed the same format and questions (when possible) as the original 2002 and 2004 Collett studies.
In the fall of 2012, Mentor Graphics commissioned Wilson Research Group again to conduct a new functional verification study. This study was also a blind study and follows the same format as the Collett, Far West Research, and previous Wilson Research Group studies. The 2012 Wilson Research Group study is one of the largest functional verification studies ever conducted. The overall confidence level of the study was calculated to be 95% with a margin of error of 4.05%.
Unlike the previous Collett and Far West Research studies that were conducted only in North America, both the 2010 and 2012 Wilson Research Group studies were worldwide studies. The regions targeted were:
- North America:Canada,United States
- Europe/Israel:Finland,France,Germany,Israel,Italy,Sweden,UK
- Asia (minusIndia):China,Korea,Japan,Taiwan
- India
The survey results are compiled both globally and regionally for analysis.
Another difference between the Wilson Research Group and previous industry studies is that both of the Wilson Research Group studies also included FPGA projects. Hence for the first time, we are able to present some emerging trends in the FPGA functional verification space.
Figure 1 shows the percentage makeup of survey participants by their job description. The red bars represents the FPGA participants while the green bars represent the non-FPGA (i.e., IC/ASIC) participants.
Figure 1: Survey participants job title description
Figure 2 shows the percentage makeup of survey participants by company type. Again, the red bars represents the FPGA participants while the green bars represents the non-FPGA (i.e., IC/ASIC) participants.
Figure 2: Survey participants company description
In a future set of blogs, over the course of the next few months, I plan to present the highlights from the 2012 Wilson Research Group study along with my analysis, comments, and obviously, opinions. A few interesting observations emerged from the study, which include:
- FPGA projects are beginning to adopt advanced verification techniques due to increased design complexity.
- The effort spent on verification is increasing.
- The industry is converging on common processes driven by maturing industry standards.
My next blog presents current design trends that were identified by the survey. This will be followed by a set of blogs focused on the functional verification results.
Also, to learn more about the 2012 Wilson Reserach Group study, view my pre-recorded Functional Verification Study web-seminar, which is located out on the Verification Academy website.
Quick links to the 2012 Wilson Research Group Study results (so far…)
- Part 1 – Design Trends
Tags: accellera, Assertion-Based Verification, formal verification, functional coverage, functional verification, IEEE, Simulation, Standards, SystemVerilog, UVM, Verification Academy, Verification Methodology, verilog, vhdl
Get your IEEE 1800-2012 SystemVerilog LRM at no charge
Today at this week’s DVCon 2013 conference, the IEEE Standards Association (IEEE-SA) and Accellera Systems Initiative (Accellera) have jointly announced the public availability of the IEEE 1800 SystemVerilog Language Reference Manual at no charge through the IEEE Get Program.
As I posted a few weeks ago, the 1800-2012 is not a major revision of the standard, but does contain a few enhancements that will be of interest to design and verification engineers alike. However, providing the standard as freely available download is major news.
Even though the relative cost of the LRM was minor compared to the cost of most projects utilizing the standard, there seemed to be a barrier in most engineer’s minds in justifying the expense. So most just continued to use the last freely available SystemVerilog 3.1a LRM, which was 9 years old and very obsolete for such a rapidly changing technology.
Thanks Accellera!
Tags: accellera, functional verification, IEEE, IEEE-SA, SystemVerilog
Coverage Cookbook Debuts
Verification Academy Adds Major New Technical Resource
The Verification Academy adds another major methodology cookbook to focus on effective coverage adoption. The Coverage Cookbook describes the different types of coverage that are available to track your verification process progress, how to create a functional coverage model from a specification, and provides examples to implement functional coverage for different types of designs.
Verification Academy “full access” members have access to the free Coverage Cookbook and the UVM/OVM Cookbooks as well. Are you a registered full access member? If not, register now to become a full access member. (Restrictions apply.)
Coverage is not a new topic. It was one of major additions to the SystemVerilog (IEEE Std. 1800™-2009) standard. But the SystemVerilog functional coverage extensions were left to the verification engineer to use in such as way to return meaningful measurements of how much of the design specification was being tested. The Universal Verification Methodology (UVM) offers greater structure for coverage over SystemVerilog, but it too, is still only a piece of the puzzle.
As verification teams have come to generate greater amounts of information from use of SystemVerilog, UVM and other verification tools, the data from the verification runs needs to be easily used to drive coverage closure. Within the Mentor Graphics Questa verification platform, this resulted in the development of the Unified Coverage Database (UCDB) and associated verification management and planning features.
Since verification teams use a variety of tools and technology from many sources, it was an imperative that verification information could be easily shared and combined to help drive faster coverage closure across the industry. This is why Mentor Graphics donated its UCDB API to Accellera where it became the Unified Coverage Interoperability Standard (UCIS).
It would be great to think that we are done; but we’re not. Tools and data are just two dimensions of the three dimensions to any IC design project. A comprehensive approach to verification management that handles all of this adds the third dimension. The Mentor Graphics Questa Verification Management features handle all this.
Now the question is how to best adopt and use all the capabilities at hand from the standards to the verification technology at your finger tips.
The Verification Academy Coverage Cookbook is one of the important tools you now have to help pull all the information into a single place where you can learn the theory and put that theory into practice. The Coverage Cookbook is much like the OVM/UVM Cookbooks in that it is web friendly, while supporting the ability for you to generate a PDF file of the whole document in case you want to have a printed copy or have it available for offline reference.
The Theory section covers:
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The Practice section shows three examples you can use today:
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The Coverage Cookbook is a live document. You can expect continued extensions and contributions to enhance it. As Harry Foster, Mentor Graphics’ Chief Scientist Verification put it, “Methodology is the bridge between tools and technologies, which creates a productive, predictable, and repeatable solution.” We should expect that our collective use of this technology will help hone the methodology which is the heart of the Coverage Cookbook. And with this use, we should expect the Coverage Cookbook to evolve as we achieve greater verification productivity.
Let us know what you think about the Coverage Cookbook and what we might be able to do to improve it. In the meantime, Happy Coverage Closing!
Tags: accellera, Coverage, Coverage Closure, Coverage Cookbook, functional coverage, Harry Foster, IEEE 1800, OVM, SystemVerilog, UCDB, UCIS, UVM, Verification Academy
OVM Gets Connected
OVM Bridges SystemVerilog and SystemC Languages
When UVM Connect was first released, the multilingual connection between IEEE Std. 1800™ (SystemVerilog) and IEEE Std. 1666™ (SystemC) standards bridged the two languages to allow design and verification engineers to access UVM from SystemC or SystemVerilog to exploit native languages advantages. OVM users wondered if it was possible to support them as well since OVM is a derived from UVM.
It is possible and UVM Connect has been extended to allow OVM users to enjoy the same benefits. An update to UVM Connect now allows it to be compiled to run with the OVM. And since the extensions are based on IEEE standards, they can be used in your simulator of choice.
OVM Thrives
The thriving OVM community is of no surprise. Last year, Harry Foster blogged about research on the use and adoption of verification methodologies. The research was done after UVM was established as an Accellera standard, and showed OVM continued its leading position as shown in one of the charts from Harry’s blog (see below). The chart even showed OVM was predicted to have a modest growth in adoption as well.
Mentor continues to bring many of the UVM additions back to the OVM user community in a way that does not disturb the upgrade path from OVM to UVM. The major addition to UVM in the first round of Accellera standardization was the addition of a register and memory package. This was back ported to OVM. (The OVM register and memory kit can be found here, if you are interested.) Now, UVM Connect has been extended to provide full OVM use.
Download
The UVM Connect 2.2 kit supports multilingual use of OVM and can be found at the Verification Academy and the Accellera UVM World contributions download site.
If you find issues or have other suggestions that we should consider, you can always share your input at the OVM Forum or UVM Forum. In addition to interacting with other users, the Verification Academy is a good site for online resources like the UVM/OVM Cookbook, basic and advanced OVM/UVM training, and more.
Tags: 1666, 1800, accellera, IEEE, Multilanguage OVM, Multilanguage UVM, OVM, Standards, systemc, SystemVerilog, UVM, UVM Connect
OpenStand & EDA Standardization
Five Leading Global Organizations Affirm “The Modern Paradigm for Standards”
The EDA industry has seen changes to the international standards paradigm the past few decades. When industry helped launch VHDL with the help of government support, it transferred ongoing maintenance and enhancement to the IEEE when it completed its first version. In addition to anchoring the standard at the IEEE, collaboration with the IEC for international standardization and recognition with the one-country, one-vote process set the stage for international approval of VHDL.
In the early days of Verilog, I encouraged similar support for that IEEE standard. But its support was not immediate and to some may have failed to track the pace of support by industry. Indeed, with Accellera developing SystemVerilog, later to become an IEEE standard and IEC standard, what was missing was the close link between a global industrial community and the international setting in which the standard was developed and deployed.
In the case of SystemVerilog, global markets drove the international deployment of the standard without respect to its formal status. Indeed, on what was called the “birthday” of SystemVerilog in Japan, the day it was approved as an official IEEE standard, the Japanese National Committee on standards hosted an open celebration that I was invited to attend. There was no waiting on their part the formal status. The interdependencies of global design, global commerce and global partnerships have driven all of us to adapt the standards development process for EDA.
On the eve of OpenStand’s launch, it is good to see the IEEE, Internet Society, W3C, IAB and IETF come together to put in writing what is the emerging practice for EDA.
You can learn more about the supporters of OpenStand, their guiding principles and how you can give your input, comments and feedback by visiting their website at http://open-stand.org. And if you agree, you can even “stand” with them; with me; with us.
But in short, OpenStand promotes a standards development model that demands:
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Tags: accellera, IAB, iec, IEEE, Internet Society, ITEF, OpenStand, Standards, SystemVerilog, vhdl, W3C
Verification Standards Take Another Step Forward
Accellera Ushers in Unified Coverage Interoperability Standard (UCIS)
For the past few months, Accellera’s Unified Coverage Interoperability Standards working group has completed and released a new standard that is destined to help boost verification productivity and efficiency. Verification teams use a variety of verification technologies, many times from different suppliers, to achieve their verification goals. Collecting information on how each tool adds to verification closure and sharing this information for ever larger designs among different tools has become a daunting challenge.
As a precursor to addressing this from a standardization point of view, many companies built their own way of collecting and sharing this information. Users recognized the need for a standard and market participants responded. For Mentor Graphics part, we developed and deployed the Unified Coverage Database (UCDB) technology for our verification products several years back. Via our Questa Vanguard Partnership program, many partners have integrated into the UCDB to help drive further verification efficiency and productivity for mutual customers.
Yet, users were still left with the challenge to use the emerging coverage database technologies from multiple vendors. Those users sought a solution to this dilemma from Accellera. After users completed a requirements document that outlined their needs, we at Mentor Graphics noted that our UCDB technology offered a good match. We offered to seed the standards development with our tested technology, as did other suppliers. In the end and with extensions from consultations with other suppliers, an updated UCDB Application Programming Interface (API) specification from Mentor Graphics formed the basis from which Accellera created the UCIS API standard.
In July 2008 we announced the Mentor Graphics technology donation to this Accellera standards effort. And on the day Accellera announced completion and availability of the standard at DAC 2012, Mentor Graphics was the first to announce product support.
To read more about support of UCIS and how it plays a critical role in verification, you may wish to read the article in the DAC issue of Verification Horizons.
The UCIS co-chair, Dr. Richard Ho from D.E. Shaw Research presented a comprehensive overview of UCIS at DAC. Dr. Ho along with his co-chair, Dr. Ambar Sarkar of Paradigm Works, Inc. also presented a tutorial at DVCon 2012 titled An Introduction to the Unified Coverage Interoperability Standard. The tutorial is available online. Accellera does require registration for the tutorial. The DVCon 2012 website on the UCIS tutorial goes into detail about what is covered in this 1 hour presentation.
I highly recommend you register and watch the DVCon 2012 tutorial for a good overview of UCIS. You can also download, for free and without registration, your copy of the Unified Coverage Interoperability Standard here. It makes a good companion for the tutorial.
What will you do with UCIS?
After reading the standard and watching the tutorial you should have a solid understanding of the importance it plays to reach coverage closure. You will learn how you can create applications to improve your own verification productivity and efficiency. Do you want to share the applications you write? The new UCIS forum and contribution area was created just for this purpose by Accellera. Please visit the site, register and contribute.
As more users begin to adopt UCIS, I envision this site will provide a good site for users to share applications.
Off to DAC!
Where might our paths cross?
It is always challenge to fit all the needed visits in during the Design Automation Conference (DAC). If you happen to like some of the same events I attend, then the chances are good our paths might cross in public.
Saturday and Sunday are busy with an Accellera Systems Initiative board meeting. Split across two days, Accellera board members will meet to conduct traditional business and do some strategic planning in which each board member outlines what they aspire the goals and objectives for the group should be in the coming year. Intel has graciously granted space in their San Francisco offices, so I won’t be around the Moscone Center during the pre-conference setup phase. (By the way, Thank you Intel!)
After we close the Accellera board meeting on Sunday, I plan to attend the pre-DAC events on Sunday that include the EDAC reception (registration required) at 6:00pm (San Francisco Marriott, Salon 7) and Gary Smith’s “Sunday Night at DAC” at 7:00pm (San Francisco Marriott, Salon 6).
During the conference I will spend most of my time at the Mentor Graphics Verification Academy Booth #1514 and on Wednesday split my time between there and the Accellera Systems Imitative meetings. And just in case you may note that most of my evenings are not scheduled, they are with customer activities.
When the show floor is open, you will find me most of the time at the Verification Academy Booth #1514. I will join Mentor’s Harry Foster there were user and partner presentations will be done on UVM applications, updates on Harry’s research results, updates on important verification standards from Mentor’s perspective and more. You are invited to join other verification experts for the Tuesday evening cocktail reception at the Verification Academy Booth. (And the cocktail hour may be just the thing that tis needed before the annual DAC Birds-Of-A-Feather meetings begin to help the conversations start.)
Verification Academy DAC Schedule
| Monday, June 4th | Tuesday, June 5th | Wednesday, June 6th |
10:00 – Simulation and Formal Assertion-Based VerificationHarry Foster, Mentor Graphics |
9:30 – Using the UVM Register Layer
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10:00 – Bringing UVM to Life
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11:00 – Bringing UVM to Life
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10:00 – Generating Coverage Models and Achieving Coverage Closure
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11:00 – Resistance is Futile: Learning to love UVM!
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2:00 – Verification of Low Power SoCs with IEEE UPF
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2:00 – Bringing UVM to Life
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2:00 – Automating Assertion Based Verification with NextOp and Mentor Graphics
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3:00 - Evolving Trends in Functional Verification
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3:00 - Evolving Trends in Functional Verification
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3:00 – UVM Express
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4:00 – An Introduction to AMBA 4 AXI Coherency Extensions (ACE) and Verification Challenges
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4:00 - Evolving Trends in Functional Verification
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5:00 - Using Rules-Based Integration to Develop a SoC-Level UVM Verification Environment
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5:00 – Meet the Verification Experts Cocktail Reception |
Accellera Systems Initiative will host a set of meetings on Wednesday starting with a luncheon to roll out the Unified Coverage Operability Standard (UCIS). The lunch is free and seating is limited and registration is required.
Hosted Luncheon and Technical Presentation
Accellera Systems Initiative Rolls Out the Unified Coverage Interoperability Standard
Speaker: Dr. Richard Ho, Co-Chair of the UCIS Technical Subcommittee
Wednesday, June 6, 12:00-1:30pm
Moscone Center, Room 250
Register Now >
This luncheon is open to all DAC attendees. Seating is limited! You must pre-register for this event.
Coverage metrics are critical to measuring and guiding design verification. As designs have grown, increasingly advanced verification technologies, methods and additional metrics have been designed to form a fuller coverage model. There is currently no single metric that consistently and globally tells engineers the exact status of verification. But one step in the right direction is to bring all types of coverage metrics into a single database that can be accessed in an industry standard way. The UCIS facilitates the creation of a unified coverage database that allows for interoperability of coverage data across multiple tools from multiple vendors.
This presentation, intended for verification managers and tool developers alike, provides an introduction to and overview of the UCIS and how users plan to utilize it to enhance their verification flows. We provide a survey of many of the commonly-used coverage metrics and how they are modeled in the UCIS. The information that users will be able to access through the UCIS will allow them to write their own applications to analyze, grade, merge and report coverage from one or more databases from one or more tool vendors. We will also discuss the XML-based interchange format of UCIS, which provides a path to exchange coverage databases without requiring a common code library between tools and vendors.
SystemC User Group Meeting
NASCUG XVIII
North American SystemC User’s Group Meeting
Wednesday, June 6, 2:00-6:00pm
Moscone Center, Room 262
Register Now >
This event is open to all DAC attendees. Seating is limited!
The North American SystemC Users Group (NASCUG) provides a unique forum for sharing SystemC experiences and knowledge among industry, research and universities. The agendafor the event has a lot offer user group attendees.
Mentor’s Adam Erickson will present An Open-Source, Standards-Based Library for Achieving Interoperability Between TLM Models in SystemC and SystemVerilog. Adam’s presentation is scheduled to start at 3:00pm.
Tags: accellera, dac, edac, gary smith, Standards, systemc, TLM, UCIS, upf, UVM, Verification Academy
UVM: Some Thoughts Before DVCon
It is time to talk about what happens next with UVM
The Design and Verification Conference (DVCon) has become the premier event to discuss front-end design issues with an emphasis on verification. If one listens to the Conversation Central interview of DVCon leadership it is clear how singularly important DVCon is. As one of the three organizers of the UVM Tutorial on Monday, I know the conference organizers had to rearrange the room layout to accommodate a greater than expected number of registrant. It is clear how important the topic of verification is and UVM in particular has become.
It seems to me that DVCon is the right place to discuss what comes next with UVM. I have three thoughts about UVM that I think merit discussion.
1. UVM needs a period of stability
While the experts at the Accellera Verification IP Technical Subcommittee (VIP-TSC) standardization table (all good people) continue to hone UVM and debate a few more features they need, they have been unable to make significant progress on those features since last DVCon. The one major item promised beyond OVM, an update to phasing, remains an open topic. Mentor has suggested in committee that we allow another year to pass and suspend committee action on this. Maybe the natural market forces would allow several options to surface, be user-tested and then merit consideration by the VIP-TSC.
This is in keeping with Karen Bartleson’s 9th Commandment for Effective Standards: “Start with Donations; Not From Scratch.” This is what is happening now with Phasing. The design by committee process is moving slowly. It is not the slow part that concerns me, however.
Completing the “last” thing has many in the verification community waiting until it is done before they migrate and adopt UVM. The best thing the committee could do to encourage use is to give the users certainty that UVM will not change in the next 12 months. At the same time, the committee could commit to take input from users at the end of those 12 months as a guide to what it does next.
2. UVM needs a simple path to first use
Accellera has an approved and published standard, an open-source implementation and embedded UVM User’s Guide. This is a lot to digest. And while one may expect the User’s Guide to help, it calls the reader to supplement it with “education, experience and professional judgment.” It warns that “not all aspects of this guide may be applicable in all circumstances.”
Users should be offered an unambiguous, easy-to-use and understand means to adopt UVM without having to know everything about it before starting to use it. UVM was not made for just those who have large verification teams and central CAD groups. Those large teams are the ones who are already using UVM. The first step to UVM adoption for the rest of the world should not be too high as it currently is.
UVM needs a simple path for fast adoption.
3. UVM needs to bridge the system domain
Accellera System Initiative has come to life from the unification of Accellera and OSCI. While the vision to bring the two organizations together is without fault, the lack of a publicly visible plan to leverage each others strengths is noted by Gabe Moretti in his recent blog on DVCon when he wrote: “First we build it and then we figure out how to use it has never been a good architectural approach, especially in electronics.” His comment was in response to the questions to be asked at DVCon’s Monday lunch about what the new organization should look like. Gabe certainly thought “the creators of the organization must have some ideas of the focus, mission and goals.”
I certainly do. In the case of UVM, I think it needs a bridge between the SystemVerilog world in which it was written and the SystemC world of design and modeling. As teams move to higher levels of abstraction for system-level architectural exploration and definition, the need for efficient and reusable functional models has become an imperative.
It is no secret to the Accellera VIP-TSC that Mentor Graphics thinks this is needed. Our presentation to committee members on a UVM API to facilitate this outlines exactly what we think should be done to address reusable functional models in the system world. [Accellera requires registration to download the Mentor presentation. Accellera members can register here. Guests require VIP-TSC leadership permission and can request it here.]
UVM must grow and bridge the system world. The Accellera SystemC Verification Working Group (VWG) knows this. They have a meeting planned at the DATE conference to discuss future evolutions related to SystemC and Verification on 14 March 2012 from 1230-1340 in Conference Room 4 which I plan to attend. The VWG meeting is open to external participants, not just Accellera members.
Summary
I don’t know what your thoughts about what should happen next with UVM are. Feel free to share them here if you wish or join me at DVCon or DATE and we can discuss it with the whole community. Maybe there is hope we can make progress on these three areas in the coming year.
Tags: accellera, DATE Conference, dvcon, Standards, systemc, SystemVerilog, UVM
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
Latest Posts
- Texas-Sized DAC Edition of Verification Horizons Now Up on Verification Academy
- IEEE 1801™-2013 UPF Standard Is Published
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
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