Posts Tagged ‘1800’
IEEE Approves Revised SystemVerilog Standard
IEEE Std. 1800™-2012 Officially Ratified
The IEEE Standards Association (SA) Standards Board (SASB) officially approved the latest SystemVerilog revision, Draft 6, as an IEEE standard. The SASB Review Committee (RevCom) agenda and the SASB agenda include review and formal approval of the latest work by the IEEE Computer Society Design Automation Standards Committee’s (DASC) SystemVerilog Working Group at their December 2012 meeting series.
What’s New?
The new standard has many new features, numerous clarifications and various corrections to improve the standard and keep pace with electronic system design and verification. DVCon 2012 included a session presentation, Keeping Up with Chip – The Proposed SystemVerilog 2012 Standard Makes Verifying Ever-Increasing Design Complexity More Efficient” that detailed the standard. The paper was written by Stuart Sutherland (Sutherland HDL, Inc.) and Tom Fitzpatrick (Mentor Graphics). You can find a copy of the paper here at the DVCon 2012 archive and the presentation can be found at Sutherland HDL’s site here.
For users of Mentor Graphics’ Questa Verification Platform, many of the major SystemVerilog 2012 features can be used today, like multiple inheritance. As Stu and Tom said in their presentation, “This is BIG!” If you read their full paper, they discuss some ways this new feature might be useful for a UVM testbench.
Major work was done to augment the current notion of constraints in SystemVerilog. In past versions of the standard they were known as hard constraints. What this meant was all the conditions of the constraints had to be met otherwise there would be an error. There was no built-in method to relax the need to satisfy the constraints. Given the world of multiple constraints is the norm for testbenches today the potential for conflicts between them is high. To alleviate this the SystemVerilog Working Group introduced soft constraints to the standard. If you are interested in the details of what was proposed to be added the standard, you can reference the full proposal here that is included in the standard. Stu and Tom said that “This is also a big enhancement!”
Availability
IEEE 1800™-2012 has only now been approved. The standard itself is not ready to be published yet. Plans are to have it ready to be published before DVCon 2013, which is scheduled for late February 2013. I will share publication information as it becomes available. And, I hope you join me and attend DVCon 2013 where we can plan to celebrate the unveiling of the published standard.
While the IEEE publication will be the authoritative source on the standard, I have pointed to the presentation and paper by Stu Sutherland and Tom Fitzpatrick for information on the new standard that you can reference now. For those who depend on assertions, you will find SystemVerilog-2012 has a major update with enhancements for properties and sequences in the area of immediate assertions, data type support, argument passing, vacuity definitions, global clock resolution and inferred clocking in sequences and much more. You may find the SystemVerilog Assertions Handbook 3rd Edition by Ben Cohen, et. al. to be of value as well. You can find more information about it on Amazon.com here.
The Story Continues…
There is much more to the SystemVerilog-2012 story I will share more of that in the months ahead. The global team of experts who have put this together has been an outstanding collection of individuals ranging from producers and suppliers of electronic design automation software to consumers of said technology who have ensured the language can be used to design and verify the most demanding of electronic systems.
Stay tuned! For now, I encourage you to get informed!
Tags: 1800, Assertions, Ben Cohen, DASC, dvcon, Hard Constraints, IEEE SASB, IEEE-SA, Muttiple Inheritance, RevCom, Soft Constraints, Standards, Stu Sutherland, SystemVerilog, Tom Fitzpatrick, UVM
OVM Gets Connected
OVM Bridges SystemVerilog and SystemC Languages
When UVM Connect was first released, the multilingual connection between IEEE Std. 1800™ (SystemVerilog) and IEEE Std. 1666™ (SystemC) standards bridged the two languages to allow design and verification engineers to access UVM from SystemC or SystemVerilog to exploit native languages advantages. OVM users wondered if it was possible to support them as well since OVM is a derived from UVM.
It is possible and UVM Connect has been extended to allow OVM users to enjoy the same benefits. An update to UVM Connect now allows it to be compiled to run with the OVM. And since the extensions are based on IEEE standards, they can be used in your simulator of choice.
OVM Thrives
The thriving OVM community is of no surprise. Last year, Harry Foster blogged about research on the use and adoption of verification methodologies. The research was done after UVM was established as an Accellera standard, and showed OVM continued its leading position as shown in one of the charts from Harry’s blog (see below). The chart even showed OVM was predicted to have a modest growth in adoption as well.
Mentor continues to bring many of the UVM additions back to the OVM user community in a way that does not disturb the upgrade path from OVM to UVM. The major addition to UVM in the first round of Accellera standardization was the addition of a register and memory package. This was back ported to OVM. (The OVM register and memory kit can be found here, if you are interested.) Now, UVM Connect has been extended to provide full OVM use.
Download
The UVM Connect 2.2 kit supports multilingual use of OVM and can be found at the Verification Academy and the Accellera UVM World contributions download site.
If you find issues or have other suggestions that we should consider, you can always share your input at the OVM Forum or UVM Forum. In addition to interacting with other users, the Verification Academy is a good site for online resources like the UVM/OVM Cookbook, basic and advanced OVM/UVM training, and more.
Tags: 1666, 1800, accellera, IEEE, Multilanguage OVM, Multilanguage UVM, OVM, Standards, systemc, SystemVerilog, UVM, UVM Connect
How Did I Get Here?
Remembering Don Loughry
“How did you get involved in standards,” I was asked.
On a business trip to India in 2009, I was asked to come by the Mentor office in Noida to meet with some “freshers” and other participants in Mentor’s Displaced Worker Program who were in the middle of a SystemVerilog training. As one of many who have been engaged in the development of the SystemVerilog (aka IEEE Std 1800™-2009) standard the past decade, they were curious to know how I became involved in the development of this standard.
“How did you get involved in standards,” I was asked.
“My work on SystemVerilog comes from an early exposure to IEEE standards, much like you are getting today,” I told them.
In the late 1970’s a visiting lecture from Hewlett-Packard spent a year at UC Davis where I went to school. One of the courses I took was a hardware interface to computers course that borrowed from the Hewlett-Packard Interface Bus (HP-IB). While we all called the protocol HP-IB, it was already an IEEE standard. Today it is known as IEEE Std 488.1™-2003.
In addition to the normal material that had to be purchased for the class, I also had to buy a copy of the IEEE standard. My first thought was the standard was expensive! When looking inside the standard, it looked more like a someone used an IBM Selectric typewriter to write it and inserted hand-drawn state diagrams. Maybe I bought a draft of the standard instead. This is not at all the IEEE standards of today.
Recently I visited IEEE Xplore and downloaded the current standard and the content, as I would expect, looks nothing like the one I bought for my class. Print was professional as all the standards look today. Even the state diagrams are computer generated.
This was my first IEEE standard I bought, studied and built prototype interfaces to connect. While one might have expected we would have spent 100% of our course time on the application of what we were learning, we did not. We got a dose of indoctrination on the importance of standards. “There may be times in your professional career where you may need to volunteer on standards development: Do it,” we were told.
This is the story I related to those learning SystemVerilog in Noida. I told them the knowledge they gain may prove to be indispensable in the work they do in the years ahead. But thank you for the question on how I got involved in standards, as it reminds me I should encourage you to be mindful of standards in your future. Let me pass on what I learned from Hewlett-Packard that if there is a time in your professional career where you may need to volunteer for standards development: Do it.
My Mentor, In Pectore
In late 2006, my home phone number rings. I answer. “Hi, this is Don Loughry calling on behalf of the IEEE and I have some good news to share with you.” “What is the good news,” I ask. “You have been elected to the IEEE Standards Association Board of Governors. As past chair it is my privilege to bring you this news,” he says. […] “Thank you, I look forward to serving,” I said as I concluded the call.
Many weeks later, my office number rings and I answer. “Hi this is Don Loughry calling. Dennis, is this you,” he asks. “Yes, this is Dennis,” I say. “Did you see the email I sent to you asking if you would join the Charles Proteus Steinmetz awards committee,” he asked. “No, I can’t recall seeing that email. Does your email come in with your first or last name listed,” I asked. “Neither,” Don told me. “You will see my email address as ‘Sunkist,’” he said. “Oh, I thought I got some message from the ‘orange company’ and did not read it. Let me do that now,” I said. And, yes I joined the committee. [From this moment on, Don Loughry was known to me as Sunkist, though I never told him.]
Not too long ago, I related the story of getting involved in standards – the story above – with the now chair of the IEEE SA BoG, Steve Mills. Steve is with Hewlett-Packard Co. and told me that standardization of HP-IB/IEEE 488 was the work of Don Loughry. He was also instrumental in setting a corporate culture that was pro-standardization and Steve told me the encouragement I got to “think standards” while in college is “all Don.”
Interesting, I thought. How I got here has a lot to do with what Don Loughry has done. This was not self evident to me, and kept in secret, in pectore, to me and Don for that matter. Don, my mentor, in pectore.
As you have read the title of the blog, you know there is some sad news to share. This is it:
Don passed away about a month ago. And as I write this, family and friends plan to gather this weekend to remember him. While his life will be recounted by personal and professional accomplishments extraordinaire – and Don’s are certainly substantial by any measure – his ripples on the pond of life continue to radiate and touch many. In my case, his call to volunteer for standards has become my endeavor. As Don has called to action, I have with those I met in Noida in 2009, as I do now with you dear reader of this blog.
Expression of Gratitude
While Don led the development of IEEE 488, he was also key to the development of IEEE 802.3 (the Ethernet LAN standard) that connects 100’s of millions of machines around the world today. We should all be grateful for that.
He launched the IEEE Standards Association and served as its first president. We all benefit from his vision. Standards developers around the globe are grateful for this.
And as for Don appointing me to be a member of the Charles Proteus Steinmetz committee, I went on to be its chair for a couple years. I am grateful for his trust.
As an aside, Don was given the 2003 Steinmetz award. Having been on the committee and its chair, I was offered one action of privilege this year. And that was to appoint myself to be a member of the committee a last time as its past chair. I appointed myself. Thank you Don for your initial appointment to this committee.
The week before last, while in India, after concluding a long week of meetings for the IEEE SA Corporate Advisory Group, it was bittersweet as I dialed into my last Steinmetz committee meeting. I could not finish the call in my hotel room before having to check out and share a ride to the Bangalore airport. Therefore I continued the call on my mobile phone in the car. I thank my friend from Broadcom for sharing his car to the airport with me. And, knowing Broadcom may like 802.3 a bit, perhaps I can be forgiven for this minor annoyance – knowing the rest of the story now. After all, “How did I get here?” How did I become to be on the phone for this call at this moment? In large measure by Don, the same person who helped sow the seeds that Broadcom reaps today with 802.3.
To Sunkist
Yes, I know why Don’s email address has “sunkist” in it. I came to learn why when we were on the Stienmetz committee together when he participated as “past chair.” And no, it is not about oranges. However, oranges will be one of those things that will remind me of him. So why it is his email address that way? Well, let’s say that is one thing I will keep in pectore.
Tags: 1800, 488, 802.3, Don Loughry, Ethernet, Hewlett-Packard, HP-IB, IEEE-SA, Lan, Standards, SystemVerilog, UC Davis
TLM Becomes an IEEE Standard
IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support
A significant step forward to address standards for advanced system-on-chip (SoC) designs has taken place by the IEEE. The IEEE announced the new revision of the SystemC standard, known as IEEE 1666™-2011, has been approved. While it is a revision of the current SystemC standard, IEEE 1666™-2005, the major new feature added was Transaction-Level Modeling (TLM), which is new to an IEEE standard.
For many years now, the TLM specification and accompanying open source code has been incubating in the Open SystemC Initiative (OSCI). OSCI’s TLM Working Group has developed the TLM 1.0 and TLM 2.0 specifications, both of which are part of the revised IEEE 1666 standard. TLM is important to SystemC, but it has also been leveraged outside of it.
We at Mentor Graphics pioneered the use of TLM in SystemVerilog (IEEE 1800™-2009) when our seminal open-source work on the Advanced Verification Methodology (AVM) brought an implementation to the verification community based on SystemVerilog. This lives on today, as AVM motivated the Open Verification Methodology (OVM), which became the basis for Accellera’s Universal Verification Methodology (UVM).
If you don’t already know what TLM is and how the verification community is using it in OVM and UVM, the Verification Academy has a lot of written material and video training modules that will help you learn how this important new IEEE standard is used from simulation to emulation and has boosted verification productivity. The “Understanding TLM” module is featured in the Advanced UVM section, so if you are still a novice to UVM, you may wish to start with the Basic material first. This module is presented by fellow Verification Horizons Blogger, Tom Fitzpatrick and offers subtitles in English, Russian, Japanese and Chinese (Traditional & Simplified) to help drive rapid global adoption.
As we brought TLM into the modern verification methodology practice with a SystemVerilog implementation, it also surfaced that there is an opportunity for the creator of TLM, OSCI, and an adopter of it in UVM, Accellera, to discuss what they could do together. And as I’ve blogged before, those two organizations announced their intention to unite before the end of 2011, as others have seen the potential when both are brought together. I expect to see more great ideas come from these two groups when they join forces, just like the TLM work that is now an IEEE standard.
For those who want a copy of the revised IEEE 1666 standard, it is still in final IEEE editorial review as the they do their last formatting. I will share with you when it is ready to use as well as how to get it and where to find it.
Tags: 1666, 1800, accellera, IEEE-SA, OSCI, OVM, Standards, systemc, SystemVerilog, TLM, TLM 1.0, TLM 2.0, UVM, Verification Academy
Verification Issues Take Center Stage
Is Legacy Holding You Back?
Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on the pressing SoC verification issues as he highlights recent research he has been reporting on in his numerous blogs. The first event will be held in San Jose, CA USA (18 October 2011) and the second event will be held in Reading, UK (15 November 2011).
Harry has been reporting on the 2010 Wilson Research Group Functional Verification Study that has shown a rapid market move towards the broadly supported SystemVerilog (IEEE 1800) language standard and ubiquitous support of the OVM/UVM methodologies. While humans have a general disdain for change, human nature also seems to wait to respond to the “crowd effect” to make a change. It appears the market is in the throes of this strain as the market moves in a direction leaving legacy behind.
To learn firsthand from Harry, I recommend attending two upcoming events where he will speak:
Date: 18 October 2011 (Tuesday)
Event: Design & Verification in the SoC Era
Location: DoubleTree – San Jose, CA USA
Website: http://www.mentor.com/events/verification/
Cost: Free; registration restrictions apply
Date: 15 November 2011 (Tuesday)
Event: Verification Futures: The Next Five Years
Location: Hilton Hotel, Reading, UK
Website: http://verificationfutures2011.eventbrite.com/
Cost: Free
Legacy set for replacement?
Have you ever noticed that one restaurant alone may get little traffic, but if there are many restaurants clustered together, they garner much greater traffic than going it alone? The crowd effect demonstrates its power and user benefit with choice and bounty. After DVCon 2011, I blogged about Wally Rhines’ keynote address and pointed to one slide that showed SystemVerilog is the clear language winner and pointed to another slide that showed OVM/UVM, built on top of SystemVerilog, as the clear methodology winner.
This has impact on legacy. And those with entrenched legacy may find it hard to adopt market driven standards practice quickly. This is to be expected.
When Accellera began its Verification IP Technical Subcommittee (VIP-TSC), I argued that the first step is to preserve legacy investment and offer a path to reuse that which has proven valuable in the past. The vote to move in this direction was close with consumer input saying all efforts should focus on a single industry supported base class library and standard. My point was we could build it, but if there was no path from where consumers were, there would be limited uptake. In a short time, a proof that OVM and VMM could interoperate demonstrated that we knew how to do this. It also gave hope that other proprietary and single-supplier solutions could take this work and adapt it for their paths forward.
With that finished, the Accellera VIP-TSC set to create the Universal Verification Methodology (UVM) standard. This has now been completed, short of finishing one commitment to expand the Phasing scheme and address a few lingering issues. While Accellera could focus on completing this work, users and owners of legacy verification languages and proprietary environments have come to realize a startling truth: the market has moved away from them. And, proprietary and single-solution suppliers have offered little in terms of paths forward. They now look for Accellera to address legacy preservation requirements and do it for them.
While this was to be expected, their shock has exposed the fact that more work could have been done on building the bridges to legacy’s past in the initial phase rather than now when the market demands time and focus on its adopted standards practice instead.
Why bring all this up?
We now find the Accellera VIP-TSC has a bifurcated focus. Part of the focus is to complete the content promises for UVM 1.0 and the other is to preserve legacy investment. But can Accellera overcome the crowd effect? The crowd effect, after all, has taken hold. In terms of product choice, legacy offers one product from a single supplier to SystemVerilog’s multiple competitive suppliers. When it comes to bounty, the availability of legacy verification IP has fewer and fewer sources while OVM/UVM offer an expanding bounty.
In the face of this rapid market move, one can expect single solution suppliers will extol features of their solution over the market’s choice. Users faced with the grim prospect of having to adapt to market changes will praise the past in hopes others will depart from the crowd. I am at a loss to think of a time when actions like this have worked to change the market. Maybe someone knows of examples and can share them.
In fact, I was a user who praised the technical benefits of one format over another. I made further investments in it. I even moved to a new job in a new area to find the community I moved to seemed to favor my selected format equally with what was to be the market winner. In time, in very short time, even my new community gave way to the market and the crowd. Can you guess what that format was?
I will share the details this with you next week when I discuss how one might actually bring value to legacy while allowing the market to continue its move forward. In the meantime, if you are close to the San Jose, CA or Reading, UK events, I suggest you register to attend.
Tags: 1800, accellera, IEEE, OVM, Standards, SystemVerilog, UVM, vip-tsc, vmm
Accellera & OSCI Unite
System Standards Worlds Initiate Unification
Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC have made known their intent to unite to form a single front-end electronic design automation (EDA) standards organization. You can read their joint press release here.
While this may come as a surprise to many, one thing has remained constant for many years: the two organizations have had a long standing policy of collaborative interactions as both have evolved their standards programs. At a DATE 2004 panel titled “SystemC and SystemVerilog: Where do they fit? Where are they going?,” technical members of the two communities gathered to ponder answers to those questions. At DAC 2004, when I was chair of Accellera and Guido Arnout was chair of OSCI, we stood before a large assembly of SystemC users a few months later to point to what was not so obvious to many, SystemVerilog and SystemC complement each other.
Guido and I dispelled any issues of a “language war” and focused on what the value each language and what it delivered to the design and verification community. A lot has transpired since then. Both SystemC and SystemVerilog are now IEEE standards, know as IEEE Std. 1666™ and IEEE Std. 1800™ respectively. And both OSCI and Accellera have continued to evolve their standards work program in significant and meaningful ways.
In this evolution, it became clear to me that each organization was “completing” the other. OSCI has developed the popular Transaction Level Modeling (TLM) standards and Accellera had adopted TLM in their Universal Verification Methodology (UVM™). As the technical teams from each organization have leveraged each other, it began to make more sense to initiate discussions to unite the two groups to address further front-end EDA standards challenges – as one. And, indeed, the two organization recognized this and have taken the steps to determine how best to combine operations into a single organization.
In the months ahead, the unified organization will emerge, but for now, it is business as usual for the standards development teams in OSCI and Accellera.
What do you think about the unification?
Tags: 1666, 1800, accellera, dac, DATE, IEEE, OSCI, systemc, SystemVerilog, TLM, UVM
The IEEE’s Most Popular EDA Standards
How do your favorites rank?
Have you ever wondered how popular the different IEEE standards for electronic design automation are? Have you ever wondered which ones show the least interest? When buying books online, popular book buying websites sites will rank customer purchases. Many newspapers manage lists that you can consult to determine what is the most popular; what has the highest demand. But if you have purchased any IEEE standards, you will know this information is not available from the IEEE Store or the IEEE XPlore platform.
On May 4th, the IEEE Standards Association announced its collaboration with Techstreet to create the New IEEE Standards Store. Until now, anyone who wanted to order a single standard had to use a more complex system that even made it hard to share a permanent link to one’s favorite standard with another. Just look at the Accellera homepage for an example of where to get the SystemVerilog (IEEE Std. 1800™) standard. At the writing of this blog, it simply points to www.ieee.org. [I will share the fact the IEEE’s new site now has fixed links that can now be used to help others find the most current SystemVerilog standard with the Accellera.]
But back to what is the most popular IEEE EDA standards… Any guesses?
Before I delve into those details, let me say the ranking is just by ordinal. The New IEEE Standards Store shares no information on the actual number of standards purchased. So the difference between #1 and #10 could be just 10 copies. It probably isn’t, but it could be. But talking about #10, why is it even on the list? The IP-XACT standard (IEEE Std. 1685™) is available for free under the IEEE Get Program. Under this program you can download a PDF of the IEEE standard for free. If you want a printed version, you can print your own copy from the free one you download. Back in December 2010, Accellera reported that since the IEEE started to offer IP-XACT for free, there had been 1200 downloads. It also looks like many people did not want the hassle to print and simply ordered the print version directly from the IEEE. The other IEEE EDA standard offered free is SystemC© And this is probably the reason it is in 32nd place. It is very popular in terms of the number of free downloads.
And yes, if you search for the those two standards on the New IEEE Standards Store, you will find you can order print copies there and if you read the small print below, you will see there is a link to take you to the free online versions.
Harry Foster has issued several research reports on the popularity of one language or format the past several months. In his last blog, he discussed which of the design and verification languages are ranked high and those, well, not so high. And I guess I feel best to share the correlation between his findings and these more “anecdotal” results from the New IEEE Standards Store. I have been party to many at the top standards (Verilog/SystemVerilog) and party to the “least highest” (yes, I can’t say the least liked) VITAL 2000. For vindication, I will note that VITAL-95 comes in at #18. In whole, it appears to me that the New IEEE Standards Store ordinal rankings of EDA standards matches the scientific data from the research Harry has reported.
Below is the full ranking of IEEE EDA standards. Where are your favorites?
| 1 | IEEE 1364-2001 | Verilog Hardware Description Language |
| 2 | IEEE 1800-2009 | SystemVerilog–Unified Hardware Design, Specification, and Verification Language |
| 3 | IEEE 1076-2002 | VHDL Language Reference Manual |
| 4 | IEEE 1076-1993 | VHDL Language Reference Manual |
| 5 | IEEE 1499-1998 | Interface for Hardware Description Models of Electronic Components |
| 6 | IEEE 1364-1995 | Hardware Description Language Based on the Verilog® Hardware Description Language |
| 7 | IEEE 1800-2005 | SystemVerilog: Unified Hardware Design, Specification and Verification Language |
| 8 | IEEE 1076.2-1996 | VHDL Mathematical Packages |
| 9 | IEEE 1076.1-1999 | VHDL Analog and Mixed-Signal Extensions |
| 10 | IEEE 1685-2009 | IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows |
| 11 | IEEE 1850-2005 | Property Specification Language (PSL) |
| 12 | IEEE 1076c-2007 | VHDL Language Reference Manual – Procedural Language Application Interface |
| 13 | IEEE 1164-1993 | Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164) |
| 14 | IEEE 1850-2010 | Property Specification Language (PSL) |
| 15 | IEEE 1076.6-2004 | VHDL Register Transfer Level (RTL) Synthesis |
| 16 | IEEE 1801-2009 | Design and Verification of Low Power Integrated Circuits |
| 17 | IEEE 1481-2009 | Integrated Circuit (IC) Open Library Architecture (OLA) |
| 18 | IEEE 1076.4-1995 | VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification |
| 19 | IEEE/IEC 61691-5-2004 | IEC 61691-5 Ed.1 (IEEE Std 1076.4(TM)-2000): Behavioural Languages – Part 5: Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification |
| 20 | IEEE 1647-2008 | Functional Verification Language e |
| 21 | IEEE 1076.1.1-2011 | VHDL Analog and Mixed-Signal Extensions — Packages for Multiple Energy Domain Support |
| 22 | IEEE/IEC 61691-7-2009 | Behavioural languages – Part 7: SystemC Language Reference Manual |
| 23 | IEEE 1076-1987 | VHDL Language Reference Manual |
| 24 | IEEE 1076.1.1-2004 | VHDL Analog and Mixed-Signal Extensions—Packages for Multiple Energy Domain Support |
| 25 | IEEE 1076.3-1997 | VHDL Synthesis Packages |
| 26 | IEEE/IEC 61523-3-2004 | IEC 61523-3 Ed.1 (IEEE Std 1497(TM)-2001): Delay and Power Calculation Standards – Part 3: Standard Delay Format (SDF) for the Electronic Design Process |
| 27 | IEEE 1076/INT-1991 | Interpretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual |
| 28 | IEEE/IEC 62531-2007 | IEC 62531 Ed. 1 (2007-11) (IEEE Std 1850-2005): Standard for Property Specification Language (PSL) |
| 29 | IEEE 1076.6-1999 | VHDL Register Transfer Level Synthesis |
| 30 | IEEE 1647-2006 | Functional Verification Language “e” |
| 31 | IEEE/IEC 61691-6-2009 | Behavioural languages – Part 6: VHDL Analog and Mixed-Signal Extensions |
| 32 | IEEE 1666-2005 | SystemC® Language Reference Manual |
| 33 | IEEE/IEC 61691-1-1-2004 | IEC 61691-1-1 Ed.1 (IEEE Std 1076(TM)-2002): Behavioural Languages – Part 1-1: VHDL Language Reference Manual |
| 34 | IEEE 1364-2005 | Verilog Hardware Description Language |
| 35 | IEEE/IEC 61691-4-2004 | IEC 61691-4 Ed.1 (IEEE Std 1364(TM)-2001): Behavioural Languages – Part 4: Verilog® Hardware Description Language |
| 36 | IEEE 1076.4-2000 | VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification |
Learn more about the New IEEE Standards Store
There is much more to the New IEEE Standards Store than just the rankings of the standards we use in electronic design automation. As I mentioned, it is easier to share fixed links to IEEE standards. And if you want to track IEEE standards development – and don’t want to have to register your email address with the actual committee developing it just to know when they are done and a standard is ready – you can register to be notified when a new standard is ready. The New IEEE Standards Store will notify you when a new one is ready.
Check out the short, one minute, video below to learn more about the New IEEE Standards Store.
Tags: 1076, 1076.4, 1364, 1800, IEEE, IP-XACT, Standards, systemc, SystemVerilog, verilog, vhdl, VITAL
Part 8: The 2010 Wilson Research Group Functional Verification Study
Language and Library Trends
This blog is a continuation of a series of blogs, which present the highlights from the 2010 Wilson Research Group Functional Verification Study (for a background on the study, click here).
In my previous blog (Part 7 click here), I focused on some of the 2010 Wilson Research Group findings related to testbench characteristics and simulation strategies. In this blog, I present design and verification language trends, as identified by the Wilson Research Group study.
You might note for some of the language and library data I present, the percentage sums to more than one hundred percent. The reason for this is that some perticipant’s projects use multiple languages and multiple methodologies.
Design Languages
Let’s begin by examining the languages used for design, as shown in Figure 1. Here, we compare the results for languages used to design FPGAs (in grey) with languages used to design non-FPGAs (in green).
Figure 1. Languages used for design
Not too surprising, we see that VHDL is the most popular language used for the design of FPGAs, while Verilog and SystemVerilog are the most popular languages used for the design of non-FPGAs.
Figure 2 shows the trends in terms of languages used for design, by comparing the 2007 Far West Research study (in blue) with the 2010 Wilson Research Group study (in green), as well as the projected design language adoption trends within the next twelve months (in purple). Note that the design language adoption is declining for most of the languages with the exception of SystemVerilog whose adoption is increasing.
Figure 2. Trends in languages used for design
Verification Languages
Next, let’s look at the languages used for verification (that is, languages used to create simulation testbenches). Figure 3 compares the results between FPGA designs (in grey) and non-FPGA designs (in green). 
Figure 3. Languages used in verification to create simulation testbenches
And again, it’s not too surprising to see that VHDL is the most popular language used to create verification testbenches for FPGAs, while SystemVerilog is the most popular language used to create testbenches for non-FPGAs.
Figure 4 shows the trends in terms of languages used to create simulation testbenches by comparing the 2007 Far West Research study (in blue) with the 2010 Wilson Research Group study (in green), as well as the projected language adoption trends within the next twelve months (in purple). Note that verification language adoption is declining for most of the languages with the exception of SystemVerilog whose adoption is increasing.
Figure 4. Trends in languages used in verification to create simulation testbenches
Now, let’s look at methodology and class library adoption. Figure 5 shows the future trends in terms of methodology and class library adoption by comparing the 2010 Wilson Research Group study (in green) with the projected adoption trends within the next twelve months (in purple). Previous studies did not include data on methodology and class library adoption, so we are unable to show previous trends.
Figure 5. Methodology and class library future trends
The study indicates that the only methodology adoption projected to grow in the next twelve months are OVM and UVM.
Assertion Languages and Libraries
Finally, let’s examine assertion language and library adoption, as shown in Figure 6. Here, we compare the results for FPGA designs (in grey) and non-FPGA designs (in green).
Figure 6. Assertion language and library adoption
SystemVerilog Assertions (SVA) is the most popular assertion language used for both FPGA and non-FPGA designs.
Figure 7 shows the trends in terms assertion language and library adoption by comparing the 2007 Far West Research study (in blue) with the 2010 Wilson Research Group study (in green), as well as the projected adoption trends within the next twelve months (in purple). Note that the adoption of most of the assertion languages is declining, with the exception of SVA whose adoption is increasing.
Figure 7. Trends in assertion language and library adoption
In my next blog (click here), I plan to focus on the adoption of various verification technologies and techniques used in the industry, as identified by the 2010 Wilson Research Group study.
Tags: 1076, 1364, 1666, 1800, accellera, Add new tag, Assertion-Based Verification, functional verification, IEEE 1800, OVM, Standards, SystemVerilog, UVM, Verification Methodology, verilog, vhdl, vmm
IEEE Standards in India
IEEE Standards Association Hosts Design Automation Standardization Workshops in Bangalore & Delhi
I, along with several other individuals, will participate in two IEEE-SA EDA standardization workshops in India on Friday, 4 February 2011 in Bangalore and on Thursday 10 February 2011 in New Delhi. In the last year, the IEEE announced it opened an office in Bangalore, India. This is the fourth IEEE office in Asia, following China, Japan and Singapore.
A large number of IEEE’s members reside in India and the EDA standards get a lot of use and attention in India. There is a strong and thriving IEEE Std 1800™ SystemVerilog community in India that are helping to extend the verification capabilities of the language. As the IEEE office gets setup, I look forward to it to help better coordinate standards development of a global community of companies and individuals.
Agenda: Bangalore, India Workshop (Register)
Location: Mentor Graphics, Bangalore
| 8:30 | Registration opens | |
| 9:00 | Welcome–Pamela Kumar (IBM) | |
| 9:05 | IEEE-SA and the World of Standards Dennis Brophy, Member, Board of Governors, IEEE-SA Director of Business Development, Mentor Graphics |
|
| 9:45 | Standards in Design Automation: Influencing Design and Verification Methodologies Low power (1801); Design & Verification productivity (1800, 1735); System Design (1666) Yatin Trivedi, Member, Standards Education Committee, IEEE-SA Director of Standards, Synopsys |
|
| 10:30 | Tea-Break | |
| 11:00 | Impact of Standards in Design Environment Sri Chandra, Chair, Standards Interest Group, India Chapter, IEEE-SA CAD Manager, Freescale |
|
| 11:30 | Anecdotes of Participation in Standards Activities Srinivasan Venkataramanan, CTO, CVC, Bangalore |
|
| 11:45 | Panel Discussion: Standards, Industry and Academia Moderator: Pamela Kumar Participants: Dennis Brophy, Yatin Trivedi, Sri Chandra, Srini Venkataramanan, Anuradha Srinivasan (Intel) |
|
| 12:30 | Conclusion & Thank You |
A set of IEEE-SA Board of Governors meetings will be held at the beginning of the the week of February 7th. And in addition to the meeting on design automation standards in Bangalore, a group of workshops are also planned in Mumbai on 4 February 2011 on Cloud Computing and Smart Grid by other colleagues I volunteer with on the IEEE-SA Board of Governors. There are more IEEE-SA events planned for the week of February 7th and a full list can be found here.
For those who wish to join the New Delhi design automation workshop, some details of it can be found below.
Agenda: New Delhi, India Workshop (Register)
Location: IIT
| 8:30 | Registration opens | |
| 9:00 | Welcome—Karen Bartleson (Synopsys) | |
| 9:05 | IEEE-SA and the World of Standards Dennis Brophy, Member, Board of Governors, IEEE-SA Director of Business Development, Mentor Graphics |
|
| 9:45 | Standards in Design Automation: Influencing Design and Verification Methodologies Low power (1801); Design & Verification productivity (1800, 1735); System Design (1666) Yatin Trivedi, Member, Standards Education Committee, IEEE-SA Director of Standards, Synopsys |
|
| 10:30 | Tea-Break | |
| 11:00 | Impact of Standards in Design Environment Sri Chandra, Chair, Standards Interest Group, India Chapter, IEEE-SA CAD Manager, Freescale |
|
| 11:30 | Anecdotes of Participation in Standards Activities Srinivasan Venkataramanan, CTO, CVC, Bangalore |
|
| 11:45 | Panel Discussion: Standards, Industry and Academia Moderator: Karen Bartleson Participants: Dennis Brophy, Yatin Trivedi, Sri Chandra |
|
| 12:30 | Conclusion & Thank You |
Tags: 1666, 1735, 1800, 1801, IEEE-SA, Standards, systemc, SystemVerilog, upf
IEC’s 47th General Assembly Meeting Opens
United States Plays Host in Seattle, WA
The IEC’s 47th General Assembly meeting opened on October 11th in Seattle, WA USA. Plans had been put in place for about 2,500 delegates but that number was exceeded by nearly 25% with more than 3,100 people registered. Three days before the start of the meeting the Technical Committee 93, which addresses all the design automation standards held seven working group meetings from Friday-Sunday. On Monday the group reported out conclusions of all the committee’s working groups.
Working Group 2 manages the process to promote dual-logo standards development between the IEEE and IEC for design languages and may be of particular interest to VHDL, Verilog, SystemVerilog and SystemC users. In addition to the responsibility to manage design language dual-logo standards, WG 2 has maintenance responsibility for IBIS, the I/O Buffer Information Specification. IBIS 4.2 is on the work plan for standardization. The Japanese National Committee’s technical report from JEITA on their Bird’s eye View of Design Language (BVDL) was also submitted as an official submission.
The TC 93 addresses a broad spectrum of standards for the design automation of electronic devices ranging from printed circuit boards and systems to semiconductor devices and systems. From that broad swath of interests, two dual-logo candidates germane to language-based design flows were on the agenda for consideration by the IEC Standards Management Board (SMB).
Specifically, IEEE Std 1076-2008 and IEEE Std 1800-2009 were approved by the SMB at the start of the meeting series on 11 October 2010 as dual-logo standards. For those who purchase their standards from the IEC or their national standards bodies, the VHDL standard is known as IEC 61691-1-1 Ed. 2.0 (2010) and the SystemVerilog standard is known as IEC 62530 Ed. 2.0 (2010). The content between the IEEE and IEC are the same with the exception of the cover page of the standard, which will carry both the IEEE and IEC logo. Different countries have different rules and laws to recognize standards. The IEC plays a key role to bridge these differences to promote efficient and effective global use of VHDL, Verilog, SystemVerilog, SystemC and more.
Tags: 1076, 1364, 1666, 1800, dual-logo, iec, IEEE, Standards, systemc, SystemVerilog, TC93, verilog, vhdl, WG2
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
Latest Posts
- Texas-Sized DAC Edition of Verification Horizons Now Up on Verification Academy
- IEEE 1801™-2013 UPF Standard Is Published
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study





