Posts Tagged ‘1666’
OVM Gets Connected
OVM Bridges SystemVerilog and SystemC Languages
When UVM Connect was first released, the multilingual connection between IEEE Std. 1800™ (SystemVerilog) and IEEE Std. 1666™ (SystemC) standards bridged the two languages to allow design and verification engineers to access UVM from SystemC or SystemVerilog to exploit native languages advantages. OVM users wondered if it was possible to support them as well since OVM is a derived from UVM.
It is possible and UVM Connect has been extended to allow OVM users to enjoy the same benefits. An update to UVM Connect now allows it to be compiled to run with the OVM. And since the extensions are based on IEEE standards, they can be used in your simulator of choice.
OVM Thrives
The thriving OVM community is of no surprise. Last year, Harry Foster blogged about research on the use and adoption of verification methodologies. The research was done after UVM was established as an Accellera standard, and showed OVM continued its leading position as shown in one of the charts from Harry’s blog (see below). The chart even showed OVM was predicted to have a modest growth in adoption as well.
Mentor continues to bring many of the UVM additions back to the OVM user community in a way that does not disturb the upgrade path from OVM to UVM. The major addition to UVM in the first round of Accellera standardization was the addition of a register and memory package. This was back ported to OVM. (The OVM register and memory kit can be found here, if you are interested.) Now, UVM Connect has been extended to provide full OVM use.
Download
The UVM Connect 2.2 kit supports multilingual use of OVM and can be found at the Verification Academy and the Accellera UVM World contributions download site.
If you find issues or have other suggestions that we should consider, you can always share your input at the OVM Forum or UVM Forum. In addition to interacting with other users, the Verification Academy is a good site for online resources like the UVM/OVM Cookbook, basic and advanced OVM/UVM training, and more.
Tags: 1666, 1800, accellera, IEEE, Multilanguage OVM, Multilanguage UVM, OVM, Standards, systemc, SystemVerilog, UVM, UVM Connect
SystemC Standardization Cycle Completes
Open-Source Proof-of-Concept Library Released
Accellera Systems Initiative has released for general industry use an open-source proof-of-concept library as a companion to the recently minted IEEE Std. 1666™-2011, SystemC Language Reference Manual standard
In November 2011, the IEEE Standards Association approved IEEE Std. 1666-2011. The completed and published standard was made available to the community as a whole for free in an agreement between Accellera Systems Initiative and the IEEE Standards Association in February 2012. As a reminder, you can download your personal copy of IEEE 1666 here for free.
In the nearly 6 months since this version of the standard has been available about 7,000 copies have been downloaded under the IEEE Get program.
The previous version was also made available for free download and was just as popular as this version of the standard is.
While the approved standard was being made ready for publication, Accellera Systems Initiative was also busy completing the open-source proof-of-concept library. After taking comments and feedback from a public review process, version 2.3.0 of the library was completed and is now available.
IEEE 1666-2011 added a number of important new features, including support for transaction-level modeling (TLM) that has proven to be an important element to enable high-level design and is a key component upon which the Universal Verification Methodology (UVM) is built from.
For those who want to used the SystemC library directly, it is now available for wide industry access.
Download Resources
The downloads from the IEEE and Accellera Systems Initiative will require some license agreement approvals. The links are not one-click access to the material below.
- IEEE 1666-2011 Standard
All who download will need to agree to a click-through IEEE license and declare a “user type.” - SystemC 2.3.0 Open-Source Proof-of-Concept Library
Non-members need to register as a “community participant” in order to download the library and regression tests.
Tags: 1666, Accellera Systems Initiative, IEEE, open-source, proof-of-concept library, Standards, systemc, UVM
TLM Becomes an IEEE Standard
IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support
A significant step forward to address standards for advanced system-on-chip (SoC) designs has taken place by the IEEE. The IEEE announced the new revision of the SystemC standard, known as IEEE 1666™-2011, has been approved. While it is a revision of the current SystemC standard, IEEE 1666™-2005, the major new feature added was Transaction-Level Modeling (TLM), which is new to an IEEE standard.
For many years now, the TLM specification and accompanying open source code has been incubating in the Open SystemC Initiative (OSCI). OSCI’s TLM Working Group has developed the TLM 1.0 and TLM 2.0 specifications, both of which are part of the revised IEEE 1666 standard. TLM is important to SystemC, but it has also been leveraged outside of it.
We at Mentor Graphics pioneered the use of TLM in SystemVerilog (IEEE 1800™-2009) when our seminal open-source work on the Advanced Verification Methodology (AVM) brought an implementation to the verification community based on SystemVerilog. This lives on today, as AVM motivated the Open Verification Methodology (OVM), which became the basis for Accellera’s Universal Verification Methodology (UVM).
If you don’t already know what TLM is and how the verification community is using it in OVM and UVM, the Verification Academy has a lot of written material and video training modules that will help you learn how this important new IEEE standard is used from simulation to emulation and has boosted verification productivity. The “Understanding TLM” module is featured in the Advanced UVM section, so if you are still a novice to UVM, you may wish to start with the Basic material first. This module is presented by fellow Verification Horizons Blogger, Tom Fitzpatrick and offers subtitles in English, Russian, Japanese and Chinese (Traditional & Simplified) to help drive rapid global adoption.
As we brought TLM into the modern verification methodology practice with a SystemVerilog implementation, it also surfaced that there is an opportunity for the creator of TLM, OSCI, and an adopter of it in UVM, Accellera, to discuss what they could do together. And as I’ve blogged before, those two organizations announced their intention to unite before the end of 2011, as others have seen the potential when both are brought together. I expect to see more great ideas come from these two groups when they join forces, just like the TLM work that is now an IEEE standard.
For those who want a copy of the revised IEEE 1666 standard, it is still in final IEEE editorial review as the they do their last formatting. I will share with you when it is ready to use as well as how to get it and where to find it.
Tags: 1666, 1800, accellera, IEEE-SA, OSCI, OVM, Standards, systemc, SystemVerilog, TLM, TLM 1.0, TLM 2.0, UVM, Verification Academy
Accellera & OSCI Unite
System Standards Worlds Initiate Unification
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Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC have made known their intent to unite to form a single front-end electronic design automation (EDA) standards organization. You can read their joint press release here.
While this may come as a surprise to many, one thing has remained constant for many years: the two organizations have had a long standing policy of collaborative interactions as both have evolved their standards programs. At a DATE 2004 panel titled “SystemC and SystemVerilog: Where do they fit? Where are they going?,” technical members of the two communities gathered to ponder answers to those questions. At DAC 2004, when I was chair of Accellera and Guido Arnout was chair of OSCI, we stood before a large assembly of SystemC users a few months later to point to what was not so obvious to many, SystemVerilog and SystemC complement each other.
Guido and I dispelled any issues of a “language war” and focused on what the value each language and what it delivered to the design and verification community. A lot has transpired since then. Both SystemC and SystemVerilog are now IEEE standards, know as IEEE Std. 1666™ and IEEE Std. 1800™ respectively. And both OSCI and Accellera have continued to evolve their standards work program in significant and meaningful ways.
In this evolution, it became clear to me that each organization was “completing” the other. OSCI has developed the popular Transaction Level Modeling (TLM) standards and Accellera had adopted TLM in their Universal Verification Methodology (UVM™). As the technical teams from each organization have leveraged each other, it began to make more sense to initiate discussions to unite the two groups to address further front-end EDA standards challenges – as one. And, indeed, the two organization recognized this and have taken the steps to determine how best to combine operations into a single organization.
In the months ahead, the unified organization will emerge, but for now, it is business as usual for the standards development teams in OSCI and Accellera.
What do you think about the unification?
Tags: 1666, 1800, accellera, dac, DATE, IEEE, OSCI, systemc, SystemVerilog, TLM, UVM
Part 8: The 2010 Wilson Research Group Functional Verification Study
Language and Library Trends
This blog is a continuation of a series of blogs, which present the highlights from the 2010 Wilson Research Group Functional Verification Study (for a background on the study, click here).
In my previous blog (Part 7 click here), I focused on some of the 2010 Wilson Research Group findings related to testbench characteristics and simulation strategies. In this blog, I present design and verification language trends, as identified by the Wilson Research Group study.
You might note for some of the language and library data I present, the percentage sums to more than one hundred percent. The reason for this is that some perticipant’s projects use multiple languages and multiple methodologies.
Design Languages
Let’s begin by examining the languages used for design, as shown in Figure 1. Here, we compare the results for languages used to design FPGAs (in grey) with languages used to design non-FPGAs (in green).
Figure 1. Languages used for design
Not too surprising, we see that VHDL is the most popular language used for the design of FPGAs, while Verilog and SystemVerilog are the most popular languages used for the design of non-FPGAs.
Figure 2 shows the trends in terms of languages used for design, by comparing the 2007 Far West Research study (in blue) with the 2010 Wilson Research Group study (in green), as well as the projected design language adoption trends within the next twelve months (in purple). Note that the design language adoption is declining for most of the languages with the exception of SystemVerilog whose adoption is increasing.
Figure 2. Trends in languages used for design
Verification Languages
Next, let’s look at the languages used for verification (that is, languages used to create simulation testbenches). Figure 3 compares the results between FPGA designs (in grey) and non-FPGA designs (in green). 
Figure 3. Languages used in verification to create simulation testbenches
And again, it’s not too surprising to see that VHDL is the most popular language used to create verification testbenches for FPGAs, while SystemVerilog is the most popular language used to create testbenches for non-FPGAs.
Figure 4 shows the trends in terms of languages used to create simulation testbenches by comparing the 2007 Far West Research study (in blue) with the 2010 Wilson Research Group study (in green), as well as the projected language adoption trends within the next twelve months (in purple). Note that verification language adoption is declining for most of the languages with the exception of SystemVerilog whose adoption is increasing.
Figure 4. Trends in languages used in verification to create simulation testbenches
Now, let’s look at methodology and class library adoption. Figure 5 shows the future trends in terms of methodology and class library adoption by comparing the 2010 Wilson Research Group study (in green) with the projected adoption trends within the next twelve months (in purple). Previous studies did not include data on methodology and class library adoption, so we are unable to show previous trends.
Figure 5. Methodology and class library future trends
The study indicates that the only methodology adoption projected to grow in the next twelve months are OVM and UVM.
Assertion Languages and Libraries
Finally, let’s examine assertion language and library adoption, as shown in Figure 6. Here, we compare the results for FPGA designs (in grey) and non-FPGA designs (in green).
Figure 6. Assertion language and library adoption
SystemVerilog Assertions (SVA) is the most popular assertion language used for both FPGA and non-FPGA designs.
Figure 7 shows the trends in terms assertion language and library adoption by comparing the 2007 Far West Research study (in blue) with the 2010 Wilson Research Group study (in green), as well as the projected adoption trends within the next twelve months (in purple). Note that the adoption of most of the assertion languages is declining, with the exception of SVA whose adoption is increasing.
Figure 7. Trends in assertion language and library adoption
In my next blog (click here), I plan to focus on the adoption of various verification technologies and techniques used in the industry, as identified by the 2010 Wilson Research Group study.
Tags: 1076, 1364, 1666, 1800, accellera, Add new tag, Assertion-Based Verification, functional verification, IEEE 1800, OVM, Standards, SystemVerilog, UVM, Verification Methodology, verilog, vhdl, vmm
SystemC Day 2011 Videos Available Now
Watch DVCon Co-Located Event Presentations
Two presentations from the second annual SystemC Day at DVCon 2011 are available now. The first presentation is the keynote by Jim Hogan, serial EDA entrepreneur at Vista Ventures, LLC and the second is an introduction to the emerging IEEE Std. 1666™, SystemC standard by Jim Aynsley at Doulos. SystemC Day brought users together to discuss the current state of the market for ESL design and the pending content of the SystemC standard that is current in final ballot by the IEEE.
To view the video presentations, you will need to register with the Open SystemC Initiative.
Jim Hogan, Vista Ventures LLC, California, USA
Keynote Presentation: “Navigating the SoC Era”
Abstract: SoCs are becoming ubiquitous in semiconductor development. Further, these SoCs are no longer processor-centric, and they are differentiated through the integration of design elements such as multi-CPU, multi-core, DSP cores, hardware accelerators, peripherals and software.
Industry expert and private investor Jim Hogan will discuss the semiconductor industry’s growing adoption of SoC design, and its reliance on diverse sources of hardware and software IP, developed both internally and externally.
John Aynsley, Doulos Ltd., UK
The New IEEE 1666 SystemC Standard
Abstract: The IEEE SystemC Standard is currently being revised and updated, with the new standard due to be published later in 2011. This new version of the SystemC standard will for the first time include the TLM-1 and TLM-2.0 libraries. Meanwhile, OSCI is working to ensure that the SystemC Proof-of-Concept simulator tracks any changes to the IEEE standard. This presentation will give a concise technical summary of the most important new and revised features in the SystemC standard, will give a behind-the-scenes insight into the rationale behind the changes, and will show examples to illustrate the new features in action.
Tags: 1666, esl, IEEE, Jim Aynsley, Jim Hogan, OSCI, SoC, systemc
IEEE Standards in India
IEEE Standards Association Hosts Design Automation Standardization Workshops in Bangalore & Delhi
I, along with several other individuals, will participate in two IEEE-SA EDA standardization workshops in India on Friday, 4 February 2011 in Bangalore and on Thursday 10 February 2011 in New Delhi. In the last year, the IEEE announced it opened an office in Bangalore, India. This is the fourth IEEE office in Asia, following China, Japan and Singapore.
A large number of IEEE’s members reside in India and the EDA standards get a lot of use and attention in India. There is a strong and thriving IEEE Std 1800™ SystemVerilog community in India that are helping to extend the verification capabilities of the language. As the IEEE office gets setup, I look forward to it to help better coordinate standards development of a global community of companies and individuals.
Agenda: Bangalore, India Workshop (Register)
Location: Mentor Graphics, Bangalore
| 8:30 | Registration opens | |
| 9:00 | Welcome–Pamela Kumar (IBM) | |
| 9:05 | IEEE-SA and the World of Standards Dennis Brophy, Member, Board of Governors, IEEE-SA Director of Business Development, Mentor Graphics |
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| 9:45 | Standards in Design Automation: Influencing Design and Verification Methodologies Low power (1801); Design & Verification productivity (1800, 1735); System Design (1666) Yatin Trivedi, Member, Standards Education Committee, IEEE-SA Director of Standards, Synopsys |
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| 10:30 | Tea-Break | |
| 11:00 | Impact of Standards in Design Environment Sri Chandra, Chair, Standards Interest Group, India Chapter, IEEE-SA CAD Manager, Freescale |
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| 11:30 | Anecdotes of Participation in Standards Activities Srinivasan Venkataramanan, CTO, CVC, Bangalore |
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| 11:45 | Panel Discussion: Standards, Industry and Academia Moderator: Pamela Kumar Participants: Dennis Brophy, Yatin Trivedi, Sri Chandra, Srini Venkataramanan, Anuradha Srinivasan (Intel) |
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| 12:30 | Conclusion & Thank You |
A set of IEEE-SA Board of Governors meetings will be held at the beginning of the the week of February 7th. And in addition to the meeting on design automation standards in Bangalore, a group of workshops are also planned in Mumbai on 4 February 2011 on Cloud Computing and Smart Grid by other colleagues I volunteer with on the IEEE-SA Board of Governors. There are more IEEE-SA events planned for the week of February 7th and a full list can be found here.
For those who wish to join the New Delhi design automation workshop, some details of it can be found below.
Agenda: New Delhi, India Workshop (Register)
Location: IIT
| 8:30 | Registration opens | |
| 9:00 | Welcome—Karen Bartleson (Synopsys) | |
| 9:05 | IEEE-SA and the World of Standards Dennis Brophy, Member, Board of Governors, IEEE-SA Director of Business Development, Mentor Graphics |
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| 9:45 | Standards in Design Automation: Influencing Design and Verification Methodologies Low power (1801); Design & Verification productivity (1800, 1735); System Design (1666) Yatin Trivedi, Member, Standards Education Committee, IEEE-SA Director of Standards, Synopsys |
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| 10:30 | Tea-Break | |
| 11:00 | Impact of Standards in Design Environment Sri Chandra, Chair, Standards Interest Group, India Chapter, IEEE-SA CAD Manager, Freescale |
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| 11:30 | Anecdotes of Participation in Standards Activities Srinivasan Venkataramanan, CTO, CVC, Bangalore |
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| 11:45 | Panel Discussion: Standards, Industry and Academia Moderator: Karen Bartleson Participants: Dennis Brophy, Yatin Trivedi, Sri Chandra |
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| 12:30 | Conclusion & Thank You |
Tags: 1666, 1735, 1800, 1801, IEEE-SA, Standards, systemc, SystemVerilog, upf
IEC’s 47th General Assembly Meeting Opens
United States Plays Host in Seattle, WA
The IEC’s 47th General Assembly meeting opened on October 11th in Seattle, WA USA. Plans had been put in place for about 2,500 delegates but that number was exceeded by nearly 25% with more than 3,100 people registered. Three days before the start of the meeting the Technical Committee 93, which addresses all the design automation standards held seven working group meetings from Friday-Sunday. On Monday the group reported out conclusions of all the committee’s working groups.
Working Group 2 manages the process to promote dual-logo standards development between the IEEE and IEC for design languages and may be of particular interest to VHDL, Verilog, SystemVerilog and SystemC users. In addition to the responsibility to manage design language dual-logo standards, WG 2 has maintenance responsibility for IBIS, the I/O Buffer Information Specification. IBIS 4.2 is on the work plan for standardization. The Japanese National Committee’s technical report from JEITA on their Bird’s eye View of Design Language (BVDL) was also submitted as an official submission.
The TC 93 addresses a broad spectrum of standards for the design automation of electronic devices ranging from printed circuit boards and systems to semiconductor devices and systems. From that broad swath of interests, two dual-logo candidates germane to language-based design flows were on the agenda for consideration by the IEC Standards Management Board (SMB).
Specifically, IEEE Std 1076-2008 and IEEE Std 1800-2009 were approved by the SMB at the start of the meeting series on 11 October 2010 as dual-logo standards. For those who purchase their standards from the IEC or their national standards bodies, the VHDL standard is known as IEC 61691-1-1 Ed. 2.0 (2010) and the SystemVerilog standard is known as IEC 62530 Ed. 2.0 (2010). The content between the IEEE and IEC are the same with the exception of the cover page of the standard, which will carry both the IEEE and IEC logo. Different countries have different rules and laws to recognize standards. The IEC plays a key role to bridge these differences to promote efficient and effective global use of VHDL, Verilog, SystemVerilog, SystemC and more.
Tags: 1076, 1364, 1666, 1800, dual-logo, iec, IEEE, Standards, systemc, SystemVerilog, TC93, verilog, vhdl, WG2
SystemC (IEEE Std. 1666™) Comes to YouTube
OSCI Expands Use of Social Media to Promote SystemC
It is a challenge for the global SystemC community to participate in conference update sessions and regional user group meetings in person to keep abreast of the SystemC developments. The OSCI website is full of information to help keep current on SystemC, but one often has to use a standard computer to access more advance audio and video content making it inconvenient. With the advent of net-ready devices that are YouTube capable (televisions, DVD/blue-ray players, Smartphones, etc.) or social media aggregation sites like MobileTribe, OSCI has created a YouTube channel you can subscribe to where you will find short clips posted to share informational and educational sessions from recent technical conferences and user group meetings
An example of a short discussion by John Anysley of Dolous on SystemC TLM 2.0 is offered here as a sample of what can be found on the SystemC YouTube channel.
While YouTube cannot substitute for the richer video synced with the actual slides presented that can be found at the OSCI website, like those for the 11th North American SystemC Users Group (NASCUG) meeting, it certainly offers a more convenient outlet to get information. I only wonder what a family response would be to the question “Do you mind if I change the station to the SystemC YouTube channel?” [Yes, I’ve watched me on full screen HD via YouTube, and it is convenient.]
If you would like to be alerted to new videos on SystemC as they are posted, you can subscribe to OSCI’s YouTube channel for notification. Web-based video sessions from DVCon and DAC are generally made available to YouTube six months after first publication at systemc.org.
The SystemC Promotions Group, which I chair, will meet shortly to review promotional activities in 2010 and I anticipate we will continue to expand the use of web-based offerings to help bring timely information to more people globally. Do you have a preferred way to learn about SystemC that we should know about? Let me know and I will share it with the OSCI promotions group.
As OSCI promotion group chair, I thank those companies that sponsor global SystemC promotion activities for adding video content from select technical conferences and user group meetings this past year and for their continued support in 2010.
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
Latest Posts
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- Even More UVM Debug in Questa 10.2
- IEEE Approves New Low Power Standard
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