Posts Tagged ‘1076’
The IEEE’s Most Popular EDA Standards
How do your favorites rank?
Have you ever wondered how popular the different IEEE standards for electronic design automation are? Have you ever wondered which ones show the least interest? When buying books online, popular book buying websites sites will rank customer purchases. Many newspapers manage lists that you can consult to determine what is the most popular; what has the highest demand. But if you have purchased any IEEE standards, you will know this information is not available from the IEEE Store or the IEEE XPlore platform.
On May 4th, the IEEE Standards Association announced its collaboration with Techstreet to create the New IEEE Standards Store. Until now, anyone who wanted to order a single standard had to use a more complex system that even made it hard to share a permanent link to one’s favorite standard with another. Just look at the Accellera homepage for an example of where to get the SystemVerilog (IEEE Std. 1800™) standard. At the writing of this blog, it simply points to www.ieee.org. [I will share the fact the IEEE’s new site now has fixed links that can now be used to help others find the most current SystemVerilog standard with the Accellera.]
But back to what is the most popular IEEE EDA standards… Any guesses?
Before I delve into those details, let me say the ranking is just by ordinal. The New IEEE Standards Store shares no information on the actual number of standards purchased. So the difference between #1 and #10 could be just 10 copies. It probably isn’t, but it could be. But talking about #10, why is it even on the list? The IP-XACT standard (IEEE Std. 1685™) is available for free under the IEEE Get Program. Under this program you can download a PDF of the IEEE standard for free. If you want a printed version, you can print your own copy from the free one you download. Back in December 2010, Accellera reported that since the IEEE started to offer IP-XACT for free, there had been 1200 downloads. It also looks like many people did not want the hassle to print and simply ordered the print version directly from the IEEE. The other IEEE EDA standard offered free is SystemC© And this is probably the reason it is in 32nd place. It is very popular in terms of the number of free downloads.
And yes, if you search for the those two standards on the New IEEE Standards Store, you will find you can order print copies there and if you read the small print below, you will see there is a link to take you to the free online versions.
Harry Foster has issued several research reports on the popularity of one language or format the past several months. In his last blog, he discussed which of the design and verification languages are ranked high and those, well, not so high. And I guess I feel best to share the correlation between his findings and these more “anecdotal” results from the New IEEE Standards Store. I have been party to many at the top standards (Verilog/SystemVerilog) and party to the “least highest” (yes, I can’t say the least liked) VITAL 2000. For vindication, I will note that VITAL-95 comes in at #18. In whole, it appears to me that the New IEEE Standards Store ordinal rankings of EDA standards matches the scientific data from the research Harry has reported.
Below is the full ranking of IEEE EDA standards. Where are your favorites?
| 1 | IEEE 1364-2001 | Verilog Hardware Description Language |
| 2 | IEEE 1800-2009 | SystemVerilog–Unified Hardware Design, Specification, and Verification Language |
| 3 | IEEE 1076-2002 | VHDL Language Reference Manual |
| 4 | IEEE 1076-1993 | VHDL Language Reference Manual |
| 5 | IEEE 1499-1998 | Interface for Hardware Description Models of Electronic Components |
| 6 | IEEE 1364-1995 | Hardware Description Language Based on the Verilog® Hardware Description Language |
| 7 | IEEE 1800-2005 | SystemVerilog: Unified Hardware Design, Specification and Verification Language |
| 8 | IEEE 1076.2-1996 | VHDL Mathematical Packages |
| 9 | IEEE 1076.1-1999 | VHDL Analog and Mixed-Signal Extensions |
| 10 | IEEE 1685-2009 | IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows |
| 11 | IEEE 1850-2005 | Property Specification Language (PSL) |
| 12 | IEEE 1076c-2007 | VHDL Language Reference Manual – Procedural Language Application Interface |
| 13 | IEEE 1164-1993 | Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164) |
| 14 | IEEE 1850-2010 | Property Specification Language (PSL) |
| 15 | IEEE 1076.6-2004 | VHDL Register Transfer Level (RTL) Synthesis |
| 16 | IEEE 1801-2009 | Design and Verification of Low Power Integrated Circuits |
| 17 | IEEE 1481-2009 | Integrated Circuit (IC) Open Library Architecture (OLA) |
| 18 | IEEE 1076.4-1995 | VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification |
| 19 | IEEE/IEC 61691-5-2004 | IEC 61691-5 Ed.1 (IEEE Std 1076.4(TM)-2000): Behavioural Languages – Part 5: Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification |
| 20 | IEEE 1647-2008 | Functional Verification Language e |
| 21 | IEEE 1076.1.1-2011 | VHDL Analog and Mixed-Signal Extensions — Packages for Multiple Energy Domain Support |
| 22 | IEEE/IEC 61691-7-2009 | Behavioural languages – Part 7: SystemC Language Reference Manual |
| 23 | IEEE 1076-1987 | VHDL Language Reference Manual |
| 24 | IEEE 1076.1.1-2004 | VHDL Analog and Mixed-Signal Extensions—Packages for Multiple Energy Domain Support |
| 25 | IEEE 1076.3-1997 | VHDL Synthesis Packages |
| 26 | IEEE/IEC 61523-3-2004 | IEC 61523-3 Ed.1 (IEEE Std 1497(TM)-2001): Delay and Power Calculation Standards – Part 3: Standard Delay Format (SDF) for the Electronic Design Process |
| 27 | IEEE 1076/INT-1991 | Interpretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual |
| 28 | IEEE/IEC 62531-2007 | IEC 62531 Ed. 1 (2007-11) (IEEE Std 1850-2005): Standard for Property Specification Language (PSL) |
| 29 | IEEE 1076.6-1999 | VHDL Register Transfer Level Synthesis |
| 30 | IEEE 1647-2006 | Functional Verification Language “e” |
| 31 | IEEE/IEC 61691-6-2009 | Behavioural languages – Part 6: VHDL Analog and Mixed-Signal Extensions |
| 32 | IEEE 1666-2005 | SystemC® Language Reference Manual |
| 33 | IEEE/IEC 61691-1-1-2004 | IEC 61691-1-1 Ed.1 (IEEE Std 1076(TM)-2002): Behavioural Languages – Part 1-1: VHDL Language Reference Manual |
| 34 | IEEE 1364-2005 | Verilog Hardware Description Language |
| 35 | IEEE/IEC 61691-4-2004 | IEC 61691-4 Ed.1 (IEEE Std 1364(TM)-2001): Behavioural Languages – Part 4: Verilog® Hardware Description Language |
| 36 | IEEE 1076.4-2000 | VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification |
Learn more about the New IEEE Standards Store
There is much more to the New IEEE Standards Store than just the rankings of the standards we use in electronic design automation. As I mentioned, it is easier to share fixed links to IEEE standards. And if you want to track IEEE standards development – and don’t want to have to register your email address with the actual committee developing it just to know when they are done and a standard is ready – you can register to be notified when a new standard is ready. The New IEEE Standards Store will notify you when a new one is ready.
Check out the short, one minute, video below to learn more about the New IEEE Standards Store.
Tags: 1076, 1076.4, 1364, 1800, IEEE, IP-XACT, Standards, systemc, SystemVerilog, verilog, vhdl, VITAL
Part 8: The 2010 Wilson Research Group Functional Verification Study
Language and Library Trends
This blog is a continuation of a series of blogs, which present the highlights from the 2010 Wilson Research Group Functional Verification Study (for a background on the study, click here).
In my previous blog (Part 7 click here), I focused on some of the 2010 Wilson Research Group findings related to testbench characteristics and simulation strategies. In this blog, I present design and verification language trends, as identified by the Wilson Research Group study.
You might note for some of the language and library data I present, the percentage sums to more than one hundred percent. The reason for this is that some perticipant’s projects use multiple languages and multiple methodologies.
Design Languages
Let’s begin by examining the languages used for design, as shown in Figure 1. Here, we compare the results for languages used to design FPGAs (in grey) with languages used to design non-FPGAs (in green).
Figure 1. Languages used for design
Not too surprising, we see that VHDL is the most popular language used for the design of FPGAs, while Verilog and SystemVerilog are the most popular languages used for the design of non-FPGAs.
Figure 2 shows the trends in terms of languages used for design, by comparing the 2007 Far West Research study (in blue) with the 2010 Wilson Research Group study (in green), as well as the projected design language adoption trends within the next twelve months (in purple). Note that the design language adoption is declining for most of the languages with the exception of SystemVerilog whose adoption is increasing.
Figure 2. Trends in languages used for design
Verification Languages
Next, let’s look at the languages used for verification (that is, languages used to create simulation testbenches). Figure 3 compares the results between FPGA designs (in grey) and non-FPGA designs (in green). 
Figure 3. Languages used in verification to create simulation testbenches
And again, it’s not too surprising to see that VHDL is the most popular language used to create verification testbenches for FPGAs, while SystemVerilog is the most popular language used to create testbenches for non-FPGAs.
Figure 4 shows the trends in terms of languages used to create simulation testbenches by comparing the 2007 Far West Research study (in blue) with the 2010 Wilson Research Group study (in green), as well as the projected language adoption trends within the next twelve months (in purple). Note that verification language adoption is declining for most of the languages with the exception of SystemVerilog whose adoption is increasing.
Figure 4. Trends in languages used in verification to create simulation testbenches
Now, let’s look at methodology and class library adoption. Figure 5 shows the future trends in terms of methodology and class library adoption by comparing the 2010 Wilson Research Group study (in green) with the projected adoption trends within the next twelve months (in purple). Previous studies did not include data on methodology and class library adoption, so we are unable to show previous trends.
Figure 5. Methodology and class library future trends
The study indicates that the only methodology adoption projected to grow in the next twelve months are OVM and UVM.
Assertion Languages and Libraries
Finally, let’s examine assertion language and library adoption, as shown in Figure 6. Here, we compare the results for FPGA designs (in grey) and non-FPGA designs (in green).
Figure 6. Assertion language and library adoption
SystemVerilog Assertions (SVA) is the most popular assertion language used for both FPGA and non-FPGA designs.
Figure 7 shows the trends in terms assertion language and library adoption by comparing the 2007 Far West Research study (in blue) with the 2010 Wilson Research Group study (in green), as well as the projected adoption trends within the next twelve months (in purple). Note that the adoption of most of the assertion languages is declining, with the exception of SVA whose adoption is increasing.
Figure 7. Trends in assertion language and library adoption
In my next blog (click here), I plan to focus on the adoption of various verification technologies and techniques used in the industry, as identified by the 2010 Wilson Research Group study.
Tags: 1076, 1364, 1666, 1800, accellera, Add new tag, Assertion-Based Verification, functional verification, IEEE 1800, OVM, Standards, SystemVerilog, UVM, Verification Methodology, verilog, vhdl, vmm
IEC’s 47th General Assembly Meeting Opens
United States Plays Host in Seattle, WA
The IEC’s 47th General Assembly meeting opened on October 11th in Seattle, WA USA. Plans had been put in place for about 2,500 delegates but that number was exceeded by nearly 25% with more than 3,100 people registered. Three days before the start of the meeting the Technical Committee 93, which addresses all the design automation standards held seven working group meetings from Friday-Sunday. On Monday the group reported out conclusions of all the committee’s working groups.
Working Group 2 manages the process to promote dual-logo standards development between the IEEE and IEC for design languages and may be of particular interest to VHDL, Verilog, SystemVerilog and SystemC users. In addition to the responsibility to manage design language dual-logo standards, WG 2 has maintenance responsibility for IBIS, the I/O Buffer Information Specification. IBIS 4.2 is on the work plan for standardization. The Japanese National Committee’s technical report from JEITA on their Bird’s eye View of Design Language (BVDL) was also submitted as an official submission.
The TC 93 addresses a broad spectrum of standards for the design automation of electronic devices ranging from printed circuit boards and systems to semiconductor devices and systems. From that broad swath of interests, two dual-logo candidates germane to language-based design flows were on the agenda for consideration by the IEC Standards Management Board (SMB).
Specifically, IEEE Std 1076-2008 and IEEE Std 1800-2009 were approved by the SMB at the start of the meeting series on 11 October 2010 as dual-logo standards. For those who purchase their standards from the IEC or their national standards bodies, the VHDL standard is known as IEC 61691-1-1 Ed. 2.0 (2010) and the SystemVerilog standard is known as IEC 62530 Ed. 2.0 (2010). The content between the IEEE and IEC are the same with the exception of the cover page of the standard, which will carry both the IEEE and IEC logo. Different countries have different rules and laws to recognize standards. The IEC plays a key role to bridge these differences to promote efficient and effective global use of VHDL, Verilog, SystemVerilog, SystemC and more.
Tags: 1076, 1364, 1666, 1800, dual-logo, iec, IEEE, Standards, systemc, SystemVerilog, TC93, verilog, vhdl, WG2
I Do It …
… To Advance Technology for Humanity
It is a humbling honor to have been elected chair of the IEEE Standards Association’s (SA) Corporate Advisory Group (CAG). While Corporate Membership in the IEEE SA has been an element of the organization from its inception, it has only been in recent years that it has started to bring the voice of global industry into the IEEE’s standards making process. As CAG chair I plan to work with fellow CAG members to continue to encourage industry to extend its role to guide the IEEE SA and deepen its impact to foster consensus standards that meet industry needs.
The EDA industry and users of EDA technology have played a big role to help the corporate program to take shape. Prior to any EDA standards adopting the IEEE corporate process, “consumer” members of the IEEE 1076 (VHDL) team offered specific feedback in a letter writing campaign to EDA company leadership. Consulted on this campaign prior to its start, I was given an opportunity to weight in, in case I was able to offer a solution to avoid the campaign.
While I agreed with the need for greater direct and clear industry involvement, a revenue tax was probably not the answer. I also indicated I was almost certain that such a request to the highest levels in Mentor Graphics would probably find its way right back to me. The letter to Wally, Mentor Graphics’ CEO, did just that. It found its way to me. And the response back promised to reflect on Mentor’s commitment and that of industry to standards.
The VHDL team planted a seed to consider the question of what industry can do to foster better standards development that binds technologist with industry that I took to heart. A good model was underway in Accellera where SystemVerilog was being crafted that had strong support from Mentor Graphics and Synopsys along with vocal planned user adoption by Intel when their representative spoke at an Accellera press conference on the need for the industry to adopt the language.
While the rest is history for Accellera (and SystemVerilog), it was just the beginning for the IEEE SA. In the year ahead, Gabe Moretti, a member of the IEEE SA New Standards Committee at the time, told me (chair of Accellera at the time) of a growing corporate program in the IEEE SA. The corporate process to make SystemVerilog the IEEE 1800 standard was adopted and used. I also encouraged the VHDL team to follow the same path. The VHDL team was even more inventive and did some of their prep work within Accellera. However, when it came time to return to the IEEE SA, they retained their historical way to complete their work in the IEEE.
My preference is to have active industry participation during standardization. I like to know up front what backing the standard has from industry. The faster we can get industry to back and adopt standards, the faster humanity can benefit from the application of standards.
It is the pace part of industry involvement that has me add something to the new IEEE tag-line: “I do it to advance technology for humanity, quickly.”
Tags: 1076, 1800, accellera, CAG, IEEE-SA, Standards, SystemVerilog, vhdl
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
Latest Posts
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- Even More UVM Debug in Questa 10.2
- IEEE Approves New Low Power Standard
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