Archive for Tom Fitzpatrick

12 August, 2014

As some of you may have seen, we release a great DAC edition of Verification Horizons back in June. Unfortunately, we were so focused on preparing for a great Verification Academy Booth at DACBoothPic
that I completely forgot to blog about the issue! Well, as the saying goes, “better late than never.”  In particular, I’d like to call your attention to two articles.

The first is “Best Practices for FPGA and ASIC Development” by my Mentor colleagues Josh Rensch and John Boone, in which they take you through the four development phases of an FPGA project. By separating the process into distinct PLAN, EXECUTE, VERIFY and SUPPORT phases, Josh and John help you establish a manageable process that you can apply to your next project. The key is to identify the techniques, or specific activities, that will be used at each phase, and establish a rigorous set of deliverables for each phase. Just like clear interface specs are necessary for two design blocks to be able to talk to each other, clear deliverables at each phase of the process let different groups work together efficiently to create a robust and well-verified design.

The other article I wanted to point out to you is “Merging SystemVerilog Covergroups by Example” by our friend Eldon Nelson, a verification engineer at Micron Technology. This article explores the options available when defining and using covergroups, establishing some important guidelines that will help you get the most useful information when multiple instances of covergroups are merged together. Be sure to check it out.

The other articles in the issue are:

3 March, 2014

DVCon is always one of my favorite events in our industry, and I am proud to let you know that the latest issue of Verification Horizons is available “hot off the presses” at the Verification Academy to mark the occasion. For those of you attending the conference, please consider this issue as an addendum to the great technical program being offered (especially paper 8.1, “Of Camels and Committees: Standards Should Enable Innovation, Not Strangle It” by Dave Rich and yours truly). For those of you not able to join us at DVCon this year, consider this your consolation prize.

Although fewer in number, I’m sure you’ll find the articles in Verification Horizons as informational and useful as any you’ll see at DVCon. In particular, I’d like to make sure you check out these articles by our partners:

  • “Don’t Forget the Little Things That Can Make Verification Easier” by our friend Stu Sutherland of Sutherland HDL
  • “Taming Power-Aware Bugs with Questa Ultra” by SmartPlay Technologies
  • “Using Mentor Questa for pre-silicon validation of IEEE 1149.1-2013 based Silicon Instruments” by Intellitech
  • “Dealing With UVM and OVM Sequences” by eInfochips

If you’re at DVCon, please make sure to stop by the Mentor Graphics booth (#501) to say hi. Please join us on Wednesday for our luncheon presentation at noon, right after Session 8, in which I’ll present my paper mentioned above (that’s right. I’m not above shameless self-promotion). And we’ll wrap up the week with two Mentor-sponsored tutorials on Thursday:

Both of these tutorials feature a mix of Mentor presenters and customers to offer some practical examples that will give you some new ideas for improving your verification process. I hope to see you at DVCon.

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15 November, 2013

Wanted to let you all know that the October, 2013 issue of Verification Horizons is available online. You can view the articles or download the issue here. In addition to a little paternal bragging in the Introduction, I wanted to call your attention in particular to a few of the articles written by some Mentor colleagues:

  • Software-Driven Testing of AXI Bus in a Dual Core ARM System by Mark Olen, Mentor Graphics
    In this article, Mark presents an architecture for verifying the functionality and performance of a complex AXI bus fabric using a combination of SystemVerilog and C software-driven test techniques, where the operation of the C code is automatically coordinated with additional UVM stimulus to ensure that you’re hitting corner cases of your software as well as your hardware.
  • Caching in on Analysis by Mark Peryer, Mentor Graphics
    Our “other Mark” explains how to verify complex interconnect subsystems in Questa through testbench and instrumentation generation, as well as automated stimulus to target interconnect functionality and cache coherency.
  • DDR SDRAM Bus Monitoring using Mentor Verification IP by Nikhil Jain, Mentor Graphics
    Here, Nikhil explains how Mentor’s DDR VIP can be used as a bus monitor, taking advantage of builtin coverage and assertions, to ensure proper protocol behavior.
  • Life Isn’t Fair, So Use Formal by Roger Sabbagh, Mentor Graphics
    Roger will show you how to use Questa CoverCheck to help you reach (or usually eliminate) that last 10% of code coverage that always seems to take so long.

I had to write my introduction before the Red Sox actually made it to the World Series, but I just have to say that

  1. I picked the Sox to beat the Tigers in 6 games in the ALCS (including calling Big Papi’s grand slam in game two – ask my son), and
  2. I picked the Sox to beat the Cardinals in 6 games to win the World Series.

Just wanted you all to know that.

-Tom

31 May, 2013

Hi Everyone,

Just wanted to let you know that we just posted the PDF of the latest, Texas-Sized, DAC edition of Verification Horizons on the Verification Academy. In addition to my Editor’s Note, in which I liken what we do as verification engineers to my set-building experiences in local theatre groups, and brag about my daughter, you’ll find these fine articles:

We’ll have plenty of copies available at DAC. Be sure to stop by the Mentor booth (2046) or the Verification Academy booth (1215) to pick one up, or just to say “Howdy.”

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19 March, 2013

We’re really excited about the recent Questa 10.2 release, and I’m sure you’ll be just as excited when you check it out. For you UVM-philes out there, we’ve extended our industry-leading UVM Debug features to make your life even easier. I’ll present a quick overview of the new features here, but you’ll really want to get your hands on 10.2 and take a more in-depth look for yourself.

The first thing you’ll notice is that we’ve enhanced to Structure Window (usually located in the upper left of the debugger) to show the class type of each UVM component in your testbench. This will make it easier to know exactly what your factory settings and other configuration settings have yielded as you built your testbench.

One of the most common requests we’ve gotten is to provide a way to see what exactly is happening with the configuration database (uvm_config_db). In the UVM Details window, you can now see the values that are available to the selected component, and by right-clicking you can see who wrote the value and where the write occurred.

In the Stream view of the Details window, you can see all of the transaction streams being recorded by the selected component.

Also, when debugging UVM processes, the Processes Window now includes the hierarchical path to the component that initiated the process.

Lastly, for those of you who may not be GUI-centric, we’ve added a new “uvm” command to the command-line interface in the transcript window (or via “.do” files):

uvm subcommand [args...] 
 

where the “subcommand” lets you choose from a number of options. The default subcommand (and in my opinion, the coolest) is the “call” command, which allows you to call UVM functions directly from the command line. You can even call functions in UVM components by referring to the components via their hierarchical name

uvm call test_top.env1.fab.get_full_name
 

or via a handle provided by Questa (as seen in the Class Instances window).

call @myClassType@223.get_full_name 
 

There are other useful UVM commands that I won’t go into here, but you should definitely check them out. So, what are you waiting for? To find out more information about Questa with this link: http://www.mentor.com/products/fv/questa/

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27 February, 2013

Hi Everyone,
Just wanted to let you all know that the new issue of Verification Horizons is now available. You can get the full edition online at the Verification Academy. Please be sure to check it out. There are a few articles in particular that I’d like to call your attention to.

Using Formal Analysis to “Block and Tackle” by Paul B. Egan of Rockwell Automation is a great case study in how apply formal to reduce verification time at both the block and chip level by plugging coverage holes missed by simulation. In the article, Paul describes a straightforward three-step process to add formal analysis to your verification flow.

In Bringing Verification and Validation under One Umbrella my colleagues Hemant Sharma and Hans van der Schoot present a unified flow for RTL verification and pre-silicon validation of hardware/software integration by reusing your transaction-level testbench from simulation to emulation.

Be sure the check out The Evolution of UPF: What’s Next? by Erich Marschner. Erich is the chair of the IEEE 1801 committee, which just released UPF 2.1, so there is no one better to explain the new features in this latest release. You can also read about the evolution of features in UPF from 1.0 to 2.1 in a previous issue of Horizons here.

Our friends at CVC list the Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features, and Mark Litterick of Verilab (and recent Best Paper winner at DVCon 2013 – congratulations!) shares his experiences of OVM-to-UVM migration in OVM to UVM Migration, or “There and Back Again: A Consultant’s Tale.”

We’re already working on our DAC edition of Verification Horizons, so if you’d like to submit an article, we’d love to have you.

-Tom

24 October, 2012

Hi Everyone,

Just wanted to let you know that the latest and greatest edition of Verification Horizons is now available. The articles in this issue all discuss how you can apply new techniques and technology to achieve greater verification productivity. And for you football (I mean “American football” as opposed to “soccer”) fans out there, be sure and check out the Editor’s Note.

If you’re not already receiving Verification Horizons, you can sign up here.

9 July, 2012

Hi Everyone,

Just wanted to make sure you’re aware of our next Recipe of the Month online Web Seminar: Scoreboards and Results Predictors in UVM on Thursday, July 12 at 9am PDT. You can register for the seminar here. This will be the ninth seminar in our ongoing Recipe of the Month seminar (see the full list here) and the reviews have been universally positive.

This particular seminar will outline the proper architecture of scoreboards and predictors in UVM and how they relate to coverage.

Overview: If verification is the art of determining that your design works correctly under all specified conditions, then it is imperative that we are able to create an environment that can tell you if this is truly the case. Scoreboards are verification components that determine that the DUT is working correctly, including ensuring that the DUT properly handles all stimuli it receives. Predictors are components that represent a “golden” model of all or part of the DUT that generate an expected response against which the scoreboard can compare the actual response of the DUT.

Hope to “see” you on Thursday.

-Tom

31 May, 2012

As Editor of Verification Horizons, I’d like to point out a couple of articles that you really need to check out, if you haven’t already. If you want to take a look at full issues of Horizons, you can find them here.

I’m sure many of you have found yourselves in the painful situation of trying to track down a hard-to-reach coverage hole only to find out, after way too much time, that the coverage item is actually unreachable. If you have, then you need to read “Using Formal Technology To Improve Coverage Results,” which will explain the unique ability of formal technology in Questa to improve coverage results while reducing the amount of time wasted trying to hit unreachable states.

The other article I want you to be sure and check out is ” Automation Management: Are You Living a Scripted Life?” In it, you’ll learn how Questa’s Verification Run Manager will help you automate your verification process so you can focus on verifying your designs and not on debugging your environment infrastructure. As you’ll see, the proper application of automation lets you boost the productivity of your verification engineers while reducing the maintenance burden on your CAD teams. This article is actually the third in a series on Verification Management, and you can check out the first two articles here and here.

The DAC issue of Verification Horizons is coming soon, so be sure to take a look.

-Tom

12 May, 2012

I’m sure many of you know my colleague, Dave Rich. I’ve known Dave since our days at Co-Design Automation when we worked together defining the Superlog language, which eventually became SystemVerilog after being donated to Accellera. Hard to believe that was 11 years ago. Having gotten to know Dave as a friend as well as a colleague over that time, I really enjoyed learning even more about him in his recent interview as the Featured Engineer on EEWeb.

It’s been a great source of pride, both personal and professional, to be able to say that I’ve worked for over 10 years with the person who probably knows more about SystemVerilog than anyone else on the planet. Back when I was working on the IEEE 1364 Verilog standard, whenever there was confusion about spec, we always used to say “what does Verilog-XL do?” With SystemVerilog, whenever there’s a question about the spec, I just ask Dave (and you should too).

Congratulations, Dave!

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