Archive for Tom Fitzpatrick
Verification Horizons BLOG
Texas-Sized DAC Edition of Verification Horizons Now Up on Verification Academy
Hi Everyone,
Just wanted to let you know that we just posted the PDF of the latest, Texas-Sized, DAC edition of Verification Horizons on the Verification Academy. In addition to my Editor’s Note, in which I liken what we do as verification engineers to my set-building experiences in local theatre groups, and brag about my daughter, you’ll find these fine articles:
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Interviewing a Verification Engineer by Akiva Michelson, Ace Verification
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Maximum Productivity with Verification IP by Joe Rodriguez, Raghu Ardeishar, and Rich Edelman, Mentor Graphics
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Power Up Hardware/Software Verification Productivity by Matthew Ballance, Mentor Graphics
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Non-invasive Software Verification using Vista Virtual Platforms by Alex Rozenman, Vladimir Pilko, and Nilay Mitash, Mentor Graphics
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QVM: Enabling Organized, Predictable, and Faster Verification Closure by Gaurav Jalan, SmartPlay Technologies, and Pradeep Salla, Mentor Graphics
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Verifying High Speed Peripheral IPs by Sreekanth Ravindran and Chakravarthi M.G., Mobiveil
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Confidence in the Face of the Unknown: X-state Verification by Kaowen Liu, MediaTek Inc., and Roger Sabbagh, Mentor Graphics
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Making it Easy to Deploy the UVM by Dr. Christoph Sühnel, frobas GmbH
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NoC Generic Scoreboard VIP by François Cerisier and Mathieu Maisonneuve, Test and Verification Solutions
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Flexible UVM Components: Configuring Bus Functional Models by Gunther Clasen, Ensilica
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Monitors, Monitors Everywhere – Who Is Monitoring the Monitors? by Rich Edelman and Raghu Ardeishar, Mentor Graphics
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The Need for Speed: Understanding Design Factors that Make Multi-core Parallel Simulations Efficient by Shobana Sudhakar & Rohit Jain, Mentor Graphics
We’ll have plenty of copies available at DAC. Be sure to stop by the Mentor booth (2046) or the Verification Academy booth (1215) to pick one up, or just to say “Howdy.”
Tags: dac, Verification Academy
Even More UVM Debug in Questa 10.2
We’re really excited about the recent Questa 10.2 release, and I’m sure you’ll be just as excited when you check it out. For you UVM-philes out there, we’ve extended our industry-leading UVM Debug features to make your life even easier. I’ll present a quick overview of the new features here, but you’ll really want to get your hands on 10.2 and take a more in-depth look for yourself.
The first thing you’ll notice is that we’ve enhanced to Structure Window (usually located in the upper left of the debugger) to show the class type of each UVM component in your testbench. This will make it easier to know exactly what your factory settings and other configuration settings have yielded as you built your testbench.
One of the most common requests we’ve gotten is to provide a way to see what exactly is happening with the configuration database (uvm_config_db). In the UVM Details window, you can now see the values that are available to the selected component, and by right-clicking you can see who wrote the value and where the write occurred.
In the Stream view of the Details window, you can see all of the transaction streams being recorded by the selected component.
Also, when debugging UVM processes, the Processes Window now includes the hierarchical path to the component that initiated the process.
Lastly, for those of you who may not be GUI-centric, we’ve added a new “uvm” command to the command-line interface in the transcript window (or via “.do” files):
uvm subcommand [args...]
where the “subcommand” lets you choose from a number of options. The default subcommand (and in my opinion, the coolest) is the “call” command, which allows you to call UVM functions directly from the command line. You can even call functions in UVM components by referring to the components via their hierarchical name
uvm call test_top.env1.fab.get_full_name
or via a handle provided by Questa (as seen in the Class Instances window).
call @myClassType@223.get_full_name
There are other useful UVM commands that I won’t go into here, but you should definitely check them out. So, what are you waiting for? To find out more information about Questa with this link: http://www.mentor.com/products/fv/questa/
Verification Horizons DVCon Issue Now Available
Hi Everyone,
Just wanted to let you all know that the new issue of Verification Horizons is now available. You can get the full edition online at the Verification Academy. Please be sure to check it out. There are a few articles in particular that I’d like to call your attention to.
Using Formal Analysis to “Block and Tackle” by Paul B. Egan of Rockwell Automation is a great case study in how apply formal to reduce verification time at both the block and chip level by plugging coverage holes missed by simulation. In the article, Paul describes a straightforward three-step process to add formal analysis to your verification flow.
In Bringing Verification and Validation under One Umbrella my colleagues Hemant Sharma and Hans van der Schoot present a unified flow for RTL verification and pre-silicon validation of hardware/software integration by reusing your transaction-level testbench from simulation to emulation.
Be sure the check out The Evolution of UPF: What’s Next? by Erich Marschner. Erich is the chair of the IEEE 1801 committee, which just released UPF 2.1, so there is no one better to explain the new features in this latest release. You can also read about the evolution of features in UPF from 1.0 to 2.1 in a previous issue of Horizons here.
Our friends at CVC list the Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features, and Mark Litterick of Verilab (and recent Best Paper winner at DVCon 2013 – congratulations!) shares his experiences of OVM-to-UVM migration in OVM to UVM Migration, or “There and Back Again: A Consultant’s Tale.”
We’re already working on our DAC edition of Verification Horizons, so if you’d like to submit an article, we’d love to have you.
-Tom
Check out the October, 2012 Verification Horizons
Hi Everyone,
Just wanted to let you know that the latest and greatest edition of Verification Horizons is now available. The articles in this issue all discuss how you can apply new techniques and technology to achieve greater verification productivity. And for you football (I mean “American football” as opposed to “soccer”) fans out there, be sure and check out the Editor’s Note.
If you’re not already receiving Verification Horizons, you can sign up here.
New UVM Recipe of the Month: Scoreboarding in UVM
Hi Everyone,
Just wanted to make sure you’re aware of our next Recipe of the Month online Web Seminar: Scoreboards and Results Predictors in UVM on Thursday, July 12 at 9am PDT. You can register for the seminar here. This will be the ninth seminar in our ongoing Recipe of the Month seminar (see the full list here) and the reviews have been universally positive.
This particular seminar will outline the proper architecture of scoreboards and predictors in UVM and how they relate to coverage.
Overview: If verification is the art of determining that your design works correctly under all specified conditions, then it is imperative that we are able to create an environment that can tell you if this is truly the case. Scoreboards are verification components that determine that the DUT is working correctly, including ensuring that the DUT properly handles all stimuli it receives. Predictors are components that represent a “golden” model of all or part of the DUT that generate an expected response against which the scoreboard can compare the actual response of the DUT.
Hope to “see” you on Thursday.
-Tom
Two Articles You Need to Check Out
As Editor of Verification Horizons, I’d like to point out a couple of articles that you really need to check out, if you haven’t already. If you want to take a look at full issues of Horizons, you can find them here.
I’m sure many of you have found yourselves in the painful situation of trying to track down a hard-to-reach coverage hole only to find out, after way too much time, that the coverage item is actually unreachable. If you have, then you need to read “Using Formal Technology To Improve Coverage Results,” which will explain the unique ability of formal technology in Questa to improve coverage results while reducing the amount of time wasted trying to hit unreachable states.
The other article I want you to be sure and check out is ” Automation Management: Are You Living a Scripted Life?” In it, you’ll learn how Questa’s Verification Run Manager will help you automate your verification process so you can focus on verifying your designs and not on debugging your environment infrastructure. As you’ll see, the proper application of automation lets you boost the productivity of your verification engineers while reducing the maintenance burden on your CAD teams. This article is actually the third in a series on Verification Management, and you can check out the first two articles here and here.
The DAC issue of Verification Horizons is coming soon, so be sure to take a look.
-Tom
Dave Rich Featured on EEWeb
I’m sure many of you know my colleague, Dave Rich. I’ve known Dave since our days at Co-Design Automation when we worked together defining the Superlog language, which eventually became SystemVerilog after being donated to Accellera. Hard to believe that was 11 years ago. Having gotten to know Dave as a friend as well as a colleague over that time, I really enjoyed learning even more about him in his recent interview as the Featured Engineer on EEWeb.
It’s been a great source of pride, both personal and professional, to be able to say that I’ve worked for over 10 years with the person who probably knows more about SystemVerilog than anyone else on the planet. Back when I was working on the IEEE 1364 Verilog standard, whenever there was confusion about spec, we always used to say “what does Verilog-XL do?” With SystemVerilog, whenever there’s a question about the spec, I just ask Dave (and you should too).
Congratulations, Dave!
Introducing UVM Connect
In his recent post on UVM: Some Thoughts Before DVCon, Dennis outlined some great ideas about what we think should happen next for UVM. His 3rd point, “UVM needs to bridge the system domain,” is particularly relevant given the newly-formed Accellera Systems Initiative. This is actually an area we’ve been contemplating for a while here at Mentor, and as Dennis indicated, we shared our thoughts on this topic at our last face-to-face with the VIP-TSC. With demand coming from our users, and some positive feedback on our proposal, we have just released UVM Connect, an open-source library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog models and components, as well as a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++).
You can find much more information on the UVM Connect page of Verification Academy.
Mentor has always believed that SystemVerilog and SystemC each have their own strengths and that the most productive way to combine them in a system-level environment is to preserve the strengths of each while allowing the free exchange of data between them. Instead of trying to re-implement UVM in SystemC, or to extend SystemC to try and recreate SystemVerilog functional coverage or constrained-random stimulus, UVM Connect provides the framework needed to interoperate between languages. This lets you:
- Reuse your SystemC architectural models as reference models in UVM verification
- Reuse your stimulus generation agents in SystemVerilog to verify models in SystemC
- Have access to a wider array of VIP since you are no longer confined to a single language
- Utilize and interact with the UVM infrastructure from SystemC, including wait for and control UVM phase transitions, set and get configuration, issue UVM-style reports, set factory type and instance overrides, and more
UVM Connect provides object-based data transfer across the language boundary via TLM1 and TLM2 interfaces, which are natively supported in both languages. It works out-of-the-box with UVM 1.1a and later and lets you use your existing TLM models, regardless of language, in a mixed-language context without modification. In a nutshell, UVM Connect fulfills the principles and purpose of the TLM interface standard, letting you design independent models that communicate without directly referring to each other. The models thus work equally well in both native and mixed-language environments.I encourage you to download the kit and give it a try. In the spirit of “co-op-etition” I also encourage our competitors to qualify the library on their simulators.
In addition to the great material in the UVM/OVM Online Methodology Cookbook on Verification Academy, the kit also includes an HTML User’s Guide, based on extensive, well-documented examples, that includes detailed information on all aspects of the API. Please make sure to stop by the Mentor booth at DVCon and let us know what you think.
Tags: dvcon, functional verification, systemc, SystemVerilog, UVM, UVM Connect, UVM-1.1, Verification Academy, Verification Methodology
New UVM Recipe-of-the-Month: Sequence Layering
I’m excited to announce that our second UVM Recipe-of-the-Month Webinar, “Sequence Layering,” will be presented on Thursday, September 15, at 1pm EDT(/10am PDT). To join over 240 of your colleagues and/or competitors in viewing this webinar, please see here. The webinar should take about an hour. If you can’t make it for the live viewing, the webinar will be archived for later viewing. Of course, if you attend the live session, you’ll be able to ask questions directly.
Last month’s inaugural Recipe-of-the-Month webinar, “OVM to UVM Migration” was a huge success and is now available online. If you have any questions about it, feel free to post them in the Forum.
Hope to “see” you on Thursday!
Tom
Verification Evangelist
Editor, Verification Horizons
Mentor Graphics
Verification Academy Now Includes OVMWorld Content
I am pleased to announce that Mentor Graphics has recently expanded Verification Academy to provide a “one-stop shop” for all your UVM/OVM and general verification information needs. As you may have noticed, the OVMWorld.org website has now been redirected to the Verification Academy and all of the content has been preserved, albeit reorganized a bit.
Of particular importance, the OVMWorld Forum discussion group has been preserved, in its entirety, on the new Verification Academy Forum, which also includes threads for UVM as well as OVM discussions, as well as general SystemVerilog discussions and discussions about other Academy content. All users of the OVMWorld forum will be able to access the Academy forum using their OVMWorld login information. Of course, current Academy users may also access the forum with their current Academy login.
By combining the expanded discussion forum with the UVM/OVM Online Methodology Cookbook and on-line video tutorials, the Verification Academy is now the premier resource for verification engineers wishing to get the most out of UVM and OVM. The Cookbook will continue to provide the latest methodology and how-to information, let you comment and make suggestions, and also let you generate PDF books directly from the website. You can print out one of our predefined books or customize to make one of your own. Of course, you can also download code examples to go along with the articles.
All OVM and UVM download kits, including UVM1.1, OVM2.1.2 and the new standalone UVM Register kit for use with OVM, are available on the Academy with no login required. In addition, unregistered users may also preview the Cookbook and read the discussion threads in the forum. To participate in the forum, you’ll need to register (forum users are allowed to use free email addresses), and to access the premium content, you’ll need to use your “work” email address to register.
So, go take a look at the new Verification Academy. I think you’ll like what you see.
-Tom
About Tom Fitzpatrick
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Latest Posts
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