Archive for Tom Fitzpatrick

3 June, 2015

I am please to announce that, beginning today, the Accellera Portable Stimulus Working Group (PSWG) is accepting technology contributions to assist in the creation of a Portable Test and Stimulus standard. More details can be found at http://www.accellera.org/.

This milestone marks a critical point in our efforts to bring a Portable Stimulus standard to the industry. Beginning in May of 2014, several companies came together to form the first Proposed Working Group in Accellera to evaluate the feasibility and need for such a standard. After six months of diligent work, the PWG created a set of 120 requirements as part of a proposal to the Accellera Board of Directors that a Working Group be formed. The PSWG began at DVCon this year and for the past several months has been working to define a set of goals, milestones and design objectives to guide the standardization effort. Now it’s your turn to get in on the act.

Contributions will be accepted until August 5th, after which the WG will be evaulating the contributions and deciding which one(s) to use as the basis for the standard.

If you’re at DAC this week, stop by the Verification Academy booth (#2408) and see a full slate of technical presentations including one where I’ll be sharing some of our thoughts on what the standard should look like. To register for any/all of these sessions, please go here. See you at DAC!


17 March, 2015

StPatricksDay

With a name like “Fitzpatrick,” you knew I’d be celebrating today, right?

Well, there’s no better way to celebrate this fine day than to announce that our latest edition of Verification Horizons is available online! Now that Spring is almost here, there’s a bit less snow on the ground than there was when I wrote my introduction, but everything is still covered. I’m considering spray-painting it all green in honor of the occasion, so at least it looks like I have a lawn again.

In this issue of Verification Horizons, I’d particularly like to draw your attention to “Successive Refinement: A Methodology for Incremental Specification of Power Intent,” by my friend and colleague Erich Marschner and several of our friends at ARM® Ltd. In this article, you’ll find out how the Unified Power Format (UPF) specification can be used to specify and verify your power architecture abstractly, and then add implementation information later in the process. This methodology is still relatively new in the industry, so if you’re thinking about making your next design PowerAware, you’ll want to read this article to be up on the very latest approach.

In addition to that, we’ve also got Harry Foster discussing some of the results from his latest industry study in “Does Design Size Influence First Silicon Success?” Harry is also blogging about his survey results on Verification Horizons here and here (with more to come).

Our friends at L&T Technology Services Ltd. share some of their experience in doing PowerAware design in “PowerAware RTL Verification of USB 3.0 IPs,” in which you’ll see how UPF can let you explore two different power management architectures for the same RTL.

Next, History class is in session, with Dr. Lauro Rizzatti, long-time EDA guru, giving us part 1 of a 3-part lesson in “Hardware Emulation: Three Decades of Evolution.”

Our friends at Oracle® are up next with “Evolving the Use of Formal Model Checking in SoC Design Verification,” in which they share a case study of their use of formal methods as the central piece in verifying an SoC design they recently completed with first-pass silicon success. By the way, I’d also like to take this opportunity to congratulate the author of this article, Ram Narayan, for his Best Paper award at DVCon(US) 2015. Well done, Ram!

We round out the issue with our famous “Partners’ Corner” section, which includes two articles. In “Small, Maintainable Tests,” our friends at Sondrel IC Design Services show you a few tricks on how to make use of UVM virtual sequences to raise the level of abstraction of your tests. In “Functional Coverage Development Tips: Do’s and Don’ts,” our friends at eInfochips give you a great overview of functional coverage, especially the covergroup and related features in SystemVerilog.

I’d also like to take a moment to thank all of you who came by our Verification Academy booth at DVCon to say hi. I found it incredibly humbling and gratifying to hear from so many of you who have learned new verification skills from the Verification Academy. That’s a big part of why we do what we do, and I appreciate you letting us know about it.

Now, it’s time to celebrate St. Patrick’s Day for real!

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12 December, 2014

Just in time for Christmas and other year-end holidays, I am pleased to announce that the latest issue of Verification Horizons is now available on-line. As usual, we have a great lineup of articles that I’m sure you’ll find informative:

By the way, if you’d like to subscribe to our quarterly Verification Horizons newsletter, you may do so here.

Whichever holiday(s) you celebrate at this special time of year, I hope you experience the peace, joy and hope that my family and I will share this Christmas.

5 November, 2014

When I was at DAC this year, I had a few folks come up to me at our Verification Academy booth and suggest that I do a “Recipe of the Month” webinar on UVM sequences. They’d seen plenty of information on sequence mechanics and generating stimulus with sequences, but these users were particularly interested in Slave sequences, which aren’t necessarily very intuitive. Of course, we have several articles dealing with all types of sequences in the UVM Cookbook on Verification Academy, but sometimes it’s a little easier to have someone walk through an example in a webinar. To that end, we created an on-demand webinar to explain “UVM Sequences in Depth” which is available for you to review at your leisure.

In the webinar, we explain how a Slave Sequence can be used to implement “responder” functionality in your testbench and how this use model makes it easier to modify the slave functionality as necessary rather than to swap in a new component. We also show how to use virtual sequences to coordinate the stimulus and slave sequences, and then we wrap up with an example of how to handle interrupt sequences.

This particular webinar is, to date, the most popular of our regular webinar series, with over 300 attendees. I was happy to be able to reach so many of you with this information and hope you found it valuable. Feel free to suggest topics for future webinars in the comments section.

Respectfully,
Tom Fitzpatrick

12 August, 2014

As some of you may have seen, we release a great DAC edition of Verification Horizons back in June. Unfortunately, we were so focused on preparing for a great Verification Academy Booth at DACBoothPic
that I completely forgot to blog about the issue! Well, as the saying goes, “better late than never.”  In particular, I’d like to call your attention to two articles.

The first is “Best Practices for FPGA and ASIC Development” by my Mentor colleagues Josh Rensch and John Boone, in which they take you through the four development phases of an FPGA project. By separating the process into distinct PLAN, EXECUTE, VERIFY and SUPPORT phases, Josh and John help you establish a manageable process that you can apply to your next project. The key is to identify the techniques, or specific activities, that will be used at each phase, and establish a rigorous set of deliverables for each phase. Just like clear interface specs are necessary for two design blocks to be able to talk to each other, clear deliverables at each phase of the process let different groups work together efficiently to create a robust and well-verified design.

The other article I wanted to point out to you is “Merging SystemVerilog Covergroups by Example” by our friend Eldon Nelson, a verification engineer at Micron Technology. This article explores the options available when defining and using covergroups, establishing some important guidelines that will help you get the most useful information when multiple instances of covergroups are merged together. Be sure to check it out.

The other articles in the issue are:

3 March, 2014

DVCon is always one of my favorite events in our industry, and I am proud to let you know that the latest issue of Verification Horizons is available “hot off the presses” at the Verification Academy to mark the occasion. For those of you attending the conference, please consider this issue as an addendum to the great technical program being offered (especially paper 8.1, “Of Camels and Committees: Standards Should Enable Innovation, Not Strangle It” by Dave Rich and yours truly). For those of you not able to join us at DVCon this year, consider this your consolation prize.

Although fewer in number, I’m sure you’ll find the articles in Verification Horizons as informational and useful as any you’ll see at DVCon. In particular, I’d like to make sure you check out these articles by our partners:

  • “Don’t Forget the Little Things That Can Make Verification Easier” by our friend Stu Sutherland of Sutherland HDL
  • “Taming Power-Aware Bugs with Questa Ultra” by SmartPlay Technologies
  • “Using Mentor Questa for pre-silicon validation of IEEE 1149.1-2013 based Silicon Instruments” by Intellitech
  • “Dealing With UVM and OVM Sequences” by eInfochips

If you’re at DVCon, please make sure to stop by the Mentor Graphics booth (#501) to say hi. Please join us on Wednesday for our luncheon presentation at noon, right after Session 8, in which I’ll present my paper mentioned above (that’s right. I’m not above shameless self-promotion). And we’ll wrap up the week with two Mentor-sponsored tutorials on Thursday:

Both of these tutorials feature a mix of Mentor presenters and customers to offer some practical examples that will give you some new ideas for improving your verification process. I hope to see you at DVCon.

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15 November, 2013

Wanted to let you all know that the October, 2013 issue of Verification Horizons is available online. You can view the articles or download the issue here. In addition to a little paternal bragging in the Introduction, I wanted to call your attention in particular to a few of the articles written by some Mentor colleagues:

  • Software-Driven Testing of AXI Bus in a Dual Core ARM System by Mark Olen, Mentor Graphics
    In this article, Mark presents an architecture for verifying the functionality and performance of a complex AXI bus fabric using a combination of SystemVerilog and C software-driven test techniques, where the operation of the C code is automatically coordinated with additional UVM stimulus to ensure that you’re hitting corner cases of your software as well as your hardware.
  • Caching in on Analysis by Mark Peryer, Mentor Graphics
    Our “other Mark” explains how to verify complex interconnect subsystems in Questa through testbench and instrumentation generation, as well as automated stimulus to target interconnect functionality and cache coherency.
  • DDR SDRAM Bus Monitoring using Mentor Verification IP by Nikhil Jain, Mentor Graphics
    Here, Nikhil explains how Mentor’s DDR VIP can be used as a bus monitor, taking advantage of builtin coverage and assertions, to ensure proper protocol behavior.
  • Life Isn’t Fair, So Use Formal by Roger Sabbagh, Mentor Graphics
    Roger will show you how to use Questa CoverCheck to help you reach (or usually eliminate) that last 10% of code coverage that always seems to take so long.

I had to write my introduction before the Red Sox actually made it to the World Series, but I just have to say that

  1. I picked the Sox to beat the Tigers in 6 games in the ALCS (including calling Big Papi’s grand slam in game two – ask my son), and
  2. I picked the Sox to beat the Cardinals in 6 games to win the World Series.

Just wanted you all to know that.

-Tom

31 May, 2013

Hi Everyone,

Just wanted to let you know that we just posted the PDF of the latest, Texas-Sized, DAC edition of Verification Horizons on the Verification Academy. In addition to my Editor’s Note, in which I liken what we do as verification engineers to my set-building experiences in local theatre groups, and brag about my daughter, you’ll find these fine articles:

We’ll have plenty of copies available at DAC. Be sure to stop by the Mentor booth (2046) or the Verification Academy booth (1215) to pick one up, or just to say “Howdy.”

,

19 March, 2013

We’re really excited about the recent Questa 10.2 release, and I’m sure you’ll be just as excited when you check it out. For you UVM-philes out there, we’ve extended our industry-leading UVM Debug features to make your life even easier. I’ll present a quick overview of the new features here, but you’ll really want to get your hands on 10.2 and take a more in-depth look for yourself.

The first thing you’ll notice is that we’ve enhanced to Structure Window (usually located in the upper left of the debugger) to show the class type of each UVM component in your testbench. This will make it easier to know exactly what your factory settings and other configuration settings have yielded as you built your testbench.

One of the most common requests we’ve gotten is to provide a way to see what exactly is happening with the configuration database (uvm_config_db). In the UVM Details window, you can now see the values that are available to the selected component, and by right-clicking you can see who wrote the value and where the write occurred.

In the Stream view of the Details window, you can see all of the transaction streams being recorded by the selected component.

Also, when debugging UVM processes, the Processes Window now includes the hierarchical path to the component that initiated the process.

Lastly, for those of you who may not be GUI-centric, we’ve added a new “uvm” command to the command-line interface in the transcript window (or via “.do” files):

uvm subcommand [args...] 
 

where the “subcommand” lets you choose from a number of options. The default subcommand (and in my opinion, the coolest) is the “call” command, which allows you to call UVM functions directly from the command line. You can even call functions in UVM components by referring to the components via their hierarchical name

uvm call test_top.env1.fab.get_full_name
 

or via a handle provided by Questa (as seen in the Class Instances window).

call @myClassType@223.get_full_name 
 

There are other useful UVM commands that I won’t go into here, but you should definitely check them out. So, what are you waiting for? To find out more information about Questa with this link: http://www.mentor.com/products/fv/questa/

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27 February, 2013

Hi Everyone,
Just wanted to let you all know that the new issue of Verification Horizons is now available. You can get the full edition online at the Verification Academy. Please be sure to check it out. There are a few articles in particular that I’d like to call your attention to.

Using Formal Analysis to “Block and Tackle” by Paul B. Egan of Rockwell Automation is a great case study in how apply formal to reduce verification time at both the block and chip level by plugging coverage holes missed by simulation. In the article, Paul describes a straightforward three-step process to add formal analysis to your verification flow.

In Bringing Verification and Validation under One Umbrella my colleagues Hemant Sharma and Hans van der Schoot present a unified flow for RTL verification and pre-silicon validation of hardware/software integration by reusing your transaction-level testbench from simulation to emulation.

Be sure the check out The Evolution of UPF: What’s Next? by Erich Marschner. Erich is the chair of the IEEE 1801 committee, which just released UPF 2.1, so there is no one better to explain the new features in this latest release. You can also read about the evolution of features in UPF from 1.0 to 2.1 in a previous issue of Horizons here.

Our friends at CVC list the Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features, and Mark Litterick of Verilab (and recent Best Paper winner at DVCon 2013 – congratulations!) shares his experiences of OVM-to-UVM migration in OVM to UVM Migration, or “There and Back Again: A Consultant’s Tale.”

We’re already working on our DAC edition of Verification Horizons, so if you’d like to submit an article, we’d love to have you.

-Tom

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