Dave Rich Featured on EEWeb

I’m sure many of you know my colleague, Dave Rich. I’ve known Dave since our days at Co-Design Automation when we worked together defining the Superlog language, which eventually became SystemVerilog after being donated to Accellera. Hard to believe that was 11 years ago. Having gotten to know Dave as a friend as well as a colleague over that time, I really enjoyed learning even more about him in his recent interview as the Featured Engineer on EEWeb.

It’s been a great source of pride, both personal and professional, to be able to say that I’ve worked for over 10 years with the person who probably knows more about SystemVerilog than anyone else on the planet. Back when I was working on the IEEE 1364 Verilog standard, whenever there was confusion about spec, we always used to say “what does Verilog-XL do?” With SystemVerilog, whenever there’s a question about the spec, I just ask Dave (and you should too).

Congratulations, Dave!

Post Author

Posted May 12th, 2012, by

Post Tags

Post Comments

No Comments

About Verification Horizons BLOG

This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool. Verification Horizons BLOG

@dennisbrophy Tweets

  • Loading tweets...

@dave_59 Tweets

  • Loading tweets...

Comments

Add Your Comment

Archives