Archive for May, 2012
As Editor of Verification Horizons, I’d like to point out a couple of articles that you really need to check out, if you haven’t already. If you want to take a look at full issues of Horizons, you can find them here.
I’m sure many of you have found yourselves in the painful situation of trying to track down a hard-to-reach coverage hole only to find out, after way too much time, that the coverage item is actually unreachable. If you have, then you need to read “Using Formal Technology To Improve Coverage Results,” which will explain the unique ability of formal technology in Questa to improve coverage results while reducing the amount of time wasted trying to hit unreachable states.
The other article I want you to be sure and check out is ” Automation Management: Are You Living a Scripted Life?” In it, you’ll learn how Questa’s Verification Run Manager will help you automate your verification process so you can focus on verifying your designs and not on debugging your environment infrastructure. As you’ll see, the proper application of automation lets you boost the productivity of your verification engineers while reducing the maintenance burden on your CAD teams. This article is actually the third in a series on Verification Management, and you can check out the first two articles here and here.
The DAC issue of Verification Horizons is coming soon, so be sure to take a look.
Where might our paths cross?
It is always challenge to fit all the needed visits in during the Design Automation Conference (DAC). If you happen to like some of the same events I attend, then the chances are good our paths might cross in public.
Saturday and Sunday are busy with an Accellera Systems Initiative board meeting. Split across two days, Accellera board members will meet to conduct traditional business and do some strategic planning in which each board member outlines what they aspire the goals and objectives for the group should be in the coming year. Intel has graciously granted space in their San Francisco offices, so I won’t be around the Moscone Center during the pre-conference setup phase. (By the way, Thank you Intel!)
After we close the Accellera board meeting on Sunday, I plan to attend the pre-DAC events on Sunday that include the EDAC reception (registration required) at 6:00pm (San Francisco Marriott, Salon 7) and Gary Smith’s “Sunday Night at DAC” at 7:00pm (San Francisco Marriott, Salon 6).
During the conference I will spend most of my time at the Mentor Graphics Verification Academy Booth #1514 and on Wednesday split my time between there and the Accellera Systems Imitative meetings. And just in case you may note that most of my evenings are not scheduled, they are with customer activities.
When the show floor is open, you will find me most of the time at the Verification Academy Booth #1514. I will join Mentor’s Harry Foster there were user and partner presentations will be done on UVM applications, updates on Harry’s research results, updates on important verification standards from Mentor’s perspective and more. You are invited to join other verification experts for the Tuesday evening cocktail reception at the Verification Academy Booth. (And the cocktail hour may be just the thing that tis needed before the annual DAC Birds-Of-A-Feather meetings begin to help the conversations start.)
Verification Academy DAC Schedule
|Monday, June 4th||Tuesday, June 5th||Wednesday, June 6th|
10:00 – Simulation and Formal Assertion-Based Verification
Harry Foster, Mentor Graphics
9:30 – Using the UVM Register Layer
10:00 – Bringing UVM to Life
11:00 – Bringing UVM to Life
10:00 – Generating Coverage Models and Achieving Coverage Closure
11:00 – Resistance is Futile: Learning to love UVM!
2:00 – Verification of Low Power SoCs with IEEE UPF
2:00 – Bringing UVM to Life
2:00 – Automating Assertion Based Verification with NextOp and Mentor Graphics
3:00 - Evolving Trends in Functional Verification
3:00 - Evolving Trends in Functional Verification
3:00 – UVM Express
4:00 – An Introduction to AMBA 4 AXI Coherency Extensions (ACE) and Verification Challenges
4:00 - Evolving Trends in Functional Verification
5:00 - Using Rules-Based Integration to Develop a SoC-Level UVM Verification Environment
5:00 – Meet the Verification Experts Cocktail Reception
Accellera Systems Initiative will host a set of meetings on Wednesday starting with a luncheon to roll out the Unified Coverage Operability Standard (UCIS). The lunch is free and seating is limited and registration is required.
Hosted Luncheon and Technical Presentation
Accellera Systems Initiative Rolls Out the Unified Coverage Interoperability Standard
Speaker: Dr. Richard Ho, Co-Chair of the UCIS Technical Subcommittee
Coverage metrics are critical to measuring and guiding design verification. As designs have grown, increasingly advanced verification technologies, methods and additional metrics have been designed to form a fuller coverage model. There is currently no single metric that consistently and globally tells engineers the exact status of verification. But one step in the right direction is to bring all types of coverage metrics into a single database that can be accessed in an industry standard way. The UCIS facilitates the creation of a unified coverage database that allows for interoperability of coverage data across multiple tools from multiple vendors.
This presentation, intended for verification managers and tool developers alike, provides an introduction to and overview of the UCIS and how users plan to utilize it to enhance their verification flows. We provide a survey of many of the commonly-used coverage metrics and how they are modeled in the UCIS. The information that users will be able to access through the UCIS will allow them to write their own applications to analyze, grade, merge and report coverage from one or more databases from one or more tool vendors. We will also discuss the XML-based interchange format of UCIS, which provides a path to exchange coverage databases without requiring a common code library between tools and vendors.
SystemC User Group Meeting
North American SystemC User’s Group Meeting
Wednesday, June 6, 2:00-6:00pm
Moscone Center, Room 262
Register Now >
This event is open to all DAC attendees. Seating is limited!
The North American SystemC Users Group (NASCUG) provides a unique forum for sharing SystemC experiences and knowledge among industry, research and universities. The agendafor the event has a lot offer user group attendees.
Mentor’s Adam Erickson will present An Open-Source, Standards-Based Library for Achieving Interoperability Between TLM Models in SystemC and SystemVerilog. Adam’s presentation is scheduled to start at 3:00pm.
I’m sure many of you know my colleague, Dave Rich. I’ve known Dave since our days at Co-Design Automation when we worked together defining the Superlog language, which eventually became SystemVerilog after being donated to Accellera. Hard to believe that was 11 years ago. Having gotten to know Dave as a friend as well as a colleague over that time, I really enjoyed learning even more about him in his recent interview as the Featured Engineer on EEWeb.
It’s been a great source of pride, both personal and professional, to be able to say that I’ve worked for over 10 years with the person who probably knows more about SystemVerilog than anyone else on the planet. Back when I was working on the IEEE 1364 Verilog standard, whenever there was confusion about spec, we always used to say “what does Verilog-XL do?” With SystemVerilog, whenever there’s a question about the spec, I just ask Dave (and you should too).
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- Even More UVM Debug in Questa 10.2
- IEEE Approves New Low Power Standard
- May 2013 (2)
- April 2013 (2)
- March 2013 (2)
- February 2013 (5)
- January 2013 (1)
- December 2012 (1)
- November 2012 (1)
- October 2012 (4)
- September 2012 (1)
- August 2012 (1)
- July 2012 (6)
- June 2012 (1)
- May 2012 (3)
- March 2012 (1)
- February 2012 (6)
- January 2012 (2)
- December 2011 (2)
- November 2011 (2)
- October 2011 (3)
- September 2011 (1)
- July 2011 (3)
- June 2011 (6)
- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
- May 2011 (2)
- April 2011 (7)
- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
- March 2011 (5)
- February 2011 (4)
- January 2011 (1)
- December 2010 (2)
- October 2010 (3)
- September 2010 (4)
- August 2010 (1)
- July 2010 (3)
- June 2010 (9)
- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
- February 2010 (5)
- January 2010 (5)
- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
- September 2009 (2)
- July 2009 (1)
- May 2009 (1)