Is my car trying to tell me something?
This past Friday was the beginning of a two day internal functional verification meeting at Mentor Graphics corporate headquarters on Intelligent Testbench Automation (iTBA). (Mentor’s iTBA product, Questa inFact is hot and getting hotter.) After getting to my car to return home at the end of the first day, I was thinking that the large interest in this technology – demonstrated by a standing room only training event – has got to be a tipping point indication for iTBA.
I turned my car on. (Actually, I “pushed” it on as there is no place to put a key to turn anymore.)
Moments after starting my car a winter storm alert interrupted the music on the radio and displayed two notices. One I am familiar with when the temperature falls and snow begins to collect on the mountain passes. I’m not going to drive in the direction of the snow, so no problem. The other alert was of grave concern. It was a tornado watch. And the tornado watch was not off in some other direction many miles away, it was “0 miles” from me. I looked up, I scanned the horizon and dark black was in one direction and sun in the other. I changed the radio channel to a local AM evening drive station, but no mention of a tornado watch. I headed in the direction of the sun. It seemed the safest direction to head. But before I did, I snapped a quick picture as proof I actually read “Tornado Watch” on the car’s navigation screen.
iTBA to the Rescue?
I returned to ponder if functional verification has just gotten too big for current techniques that iTBA is going from a nice to have, to a must have.
Several years back it was popular to brag about the compute farms & ranches one had. With 5,000 machines here and another 5,000 machines there it seemed a sane demonstration of one’s design and verification prowess. But this gave way to 50,000 multicore machines and who is talking about this with pride? All talk is out of necessity. And what about the next step? Who has 500,000 or 5,000,000 on the drawing board or in their data centers? Looking around, it seems very few admit to more than 100,000 and even fewer have more than 500,000.
Verification may be in crisis, as many will say, but it you hold verification technology constant, it is not in crisis, is on a collision coarse with disaster. Addressing this crisis has been the theme of many of Mentor Graphics CEO Wally Rhines’ keynotes at DVCon. His 2011 keynote was taken to heart by many who attended. The need to improve by a several orders of magnitude the “Velocity of Verification” has been followed by several examples over the year.
One example was shared several months after DVCon when Mentor Graphics and TSMC announced we had partnered to validate advanced functional verification technology. While not all test results at TSMC or our common customer, AppliedMicro, were revealed, one of the slower tests demonstrated the value of iTBA to shorten time-to-coverage by over 100x. Even days after that announcement we disclosed Mentor’s Veloce emulation platform offered 400x OVM/UVM driven verification improvement.
100x and 400x seem like a large numbers, but it appears even bigger when you put it into the context of the time it was measured. With current constrained random techniques, a project that takes 6 weeks of simulator run time to reach 100% closure can reach it in about 10 hours with Questa inFact or about 2.5 hours with Veloce. Instead of using complex scripts to peek in on a simulation run over the course of a month and a half, a verification team could actually leave work for the day, return the next morning and have a full, complete and exhaustive verification run. And when even faster turnaround time is needed, emulation returns results during the work day.
SoC Verification: A Balance of simulation, iTBA & emulation
Wally’s DVCon 2011 keynote referenced 8 customer results coming from Mentor’s Questa inFact tool. Many more have discovered what this can do for them as well. And with each success, come the requests from more to see what it can do for them.
But changing the “Velocity of SoC Verification” has not rested on one technique alone. Stop by the Mentor Graphics DVCon booth and we can share with you the advances we have made to address system-level verification since last year.
Crossing The Chasm
Which brings me to the point of the “Tornado Watch.” As I pondered the iTBA tipping point, about “how little things can make big differences” as can be found in Malcolm Gladwell’s book, my car must have been channeling Geoffrey Moore of “Crossing The Chasm” fame instead. For that reason it must have issued the Tornado Watch. Could it be that iTBA is set to cross the chasm from early adopters to the early majority?
And thankfully, I don’t think my car is programmed to issue tipping point warnings, nor do I want to see if it can.
In the end, it will be with the benefit of hindsight that let’s us know if we are crossing the chasm into the tornado or not now or soon. But for Mentor’s part, full and advanced support of iTBA technology with Questa inFact is ready now, and we are set to cross the chasm into the tornado. My colleague, Mark Olen, blogs about iTBA here. If you have not had a chance yet to read his blog on iTBA delivering 10x to 100x faster functional verification, it is worth the time to do so. You can look for him to give frequent updates on iTBA and comment on the positive impact is has on SoC design and verification teams in the months ahead.
I look forward to seeing you at DVCon.
Posted February 21st, 2012, by Dennis Brophy
- Loading tweets...
- Loading tweets...
- Loading tweets...
- Epilogue: The 2012 Wilson Research Group Functional Verification Study
- New Verification Horizons Issue Available
- Happy Halloween from ARM TechCon
- IEEE Standards Association Symposium on EDA Interoperability
- STMicroelectronics: Simulation + Emulation = Verification Success
- A Decade of SystemVerilog: Unifying Design and Verification?
- Part 12: The 2012 Wilson Research Group Functional Verification Study
- Part 11: The 2012 Wilson Research Group Functional Verification Study
- Part 10: The 2012 Wilson Research Group Functional Verification Study
- Part 9: The 2012 Wilson Research Group Functional Verification Study
- November 2013 (2)
- October 2013 (3)
- September 2013 (2)
- August 2013 (4)
- July 2013 (6)
- Part 7: The 2012 Wilson Research Group Functional Verification Study
- Walking in the Desert or Drinking from a Fire Hose?
- Part 6: The 2012 Wilson Research Group Functional Verification Study
- A Short Class on SystemVerilog Classes
- Part 5: The 2012 Wilson Research Group Functional Verification Study
- Part 4: The 2012 Wilson Research Group Functional Verification Study
- June 2013 (2)
- May 2013 (4)
- April 2013 (2)
- March 2013 (2)
- February 2013 (5)
- January 2013 (1)
- December 2012 (1)
- November 2012 (1)
- October 2012 (4)
- September 2012 (1)
- August 2012 (1)
- July 2012 (6)
- June 2012 (1)
- May 2012 (3)
- March 2012 (1)
- February 2012 (6)
- January 2012 (2)
- December 2011 (2)
- November 2011 (2)
- October 2011 (3)
- September 2011 (1)
- July 2011 (3)
- June 2011 (6)
- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
- May 2011 (2)
- April 2011 (7)
- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
- March 2011 (5)
- February 2011 (4)
- January 2011 (1)
- December 2010 (2)
- October 2010 (3)
- September 2010 (4)
- August 2010 (1)
- July 2010 (3)
- June 2010 (9)
- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
- February 2010 (5)
- January 2010 (5)
- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
- September 2009 (2)
- July 2009 (1)
- May 2009 (1)