UVM: Some Thoughts Before DVCon
It is time to talk about what happens next with UVM
The Design and Verification Conference (DVCon) has become the premier event to discuss front-end design issues with an emphasis on verification. If one listens to the Conversation Central interview of DVCon leadership it is clear how singularly important DVCon is. As one of the three organizers of the UVM Tutorial on Monday, I know the conference organizers had to rearrange the room layout to accommodate a greater than expected number of registrant. It is clear how important the topic of verification is and UVM in particular has become.
It seems to me that DVCon is the right place to discuss what comes next with UVM. I have three thoughts about UVM that I think merit discussion.
1. UVM needs a period of stability
While the experts at the Accellera Verification IP Technical Subcommittee (VIP-TSC) standardization table (all good people) continue to hone UVM and debate a few more features they need, they have been unable to make significant progress on those features since last DVCon. The one major item promised beyond OVM, an update to phasing, remains an open topic. Mentor has suggested in committee that we allow another year to pass and suspend committee action on this. Maybe the natural market forces would allow several options to surface, be user-tested and then merit consideration by the VIP-TSC.
This is in keeping with Karen Bartleson’s 9th Commandment for Effective Standards: “Start with Donations; Not From Scratch.” This is what is happening now with Phasing. The design by committee process is moving slowly. It is not the slow part that concerns me, however.
Completing the “last” thing has many in the verification community waiting until it is done before they migrate and adopt UVM. The best thing the committee could do to encourage use is to give the users certainty that UVM will not change in the next 12 months. At the same time, the committee could commit to take input from users at the end of those 12 months as a guide to what it does next.
2. UVM needs a simple path to first use
Accellera has an approved and published standard, an open-source implementation and embedded UVM User’s Guide. This is a lot to digest. And while one may expect the User’s Guide to help, it calls the reader to supplement it with “education, experience and professional judgment.” It warns that “not all aspects of this guide may be applicable in all circumstances.”
Users should be offered an unambiguous, easy-to-use and understand means to adopt UVM without having to know everything about it before starting to use it. UVM was not made for just those who have large verification teams and central CAD groups. Those large teams are the ones who are already using UVM. The first step to UVM adoption for the rest of the world should not be too high as it currently is.
UVM needs a simple path for fast adoption.
3. UVM needs to bridge the system domain
Accellera System Initiative has come to life from the unification of Accellera and OSCI. While the vision to bring the two organizations together is without fault, the lack of a publicly visible plan to leverage each others strengths is noted by Gabe Moretti in his recent blog on DVCon when he wrote: “First we build it and then we figure out how to use it has never been a good architectural approach, especially in electronics.” His comment was in response to the questions to be asked at DVCon’s Monday lunch about what the new organization should look like. Gabe certainly thought “the creators of the organization must have some ideas of the focus, mission and goals.”
I certainly do. In the case of UVM, I think it needs a bridge between the SystemVerilog world in which it was written and the SystemC world of design and modeling. As teams move to higher levels of abstraction for system-level architectural exploration and definition, the need for efficient and reusable functional models has become an imperative.
It is no secret to the Accellera VIP-TSC that Mentor Graphics thinks this is needed. Our presentation to committee members on a UVM API to facilitate this outlines exactly what we think should be done to address reusable functional models in the system world. [Accellera requires registration to download the Mentor presentation. Accellera members can register here. Guests require VIP-TSC leadership permission and can request it here.]
UVM must grow and bridge the system world. The Accellera SystemC Verification Working Group (VWG) knows this. They have a meeting planned at the DATE conference to discuss future evolutions related to SystemC and Verification on 14 March 2012 from 1230-1340 in Conference Room 4 which I plan to attend. The VWG meeting is open to external participants, not just Accellera members.
I don’t know what your thoughts about what should happen next with UVM are. Feel free to share them here if you wish or join me at DVCon or DATE and we can discuss it with the whole community. Maybe there is hope we can make progress on these three areas in the coming year.
Posted February 17th, 2012, by Dennis Brophy
- Loading tweets...
- Loading tweets...
- Loading tweets...
- Epilogue: The 2012 Wilson Research Group Functional Verification Study
- New Verification Horizons Issue Available
- Happy Halloween from ARM TechCon
- IEEE Standards Association Symposium on EDA Interoperability
- STMicroelectronics: Simulation + Emulation = Verification Success
- A Decade of SystemVerilog: Unifying Design and Verification?
- Part 12: The 2012 Wilson Research Group Functional Verification Study
- Part 11: The 2012 Wilson Research Group Functional Verification Study
- Part 10: The 2012 Wilson Research Group Functional Verification Study
- Part 9: The 2012 Wilson Research Group Functional Verification Study
- November 2013 (2)
- October 2013 (3)
- September 2013 (2)
- August 2013 (4)
- July 2013 (6)
- Part 7: The 2012 Wilson Research Group Functional Verification Study
- Walking in the Desert or Drinking from a Fire Hose?
- Part 6: The 2012 Wilson Research Group Functional Verification Study
- A Short Class on SystemVerilog Classes
- Part 5: The 2012 Wilson Research Group Functional Verification Study
- Part 4: The 2012 Wilson Research Group Functional Verification Study
- June 2013 (2)
- May 2013 (4)
- April 2013 (2)
- March 2013 (2)
- February 2013 (5)
- January 2013 (1)
- December 2012 (1)
- November 2012 (1)
- October 2012 (4)
- September 2012 (1)
- August 2012 (1)
- July 2012 (6)
- June 2012 (1)
- May 2012 (3)
- March 2012 (1)
- February 2012 (6)
- January 2012 (2)
- December 2011 (2)
- November 2011 (2)
- October 2011 (3)
- September 2011 (1)
- July 2011 (3)
- June 2011 (6)
- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
- May 2011 (2)
- April 2011 (7)
- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
- March 2011 (5)
- February 2011 (4)
- January 2011 (1)
- December 2010 (2)
- October 2010 (3)
- September 2010 (4)
- August 2010 (1)
- July 2010 (3)
- June 2010 (9)
- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
- February 2010 (5)
- January 2010 (5)
- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
- September 2009 (2)
- July 2009 (1)
- May 2009 (1)