Archive for December, 2011
Instant Replay Offers Multiple Views at Any Speed
If you’ve watched any professional sporting event on television lately, you’ve seen the pressure put on referees and umpires. They have to make split-second decisions in real-time, having viewed ultra-high-speed action just a single time. But watching at home on television, we get the luxury of viewing multiple replays of events in question in high-definition super-slow-motion, one frame at a time, and even in reverse. We also get to see many different views of these controversial events, from the front, the back, the side, up close, or far away. Sometimes it seems there must be twenty different cameras at every sporting event.
Wouldn’t it nice if you could apply this same principle to your SoC level simulations? What if you had instant replay from multiple viewing angles in your functional verification toolbox? It turns out that such a technology indeed exists, and it’s called “Codelink Replay”.
Codelink Replay enables verification engineers to use instant replay with multiple viewing angles to quickly and accurately debug even the most complex SoC level simulation failures. This is becoming increasingly important, as we see in Harry Foster’s blog series about the 2010 Wilson Research Group Functional Verification Study that over half of all new design starts now contain multiple embedded processors. If you’re responsible for verifying a design with multiple embedded cores such as ARM’s new Cortex A15 and Cortex A7 processors, this technology will have a dramatic impact for you.
Multi-Core SoC Design Verification
Multi-core designs present a whole new level of verification challenges. Achieving functional coverage of your IP blocks at the RTL level has become merely a pre-requisite now – as they say “necessary but not sufficient”. Welcome to the world of SoC level verification, where you use your design’s software as a testbench. After all, since a testbench’s role is to mimic the design’s target environment, so as to test its functionality, how better to accomplish this than to execute the design’s software against its hardware, albeit during simulation?
Some verification teams have already dabbled in this world. Perhaps you’ve written a handful of tests in C or assembly code, loaded them into memory, initialized your processor, and executed them. This is indeed the best way to verify SoC level functionality including power optimization management, clocking domain control, bus traffic arbitration schemes, driver-to-peripheral compatibility, and more, as none of these aspects of an SoC design can be appropriately verified at the RTL IP block level.
However, imagine running a software testbench program only to see that the processor stopped executing code two hours into the simulation. What do you do next? Debugging “software as a testbench” simulation can be daunting. Especially when the software developers say “the software is good”, and the hardware designers say “the hardware is fine”. Until recently, you could count on weeks to debug these types of failures. And the problem is compounded with today’s SoC designs with multiple processors running software test programs from memory.
This is where Codelink Replay comes in. It enables you to replay your simulation in slow motion or fast forward, while observing many different views including hardware views (waveforms, CPU register values, program counter, call stack, bus transactions, and four-state logic) and software views (memory, source code, decompiled code, variable values, and output) – all remaining in perfect synchrony, whether you’re playing forward or backward, single-step, slow-motion, or fast speed. So when your simulation fails, just start at that point in time, and replay backwards to the root of the problem. It’s non-invasive. It doesn’t require any modifications to your design or to your tests.
Debugging SoC Designs Quickly and Accurately
So if you’re under pressure to make fast and accurate decisions when your SoC level tests fail, you can relate to the challenges faced by professional sports referees and umpires. But with Codelink Replay, you can be assured that there are about 20 different virtual “cameras” tracing and logging your processors during simulation, giving you the same instant replay benefit we get when we watch sporting events on television. If you’re interested to learn more about this new technology, check out the web seminar at the URL below, that introduces Codelink Replay, and shows how it supports the entire ARM family of processors, including even the latest Cortex A-Series, Cortex R-Series, and Cortex M-Series.
The DASC Participates in IEEE Standards Association Gala Event
The IEEE Computer Society Design Automation Standards Committee (DASC) participated in the annual IEEE Standards Association (SA) Award ceremony held in New Brunswick, NJ USA on 4 December 2011. Hundreds met to recognize the work of thousands who volunteer daily to develop standards and to honor the few who are exceptional examples.
The DASC recognized Larry Saunders as its “Ron Waxman Design Automation Standards Committee Meritorious Service Award” recipient. Larry was recognized “for pioneering the standardization of VHDL that fundamentally changed the electronic system design process.”
As someone who has worked with Larry on and off over the years to promote the use of VHDL, I know firsthand he is very deserving of this recognition and it was a pleasure to be present as he, one of the renowned VHDL fathers, was given this award. Yatin Trivedi, vice-chair of the DASC and director of standards at Synopsys gave a glowing tribute to Larry, not just from his DASC leadership role, but as a colleague, friend and mentor.
In addition to the “Ron Waxman” award, the IEEE-SA Working Group Chair Awards were also officially recognized. From the DASC, two of the working groups completed standards development and published their work and a few members of each of those groups were given Working Group Chair awards.
1076.1.1™-2010 IEEE Standard for VHDL Analog and Mixed-Signal Extensions – Packages for Multiple Energy Domain Support
Tom Alderton, Peter J. Ashendon, Ernst Christen, David W. Smith
1647™-2011 IEEE Standard for the Functional Verification Language e
Mike Bartley, Darren Galpin, Amy Witherow
Yatin’s citation for the Ron Waxman Award, Ron’s additional background on Larry’s contributions and Larry’s acceptance video can be seen below. The microphone was a bit away from the speakers and it was recorded at some distance from the speakers so the sound may be a bit hard to hear unless you use headphones. But for those who were not there and might like to see it, it is offered for you.
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This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
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