Worlds Standards Day 2011
Creating Confidence Globally
Today, 14 October 2011, is the day the world celebrates standards. The leadership of the IEC, ISO and ITU issued a message in support of it that clearly articulates the role standards play in safety, reliability, interoperability, their impact on business efficiency and more.
And from time-to-time, I have had the opportunity to join the celebration the American National Standards Institute (ANSI) in the United States hosted when the international community for electronic design automation specialists would gather in Washington, D.C. The highlight of the celebration in the United States is the presentation of the “Ronald Brown Standards Leadership Award” and the results from the Worlds Standards Day Paper Competition.
Ron Brown, Commerce Secretary in the United States until his untimely death in a plane crash in Croatia in 1996, is the namesake of the award. He was an inspiration to promote the role of standardization to eliminate global barriers to trade. ANSI honors this spirit annually, by naming their award after him. When this year’s award recipient is announced, they will join a long list of other important people recognized as well.
The winner of the 2011 World Standards Day paper competition will also be announced. This year, ANSI selected the theme of “Advancing Safety and Sustainability Standards.” Past year winners and their papers can be found here. One of my favorite papers was the 1999 paper, The Yin and Yang of Standards Development. The paper juxtaposed formal standards development against that of consortia.
While I won’t say one is right or wrong, I can say I offer leadership to the international bodies, like IEC, the formal bodies, like the IEEE and consortia like Accellera. If you have some take on this, I would be more than interested to hear. For electronic design automation, a good example of respecting the value of each of these is offered by SystemVerilog. We know that SystemVerilog started as donations from many sources that became an Accellera standard. After a year of stabilization, it was transferred to the IEEE for further maintenance and updates. And when the IEEE finished its work, it was offered to the IEC under the IEEE/IEC dual-logo program as an international standard. At each phase of development, a new level of “confidence” was established for consumers and producers.
This brings me back to this year’s tag line of creating confidence globally.
I would like to see some finality from Accellera to complete its initial Universal Verification Methodology (UVM) commitments. A large overhang exists given the fact the commitment to close on an update to Phasing remains unsatisfied and incomplete. Maybe one thing to recognize is we can’t do everything at once and so a little is better than none right now. Or, maybe even, keeping OVM’s phasing scheme is sufficient and add no phasing extensions. The lack of finality does not engender nor instill confidence in the global market that UVM should be adopted now. We need to be doing what we can to create the global confidence that sets the perception UVM is ready to use and adopt now.
While we celebrate Worlds Standards Day 2011, let us think of what we can do to Create Confidence Globally. And maybe we should focus on UVM.
Note: Click here for information on prior World Standards Day themes.
- Loading tweets...
- Loading tweets...
- Loading tweets...
- DVCon 2014 Issue of Verification Horizons Now Available
- DVCon–The FREE Side
- More DVCon–More Mentor Tutorials!
- UVM 1.2: Open Public Review
- DVCon 2014: Standards on Display
- Just because FPGAs are programmable doesn’t mean verification is dead
- Managing Verification Coverage Information
- Epilogue: The 2012 Wilson Research Group Functional Verification Study
- New Verification Horizons Issue Available
- Happy Halloween from ARM TechCon
- March 2014 (1)
- February 2014 (5)
- January 2014 (1)
- November 2013 (2)
- October 2013 (3)
- September 2013 (2)
- August 2013 (4)
- July 2013 (6)
- Part 7: The 2012 Wilson Research Group Functional Verification Study
- Walking in the Desert or Drinking from a Fire Hose?
- Part 6: The 2012 Wilson Research Group Functional Verification Study
- A Short Class on SystemVerilog Classes
- Part 5: The 2012 Wilson Research Group Functional Verification Study
- Part 4: The 2012 Wilson Research Group Functional Verification Study
- June 2013 (2)
- May 2013 (4)
- April 2013 (2)
- March 2013 (2)
- February 2013 (5)
- January 2013 (1)
- December 2012 (1)
- November 2012 (1)
- October 2012 (4)
- September 2012 (1)
- August 2012 (1)
- July 2012 (6)
- June 2012 (1)
- May 2012 (3)
- March 2012 (1)
- February 2012 (6)
- January 2012 (2)
- December 2011 (2)
- November 2011 (2)
- October 2011 (3)
- September 2011 (1)
- July 2011 (3)
- June 2011 (6)
- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
- May 2011 (2)
- April 2011 (7)
- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
- March 2011 (5)
- February 2011 (4)
- January 2011 (1)
- December 2010 (2)
- October 2010 (3)
- September 2010 (4)
- August 2010 (1)
- July 2010 (3)
- June 2010 (9)
- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
- February 2010 (5)
- January 2010 (5)
- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
- September 2009 (2)
- July 2009 (1)
- May 2009 (1)