VHS or Betamax?
Legacy’s Luster Lost
As a follow-on to my last blog, where I shared information about Harry Foster speaking live about the research he has been reporting on the last year and where I noted legacy might hold some back, I was going to finish on some of the work we have done at Mentor Graphics to move forward while trying to keep some of those held back by legacy, whole.
Buy why this title? For some, there may be no recollection of what VHS or Betamax are. And if I were to say it is a format used to tape record video, that still might not help given DVD, MP4, etc. If I were to even say there was once a format war over these two, one could easily shrug one’s shoulder and proclaim they both lost. And that is true.
What do we record on today? Precisely, the answer is neither of these for all but an obscure few. But it was towards the end of this format war I left one area to move to another. VHS had all but become the format of that area for video rentals, while the area I moved to was evenly split between the two formats. I had selected Betamax. I can go into great detail to explain the technical advantages of the format. But those words are all lost on the market forces that ushered in VHS. And thanks to continued innovation, these legacy formats have lost their luster. We have all moved on.
Be Kind – Rewind
As SystemVerilog has become the dominant language standard for verification, the methodology work aggregated in Accellera’s Verification IP Technical Subcommittee (VIP-TSC) where it built the Universal Verification Methodology (UVM). While UVM leverages SystemVerilog, the market’s move from legacy formats has left some who still use those formats to ask if the industry can be “kind, and rewind” – to still support them.
While Accellera’s UVM has been open to bring the dogma of all market participants together to create a single coherent standard, that has not met with total satisfaction of legacy users. What now appears to be more liked by them is a wholesale translation of UVM in SystemVerilog to legacy languages. What’s the value in that? Does one gain greater productivity from this?
Accellera hopes to bridge this divide with a return to its first phase of verification IP interoperability work to suggest additional ways to interoperate. For up-to-the-minute information on this, I suggest you get involved with the group. Full information about the group is only available in the membership area – and everyone is invited to be an observing member. But we should expect Accellera to talk about better bridges to those formats important to those sitting around the standardization table.
But I still come back to the question about what’s the value in this. It is time to move forward or be stuck in the past? The format is not the value; the algorithms to do better and faster verification are. To that end, for the users of the e language, Mentor Graphics has extended its Intelligent Testbench Automation (iTBA) technology to work in an e environment.
Many UVM (and OVM) users have found they have been able to achieve their coverage goals 10x to 100x faster than before with this innovative technology. And it is now readily available to the 10-15% who still use e. For more information about leveraging iTBA, you can visit the Verification Academy where one of the new modules that was added in the iTBA section, titled Integrating iTBA into an ‘e’ Environment, is ready for viewing and explains how this is done. [Note: Registration is required to view the module and certain restrictions apply.] This module describes integrating Intelligent Testbench Automation into an e environment, re-using existing eVCs, and achieving functional coverage >10X faster.
While legacy language users may fret about their preferred language, the market has already spoken. Maybe it is time to explore how advanced verification algorithms can be back ported to support legacy to ease the transition. After all, its not the language, it’s the algorithms. Go online and see what the advance algorithms can offer you. Or, join us next week in San Jose, CA at the Verification Seminar.
Posted October 13th, 2011, by Dennis Brophy
- Loading tweets...
- Loading tweets...
- Loading tweets...
- Mentor Enterprise Verification Platform Debuts
- New Verification Academy ABV Course
- DVCon 2014 Issue of Verification Horizons Now Available
- DVCon–The FREE Side
- More DVCon–More Mentor Tutorials!
- UVM 1.2: Open Public Review
- DVCon 2014: Standards on Display
- Just because FPGAs are programmable doesn’t mean verification is dead
- Managing Verification Coverage Information
- Epilogue: The 2012 Wilson Research Group Functional Verification Study
- April 2014 (1)
- March 2014 (2)
- February 2014 (5)
- January 2014 (1)
- November 2013 (2)
- October 2013 (3)
- September 2013 (2)
- August 2013 (4)
- July 2013 (6)
- Part 7: The 2012 Wilson Research Group Functional Verification Study
- Walking in the Desert or Drinking from a Fire Hose?
- Part 6: The 2012 Wilson Research Group Functional Verification Study
- A Short Class on SystemVerilog Classes
- Part 5: The 2012 Wilson Research Group Functional Verification Study
- Part 4: The 2012 Wilson Research Group Functional Verification Study
- June 2013 (2)
- May 2013 (4)
- April 2013 (2)
- March 2013 (2)
- February 2013 (5)
- January 2013 (1)
- December 2012 (1)
- November 2012 (1)
- October 2012 (4)
- September 2012 (1)
- August 2012 (1)
- July 2012 (6)
- June 2012 (1)
- May 2012 (3)
- March 2012 (1)
- February 2012 (6)
- January 2012 (2)
- December 2011 (2)
- November 2011 (2)
- October 2011 (3)
- September 2011 (1)
- July 2011 (3)
- June 2011 (6)
- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
- May 2011 (2)
- April 2011 (7)
- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
- March 2011 (5)
- February 2011 (4)
- January 2011 (1)
- December 2010 (2)
- October 2010 (3)
- September 2010 (4)
- August 2010 (1)
- July 2010 (3)
- June 2010 (9)
- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
- February 2010 (5)
- January 2010 (5)
- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
- September 2009 (2)
- July 2009 (1)
- May 2009 (1)