Archive for October, 2011
Creating Confidence Globally
Today, 14 October 2011, is the day the world celebrates standards. The leadership of the IEC, ISO and ITU issued a message in support of it that clearly articulates the role standards play in safety, reliability, interoperability, their impact on business efficiency and more.
And from time-to-time, I have had the opportunity to join the celebration the American National Standards Institute (ANSI) in the United States hosted when the international community for electronic design automation specialists would gather in Washington, D.C. The highlight of the celebration in the United States is the presentation of the “Ronald Brown Standards Leadership Award” and the results from the Worlds Standards Day Paper Competition.
Ron Brown, Commerce Secretary in the United States until his untimely death in a plane crash in Croatia in 1996, is the namesake of the award. He was an inspiration to promote the role of standardization to eliminate global barriers to trade. ANSI honors this spirit annually, by naming their award after him. When this year’s award recipient is announced, they will join a long list of other important people recognized as well.
The winner of the 2011 World Standards Day paper competition will also be announced. This year, ANSI selected the theme of “Advancing Safety and Sustainability Standards.” Past year winners and their papers can be found here. One of my favorite papers was the 1999 paper, The Yin and Yang of Standards Development. The paper juxtaposed formal standards development against that of consortia.
While I won’t say one is right or wrong, I can say I offer leadership to the international bodies, like IEC, the formal bodies, like the IEEE and consortia like Accellera. If you have some take on this, I would be more than interested to hear. For electronic design automation, a good example of respecting the value of each of these is offered by SystemVerilog. We know that SystemVerilog started as donations from many sources that became an Accellera standard. After a year of stabilization, it was transferred to the IEEE for further maintenance and updates. And when the IEEE finished its work, it was offered to the IEC under the IEEE/IEC dual-logo program as an international standard. At each phase of development, a new level of “confidence” was established for consumers and producers.
This brings me back to this year’s tag line of creating confidence globally.
I would like to see some finality from Accellera to complete its initial Universal Verification Methodology (UVM) commitments. A large overhang exists given the fact the commitment to close on an update to Phasing remains unsatisfied and incomplete. Maybe one thing to recognize is we can’t do everything at once and so a little is better than none right now. Or, maybe even, keeping OVM’s phasing scheme is sufficient and add no phasing extensions. The lack of finality does not engender nor instill confidence in the global market that UVM should be adopted now. We need to be doing what we can to create the global confidence that sets the perception UVM is ready to use and adopt now.
While we celebrate Worlds Standards Day 2011, let us think of what we can do to Create Confidence Globally. And maybe we should focus on UVM.
Note: Click here for information on prior World Standards Day themes.
Legacy’s Luster Lost
As a follow-on to my last blog, where I shared information about Harry Foster speaking live about the research he has been reporting on the last year and where I noted legacy might hold some back, I was going to finish on some of the work we have done at Mentor Graphics to move forward while trying to keep some of those held back by legacy, whole.
Buy why this title? For some, there may be no recollection of what VHS or Betamax are. And if I were to say it is a format used to tape record video, that still might not help given DVD, MP4, etc. If I were to even say there was once a format war over these two, one could easily shrug one’s shoulder and proclaim they both lost. And that is true.
What do we record on today? Precisely, the answer is neither of these for all but an obscure few. But it was towards the end of this format war I left one area to move to another. VHS had all but become the format of that area for video rentals, while the area I moved to was evenly split between the two formats. I had selected Betamax. I can go into great detail to explain the technical advantages of the format. But those words are all lost on the market forces that ushered in VHS. And thanks to continued innovation, these legacy formats have lost their luster. We have all moved on.
Be Kind – Rewind
As SystemVerilog has become the dominant language standard for verification, the methodology work aggregated in Accellera’s Verification IP Technical Subcommittee (VIP-TSC) where it built the Universal Verification Methodology (UVM). While UVM leverages SystemVerilog, the market’s move from legacy formats has left some who still use those formats to ask if the industry can be “kind, and rewind” – to still support them.
While Accellera’s UVM has been open to bring the dogma of all market participants together to create a single coherent standard, that has not met with total satisfaction of legacy users. What now appears to be more liked by them is a wholesale translation of UVM in SystemVerilog to legacy languages. What’s the value in that? Does one gain greater productivity from this?
Accellera hopes to bridge this divide with a return to its first phase of verification IP interoperability work to suggest additional ways to interoperate. For up-to-the-minute information on this, I suggest you get involved with the group. Full information about the group is only available in the membership area – and everyone is invited to be an observing member. But we should expect Accellera to talk about better bridges to those formats important to those sitting around the standardization table.
But I still come back to the question about what’s the value in this. It is time to move forward or be stuck in the past? The format is not the value; the algorithms to do better and faster verification are. To that end, for the users of the e language, Mentor Graphics has extended its Intelligent Testbench Automation (iTBA) technology to work in an e environment.
Many UVM (and OVM) users have found they have been able to achieve their coverage goals 10x to 100x faster than before with this innovative technology. And it is now readily available to the 10-15% who still use e. For more information about leveraging iTBA, you can visit the Verification Academy where one of the new modules that was added in the iTBA section, titled Integrating iTBA into an ‘e’ Environment, is ready for viewing and explains how this is done. [Note: Registration is required to view the module and certain restrictions apply.] This module describes integrating Intelligent Testbench Automation into an e environment, re-using existing eVCs, and achieving functional coverage >10X faster.
While legacy language users may fret about their preferred language, the market has already spoken. Maybe it is time to explore how advanced verification algorithms can be back ported to support legacy to ease the transition. After all, its not the language, it’s the algorithms. Go online and see what the advance algorithms can offer you. Or, join us next week in San Jose, CA at the Verification Seminar.
Is Legacy Holding You Back?
Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on the pressing SoC verification issues as he highlights recent research he has been reporting on in his numerous blogs. The first event will be held in San Jose, CA USA (18 October 2011) and the second event will be held in Reading, UK (15 November 2011).
Harry has been reporting on the 2010 Wilson Research Group Functional Verification Study that has shown a rapid market move towards the broadly supported SystemVerilog (IEEE 1800) language standard and ubiquitous support of the OVM/UVM methodologies. While humans have a general disdain for change, human nature also seems to wait to respond to the “crowd effect” to make a change. It appears the market is in the throes of this strain as the market moves in a direction leaving legacy behind.
To learn firsthand from Harry, I recommend attending two upcoming events where he will speak:
Date: 18 October 2011 (Tuesday)
Event: Design & Verification in the SoC Era
Location: DoubleTree – San Jose, CA USA
Cost: Free; registration restrictions apply
Date: 15 November 2011 (Tuesday)
Event: Verification Futures: The Next Five Years
Location: Hilton Hotel, Reading, UK
Legacy set for replacement?
Have you ever noticed that one restaurant alone may get little traffic, but if there are many restaurants clustered together, they garner much greater traffic than going it alone? The crowd effect demonstrates its power and user benefit with choice and bounty. After DVCon 2011, I blogged about Wally Rhines’ keynote address and pointed to one slide that showed SystemVerilog is the clear language winner and pointed to another slide that showed OVM/UVM, built on top of SystemVerilog, as the clear methodology winner.
This has impact on legacy. And those with entrenched legacy may find it hard to adopt market driven standards practice quickly. This is to be expected.
When Accellera began its Verification IP Technical Subcommittee (VIP-TSC), I argued that the first step is to preserve legacy investment and offer a path to reuse that which has proven valuable in the past. The vote to move in this direction was close with consumer input saying all efforts should focus on a single industry supported base class library and standard. My point was we could build it, but if there was no path from where consumers were, there would be limited uptake. In a short time, a proof that OVM and VMM could interoperate demonstrated that we knew how to do this. It also gave hope that other proprietary and single-supplier solutions could take this work and adapt it for their paths forward.
With that finished, the Accellera VIP-TSC set to create the Universal Verification Methodology (UVM) standard. This has now been completed, short of finishing one commitment to expand the Phasing scheme and address a few lingering issues. While Accellera could focus on completing this work, users and owners of legacy verification languages and proprietary environments have come to realize a startling truth: the market has moved away from them. And, proprietary and single-solution suppliers have offered little in terms of paths forward. They now look for Accellera to address legacy preservation requirements and do it for them.
While this was to be expected, their shock has exposed the fact that more work could have been done on building the bridges to legacy’s past in the initial phase rather than now when the market demands time and focus on its adopted standards practice instead.
Why bring all this up?
We now find the Accellera VIP-TSC has a bifurcated focus. Part of the focus is to complete the content promises for UVM 1.0 and the other is to preserve legacy investment. But can Accellera overcome the crowd effect? The crowd effect, after all, has taken hold. In terms of product choice, legacy offers one product from a single supplier to SystemVerilog’s multiple competitive suppliers. When it comes to bounty, the availability of legacy verification IP has fewer and fewer sources while OVM/UVM offer an expanding bounty.
In the face of this rapid market move, one can expect single solution suppliers will extol features of their solution over the market’s choice. Users faced with the grim prospect of having to adapt to market changes will praise the past in hopes others will depart from the crowd. I am at a loss to think of a time when actions like this have worked to change the market. Maybe someone knows of examples and can share them.
In fact, I was a user who praised the technical benefits of one format over another. I made further investments in it. I even moved to a new job in a new area to find the community I moved to seemed to favor my selected format equally with what was to be the market winner. In time, in very short time, even my new community gave way to the market and the crowd. Can you guess what that format was?
I will share the details this with you next week when I discuss how one might actually bring value to legacy while allowing the market to continue its move forward. In the meantime, if you are close to the San Jose, CA or Reading, UK events, I suggest you register to attend.
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This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- Even More UVM Debug in Questa 10.2
- IEEE Approves New Low Power Standard
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- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
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- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
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- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
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- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
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