The IEEE’s Most Popular EDA Standards

How do your favorites rank?

Have you ever wondered how popular the different IEEE standards for electronic design automation are? Have you ever wondered which ones show the least interest? When buying books online, popular book buying websites sites will rank customer purchases. Many newspapers manage lists that you can consult to determine what is the most popular; what has the highest demand. But if you have purchased any IEEE standards, you will know this information is not available from the IEEE Store or the IEEE XPlore platform.

On May 4th, the IEEE Standards Association announced its collaboration with Techstreet to create the New IEEE Standards Store.  Until now, anyone who wanted to order a single standard had to use a more complex system that even made it hard to share a permanent link to one’s favorite standard with another.  Just look at the Accellera homepage for an example of where to get the SystemVerilog (IEEE Std. 1800™) standard.  At the writing of this blog, it simply points to www.ieee.org.  [I will share the fact the IEEE’s new site now has fixed links that can now be used to help others find the most current SystemVerilog standard with the Accellera.]

But back to what is the most popular IEEE EDA standards… Any guesses?

Before I delve into those details, let me say the ranking is just by ordinal.  The New IEEE Standards Store shares no information on the actual number of standards purchased.  So the difference between #1 and #10 could be just 10 copies.  It probably isn’t, but it could be.  But talking about #10, why is it even on the list?  The IP-XACT standard (IEEE Std. 1685™) is available for free under the IEEE Get Program.  Under this program you can download a PDF of the IEEE standard for free.  If you want a printed version, you can print your own copy from the free one you download.  Back in December 2010, Accellera reported that since the IEEE started to offer IP-XACT for free, there had been 1200 downloads.  It also looks like many people did not want the hassle to print and simply ordered the print version directly from the IEEE.  The other IEEE EDA standard offered free is SystemC©  And this is probably the reason it is in 32nd place.  It is very popular in terms of the number of free downloads.

And yes, if you search for the those two standards on the New IEEE Standards Store, you will find you can order print copies there and if you read the small print below, you will see there is a link to take you to the free online versions.

Harry Foster has issued several research reports on the popularity of one language or format the past several months.  In his last blog, he discussed which of the design and verification languages are ranked high and those, well, not so high.  And I guess I feel best to share the correlation between his findings and these more “anecdotal” results from the New IEEE Standards Store.  I have been party to many at the top standards  (Verilog/SystemVerilog) and party to the “least highest” (yes, I can’t say the least liked) VITAL 2000.  For vindication, I will note that VITAL-95 comes in at #18.  In whole, it appears to me that the New IEEE Standards Store ordinal rankings of EDA standards matches the scientific data from the research Harry has reported.

Below is the full ranking of IEEE EDA standards.  Where are your favorites?

1 IEEE 1364-2001 Verilog Hardware Description Language
2 IEEE 1800-2009 SystemVerilog–Unified Hardware Design, Specification, and Verification Language
3 IEEE 1076-2002 VHDL Language Reference Manual
4 IEEE 1076-1993 VHDL Language Reference Manual
5 IEEE 1499-1998 Interface for Hardware Description Models of Electronic Components
6 IEEE 1364-1995 Hardware Description Language Based on the Verilog® Hardware Description Language
7 IEEE 1800-2005 SystemVerilog: Unified Hardware Design, Specification and Verification Language
8 IEEE 1076.2-1996 VHDL Mathematical Packages
9 IEEE 1076.1-1999 VHDL Analog and Mixed-Signal Extensions
10 IEEE 1685-2009 IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows
11 IEEE 1850-2005 Property Specification Language (PSL)
12 IEEE 1076c-2007 VHDL Language Reference Manual – Procedural Language Application Interface
13 IEEE 1164-1993 Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)
14 IEEE 1850-2010 Property Specification Language (PSL)
15 IEEE 1076.6-2004 VHDL Register Transfer Level (RTL) Synthesis
16 IEEE 1801-2009 Design and Verification of Low Power Integrated Circuits
17 IEEE 1481-2009 Integrated Circuit (IC) Open Library Architecture (OLA)
18 IEEE 1076.4-1995 VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification
19 IEEE/IEC 61691-5-2004 IEC 61691-5 Ed.1 (IEEE Std 1076.4(TM)-2000): Behavioural Languages – Part 5: Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification
20 IEEE 1647-2008 Functional Verification Language e
21 IEEE 1076.1.1-2011 VHDL Analog and Mixed-Signal Extensions — Packages for Multiple Energy Domain Support
22 IEEE/IEC 61691-7-2009 Behavioural languages – Part 7: SystemC Language Reference Manual
23 IEEE 1076-1987 VHDL Language Reference Manual
24 IEEE 1076.1.1-2004 VHDL Analog and Mixed-Signal Extensions—Packages for Multiple Energy Domain Support
25 IEEE 1076.3-1997 VHDL Synthesis Packages
26 IEEE/IEC 61523-3-2004 IEC 61523-3 Ed.1 (IEEE Std 1497(TM)-2001): Delay and Power Calculation Standards – Part 3: Standard Delay Format (SDF) for the Electronic Design Process
27 IEEE 1076/INT-1991 Interpretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual
28 IEEE/IEC 62531-2007 IEC 62531 Ed. 1 (2007-11) (IEEE Std 1850-2005): Standard for Property Specification Language (PSL)
29 IEEE 1076.6-1999 VHDL Register Transfer Level Synthesis
30 IEEE 1647-2006 Functional Verification Language “e”
31 IEEE/IEC 61691-6-2009 Behavioural languages – Part 6: VHDL Analog and Mixed-Signal Extensions
32 IEEE 1666-2005 SystemC® Language Reference Manual
33 IEEE/IEC 61691-1-1-2004 IEC 61691-1-1 Ed.1 (IEEE Std 1076(TM)-2002): Behavioural Languages – Part 1-1: VHDL Language Reference Manual
34 IEEE 1364-2005 Verilog Hardware Description Language
35 IEEE/IEC 61691-4-2004 IEC 61691-4 Ed.1 (IEEE Std 1364(TM)-2001): Behavioural Languages – Part 4: Verilog® Hardware Description Language
36 IEEE 1076.4-2000 VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification

Learn more about the New IEEE Standards Store

There is much more to the New IEEE Standards Store than just the rankings of the standards we use in electronic design automation.  As I mentioned, it is easier to share fixed links to IEEE standards.  And if you want to track IEEE standards development – and don’t want to have to register your email address with the actual committee developing it just to know when they are done and a standard is ready – you can register to be notified when a new standard is ready.  The New IEEE Standards Store will notify you when a new one is ready.

Check out the short, one minute, video below to learn more about the New IEEE Standards Store.

Post Author

Posted June 17th, 2011, by

Post Tags

, , , , , , , , , , ,

Post Comments

No Comments

About Verification Horizons BLOG

This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool. Verification Horizons BLOG

@dennisbrophy Tweets

  • Loading tweets...

@dave_59 Tweets

  • Loading tweets...

@jhupcey Tweets

  • Loading tweets...

Comments

Add Your Comment

Archives

September 2014
  • Portable and Productive Test Creation with Graph-Based Stimulus
  • Supporting A Season of Learning
  • August 2014
  • DVCon Goes Global!
  • Better Late Than Never: Magical Verification Horizons DAC Edition
  • July 2014
  • Accellera Approves UVM 1.2
  • May 2014
  • Getting More Value from your Stimulus Constraints
  • The FPGA Verification Window Is Open
  • April 2014
  • UVM DVCon 2014 Tutorial Video Online
  • Mentor Enterprise Verification Platform Debuts
  • March 2014
  • New Verification Academy ABV Course
  • DVCon 2014 Issue of Verification Horizons Now Available
  • February 2014
  • DVCon–The FREE Side
  • More DVCon–More Mentor Tutorials!
  • UVM 1.2: Open Public Review
  • DVCon 2014: Standards on Display
  • Just because FPGAs are programmable doesn’t mean verification is dead
  • January 2014
  • Managing Verification Coverage Information
  • November 2013
  • Epilogue: The 2012 Wilson Research Group Functional Verification Study
  • New Verification Horizons Issue Available
  • October 2013
  • Happy Halloween from ARM TechCon
  • IEEE Standards Association Symposium on EDA Interoperability
  • STMicroelectronics: Simulation + Emulation = Verification Success
  • September 2013
  • A Decade of SystemVerilog: Unifying Design and Verification?
  • Part 12: The 2012 Wilson Research Group Functional Verification Study
  • August 2013
  • Part 11: The 2012 Wilson Research Group Functional Verification Study
  • Part 10: The 2012 Wilson Research Group Functional Verification Study
  • Part 9: The 2012 Wilson Research Group Functional Verification Study
  • Part 8: The 2012 Wilson Research Group Functional Verification Study
  • July 2013
  • Part 7: The 2012 Wilson Research Group Functional Verification Study
  • Walking in the Desert or Drinking from a Fire Hose?
  • Part 6: The 2012 Wilson Research Group Functional Verification Study
  • A Short Class on SystemVerilog Classes
  • Part 5: The 2012 Wilson Research Group Functional Verification Study
  • Part 4: The 2012 Wilson Research Group Functional Verification Study
  • June 2013
  • Part 3: The 2012 Wilson Research Group Functional Verification Study
  • Part 2: The 2012 Wilson Research Group Functional Verification Study
  • May 2013
  • Texas-Sized DAC Edition of Verification Horizons Now Up on Verification Academy
  • IEEE 1801™-2013 UPF Standard Is Published
  • Part 1: The 2012 Wilson Research Group Functional Verification Study
  • What’s the deal with those wire’s and reg’s in Verilog
  • April 2013
  • Getting AMP’ed Up on the IEEE Low-Power Standard
  • Prologue: The 2012 Wilson Research Group Functional Verification Study
  • March 2013
  • Even More UVM Debug in Questa 10.2
  • IEEE Approves New Low Power Standard
  • February 2013
  • Verification Horizons DVCon Issue Now Available
  • Get your IEEE 1800-2012 SystemVerilog LRM at no charge
  • IEEE 1800™-2012 SystemVerilog Standard Is Published
  • See You at DVCon 2013!
  • Get Ready for SystemVerilog 2012
  • January 2013
  • VHDL Update Comes to Verification Academy!
  • December 2012
  • IEEE Approves Revised SystemVerilog Standard
  • November 2012
  • Coverage Cookbook Debuts
  • October 2012
  • IoT: Internet of Things
  • Check out the October, 2012 Verification Horizons
  • Improving simulation results with formal-based technology
  • Introducing “Verification Academy 2.0”
  • September 2012
  • OVM Gets Connected
  • August 2012
  • OpenStand & EDA Standardization
  • July 2012
  • Synthesizing Hardware Assertions and Post-Silicon Debug
  • Virtual Emulation for Debugging
  • Verification Academy: Up Close & Personal
  • SystemC Standardization Cycle Completes
  • Verification Standards Take Another Step Forward
  • New UVM Recipe of the Month: Scoreboarding in UVM
  • June 2012
  • Intelligent Testbench Automation – Catching on Fast
  • May 2012
  • Two Articles You Need to Check Out
  • Off to DAC!
  • Dave Rich Featured on EEWeb
  • March 2012
  • How Did I Get Here?
  • February 2012
  • Expanding the Verification Academy!
  • Get on the Fast Track to Advanced Verification with UVM Express
  • Introducing UVM Connect
  • Tornado Alert!!!
  • UVM: Some Thoughts Before DVCon
  • UVM™ at DVCon 2012
  • January 2012
  • SystemC 2011 Standard Published
  • Verification solutions that help reduce bug cost
  • December 2011
  • Instant Replay for Debugging SoC Level Simulations
  • 2011 IEEE Design Automation Standards Awards
  • November 2011
  • Getting started with the UVM – Using the Register Modeling package
  • TLM Becomes an IEEE Standard
  • October 2011
  • Worlds Standards Day 2011
  • VHS or Betamax?
  • Verification Issues Take Center Stage
  • September 2011
  • New UVM Recipe-of-the-Month: Sequence Layering
  • July 2011
  • Combining Intelligent Testbench Automation with Constrained Random Testing
  • Going from “Standards Development” to “Standards Practice”
  • Verification Academy Now Includes OVMWorld Content
  • June 2011
  • Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
  • Part 9: The 2010 Wilson Research Group Functional Verification Study
  • Verification Horizons DAC Issue Now Available Online
  • Accellera & OSCI Unite
  • The IEEE’s Most Popular EDA Standards
  • UVM Register Kit Available for OVM 2.1.2
  • May 2011
  • Part 8: The 2010 Wilson Research Group Functional Verification Study
  • Getting Your Standards Update @ DAC 2011
  • April 2011
  • User-2-User’s Functional Verification Track
  • Part 7: The 2010 Wilson Research Group Functional Verification Study
  • Part 6: The 2010 Wilson Research Group Functional Verification Study
  • SystemC Day 2011 Videos Available Now
  • Part 5: The 2010 Wilson Research Group Functional Verification Study
  • Part 4: The 2010 Wilson Research Group Functional Verification Study
  • Part 3: The 2010 Wilson Research Group Functional Verification Study
  • March 2011
  • Part 2: The 2010 Wilson Research Group Functional Verification Study
  • Part 1: The 2010 Wilson Research Group Functional Verification Study
  • Prologue: The 2010 Wilson Research Group Functional Verification Study
  • Language Transitions: The Dawning of Age of Aquarius
  • Using the UVM libraries with Questa
  • February 2011
  • DVCon: The Present and the Future
  • Free at Last! UVM1.0 is Here!
  • Parameterized Classes, Static Members and the Factory Macros
  • IEEE Standards in India
  • January 2011
  • Accellera Approves New Co-Emulation Standard
  • December 2010
  • New Verification Horizons: Methodologies Don’t Have to be Scary
  • The Survey Says: Verification Planning
  • October 2010
  • Towards UVM Register Package Interoperability
  • IEC’s 47th General Assembly Meeting Opens
  • UVM: Giving Users What They Want
  • September 2010
  • UVM Takes Shape in the Accellera VIP-TSC
  • Accellera VIP-TSC Selects RAL for UVM 1.0 Register Package
  • OVM Cookbook Available from OVMWorld.org
  • UVM Register Package Candidate News
  • August 2010
  • Redefining Verification Performance (Part 2)
  • July 2010
  • Making formal property checking easy to use
  • Redefining Verification Performance (Part 1)
  • SystemVerilog Coding Guidelines: Package import versus `include
  • June 2010
  • The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
  • New Verification Academy Advanced OVM (&UVM) Module
  • OVM/UVM @DAC: The Dog That Didn’t Bark
  • DAC: Day 1; An Ode to an Old Friend
  • UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
  • Static Verification
  • OVM/UVM at DAC 2010
  • DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
  • Accellera’s DAC Breakfast & Panel Discussion
  • May 2010
  • Easier UVM Testbench Construction – UVM Sequence Layering
  • North American SystemC User Group (NASCUG) Meeting at DAC
  • An Extension to UVM: The UVM Container
  • UVM Register Package 2.0 Available for Download
  • Accellera’s OVM: Omnimodus Verification Methodology
  • High-Level Design Validation and Test (HLDVT) 2010
  • New OVM Sequence Layering Package – For Easier Tests
  • OVM 2.0 Register Package Released
  • OVM Extensions for Testbench Reuse
  • April 2010
  • SystemC Day Videos from DVCon Available Now
  • On Committees and Motivations
  • The Final Signatures (the meeting during the meeting)
  • UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
  • UVM-EA (Early Adopter) Starter Kit Available for Download
  • Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
  • March 2010
  • The Art of Deprecation
  • OVM 2.1.1 Now Ready for Download
  • February 2010 Verification Horizons Newsletter Now Available
  • IEEE Standards Meetings in India
  • February 2010
  • I Do It …
  • SystemVerilog: A time for change? Maybe not.
  • Partners Offer Support for OVM 1.0 Register Package
  • SystemC Day at DVCon
  • OVM/VMM Interoperability Kit: It’s Ready!
  • January 2010
  • Three Perfect 10’s
  • OVM 1.0 Register Package Released
  • Accellera Adopts OVM
  • SystemC (IEEE Std. 1666™) Comes to YouTube
  • Debugging requires a multifaceted solution
  • December 2009
  • A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
  • Truth in Labeling: VMM2.0
  • IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
  • December Verification Horizons Issue Out
  • Evolution is a tinkerer
  • It Is Better to Give than It Is to Receive
  • Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
  • DVCon is Just Around the Corner
  • The “Standards Corner” Becomes a Blog
  • I Am Honored to Honor
  • IEEE Standards Association Awards Ceremony
  • ABV and being from Missouri…
  • Time hogs, blogs, and evolving underdogs…
  • Full House – and this is no gamble!
  • Welcome to the Verification Horizons Blog!
  • September 2009
  • SystemVerilog: The finer details of $unit versus $root.
  • SystemVerilog Coding Guidelines
  • July 2009
  • The Language versus The Methodology
  • May 2009
  • Are Program Blocks Necessary?