Archive for January, 2011
Accellera Approves New Co-Emulation Standard
Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity
The Accellera Interface Technical Subcommittee (ITC) completed version 2.1 of the standard used to interface software and hardware-based verification technology. With SCE-MI, models can be developed for simulation to run in an emulation environment and visa versa.
The major addition to SCE-MI 2.1 is support for a subset of the IEEE Std 1800™ (SystemVerilog) Direct Programming Interface (DPI) that permits a streaming, variable length messaging system to be built on top of it to reduce the number of synchronizations that would otherwise be required by alternate methods.
The standard is available here free of charge from Accellera.
What does this mean to the verification professional?
Dr. van der Schoot has published four sessions on Acceleration of SystemVerilog Testbenches with Co-Emulation at the Verification Academy that give an excellent overview of the benefits of this technology. Dr. van der Schoot shows how the prevalent verification methodologies (OVM and UVM) can see dramatic improvements when this technology is applied.
| Verification Academy Session | |
| Introduction to Hardware Assisted Testbench Acceleration | |
| Testbench Acceleration Depicted | |
| Modeling for Acceleration | |
| Testbench Acceleration Flow |
How is Co-Emulation Used in Practice?
EDSFair 2011
The technology is also deployed in a working verification flow by Mentor Graphics. At EDSFair 2011 in Japan this week, users could see Co-Emulation in action.
This technology has allowed verification runs using the prevalent methodologies, OVM and UVM, to operate easily up to 400x faster when emulation technology is used to accelerate verification as previously announced.
While EDSFair is over, verification professionals will have another opportunity to see this technology in action at the DVCon 2011 exhibition. Dr. van der Schoot also has a paper at DVCon, Off To The Races With Your Accelerated SystemVerilog Testbench, that he will present to explore details on how this standards technology is being applied in real life.
Tags: accellera, dvcon, EDSFair, OVM, SCE-MI, Standards, SystemVerilog, UVM
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This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
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