Archive for September, 2010
UVM is Taking Shape
While you have all been happily verifying your complex SoCs the Accellera VIP Technical Subcommittee (VIP-TSC), otherwise known as the Committee, has been working hard to define UVM. Their work is beginning to pay off. The body of code that will eventually be known as UVM-1.0 is starting to take shape. Today I will give you a short tour through the features of UVM-1.0.
Mentor and Synopsys collaborated on a register package for UVM. Building on the base data structures from Synopsys VMM RAL, Mentor provided the expertise to “UVM-ize” the package. Along the way the code was optimized and cleaned up to create a high-performance, very flexible register modeling package. This package was chosen by the committee to be included with UVM. For more information see Dennis Brophy’s blog post “Mentor/Synopsys Collaboration Bears Fruit.”
In UVM-EA and its predecessor OVM, the phase ordering was represented by a linear list. This proved to be insufficient for complex testbenches, including modeling such things as resets and interrupts. In UVM-1.0 phase ordering will be represented by a directed acyclic graph (DAG). While the term sounds fancy, the idea is pretty simple. The graph-based ordering allows some phases to operate in parallel with other. In the new system it will be easier to add new phases and to integrate IP together that have been built with different phasing schemes.
The set of built-in phases will be:
The starred phases are new ones; the ones without stars are the same phases found in OVM and UVM-EA. The phases are in three groups: initialization, execution, and termination. The initialization phases are the same as in OVM and have the same semantics. The new execution phases will execute in parallel with run. In the termination set final is provided as the very last phase. This allows the possibility of test concatenation where multiple tests are run, each through extract, check, and report. Only when the last test completes is final executed.
TLM-2 has been standardized and available in the SystemC community since 2009. Now, the same facilities will be available for the SystemVerilog community as well. In creating a TLM-2 facility for SystemVerilog, the goal as defined by the Committee is to translate the SystemC TLM-2 LRM into SystemVerilog as faithfully as possible. Because of the differences in SystemC and SystemVerilog there are necessarily some differences in the SystemVerilog and SystemC versions. It’s like translating a poem from English to French. There are a lot of different translations, each of which would be considered “accurate,” but which one best expresses the sense of the original? This can be tricky. The Committee is working hard to ensure the best possible translation.
(As an aside, there is a wonderful book on this topic called “Le Ton beau de Marot: In Praise of the Music of Language” by Douglas Hofstadter [Basic Books, 1997]. The book uses a simple poem written by Clement Marot to discuss the issues and subtleties of translation. I highly recommend it for anyone interested in languages — computer or natural.)
The configuration system in UVM-EA has many limitations, including the fact that only components can be configured. It’s possible, but not easy to get configuration information into other kinds of objects such as sequences. In UVM-1.0 the set_config/get_config configuration system will be replaced with a more generalized facility called “resources.” It provides a means for storing objects of any data type, not just strings, ints, and things derived from uvm_object, including virtual interfaces. A compatibility layer is also provided that has an implementation of set_config/get_config in terms of resources.
Command Line Options
Everyone who has written any significant testbench code has also written some means to capture command line options and to process them. Now UVM-1.0 will contain a facility that does that for you. It will grab all the command line options and store them in a data structure. You can locate specific ones by name, or you can locate groups using regular expression. You can obtain argument values for those options that take a value. Additionally some pre-defined command line options are provided for consistency, such as +uvm_set_verbosity, +uvm_timeout, or +uvm_max_count, as well as others.
UVM-1.0 will retain backward compatible with OVM-2.1.1 (save the Os changed to Us) while bringing a wealth of new features and capabilities to testbench writers. I am personally pleased with the technical direction that UVM is taking and I hope you will be too.
Two weeks back I shared information in a blog on collaboration between Mentor Graphics and Synopsys to reduce the number of candidate register packages being considered by the Accellera Verification IP (VIP) Technical Subcommittee (TSC). Mentor withdrew its candidate when all our requirements were able to be addressed in an update to the Synopsys RAL candidate.
As it happened, of the three major features planned for UVM 1.0, only the register package addition had multiple candidates. For the phasing and TLM2 integration, there is only one code candidate. There was no need to select from multiple candidates for them.
After we announced our collaboration with Synopsys, the next steps were to review the candidates via public review meetings and then hold an in-depth review at an Accellera VIP-TSC face-to-face meeting. The multi-day face-to-face meeting concluded on September 16th and a vote to select one of the two candidate register packages opened. That vote concluded on September 22nd with the selection of RAL, the Mentor/Synopsys collaborated candidate.
While neither candidate addressed 100% of the Accellera VIP-TSC requirements, the work now is to move in a direction where it can get closer to 100% and final approval of the UVM 1.0 standard can move this work from standards development to standards deployment.
I will update you on further UVM 1.0 developments as the code progresses to a final stage for approval. As we near that point, we will want to have early users of UVM 1.0 test it with the Questa verification platform for completeness and readiness.
As I have done in my prior blogs, I invite those who wish to participate in this work or monitor it more closely to join the committee email reflector. You can find official status on Accellera UVM development and how to join and monitor it at the committee website located at http://www.accellera.org/activities/vip.
Several months ago, the OVM Cookbook and the Examples Kit were made available for online use at the Verification Academy. This proved to be a great help to accelerate the skill level of new OVM users. Given the number of new projects that have deployed OVM and the number of new engineers that now need to use OVM, there is increased demand for practical and useful information found in the Cookbook.
One can see the OVM World community continues to grow. The same needs from that community to invest in bettering their OVM knowledge and skills is just as needed as those who are members of the Verification Academy. For that reason, we are making the OVM Cookbook and the Examples Kit available for free download from OVMWorld.org.
The OVM Cookbook, authored by Mentor Graphics’ Mark Glasser, is written, as he says, for engineers that want to “jump right into a new technology.” While there is a general disdain for reading long reference guides or operation manuals, engineers are comfortable to read how-to books that have concrete examples that can be applied to their problems. Later, when needed, engineers might return to theory of operation manuals to move to an advanced understanding of something.
The OVM Cookbook was designed as that introductory guide that makes it easier to plunge into OVM right away.
With the large rise in OVM users, we make the Cookbook and examples available fee-free and without the need to register on OVM World. You can keep a softcopy on your computer for easy access and reference, your PDF ready e-reader, or you can print it if you prefer to annotate a hardcopy as you use it. However you want to use the Cookbook, it is your free practical guide to OVM.
Mentor Announces Collaboration with Synopsys on Joint Register Package Candidate
Mentor has recently teamed with Synopsys to collaborate on the Synopsys RAL candidate to provide extensions that meet our register package requirements. Because of this, it allowed us to withdraw our candidate from consideration by the Accellera VIP-TSC recently.
Further, as part of the Accellera VIP-TSC UVM development process, a request was made for companies that would have candidate solutions to hold public review meetings to share high-level information about their proposals. There is such a review meeting for this candidate on Wednesday, 8 September 2010 at 8am PDT.
You are invited to join the presentation on WebEx and listen live on the teleconference by Mentor’s Tom Fitzpatrick and Synopsys’ Janick Bergeron as they cover the details of Synopsys RAL for UVM. For more information on the event, visit the Main UVM Forum on OVMWorld.org by clicking here.
There are more elements to UVM 1.0 that are not part of a public review process and I invite you to visit the committee website where you can find official status on Accellera UVM development or to participate in the committee. The committee website is located at www.accellera.org/activities/vip.
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