Archive for June, 2010

28 June, 2010

Now that the Accellera VIP-TSC has released UVM-EA, effectively narrowing the choice of verification methodologies to UVM or OVM, many people are asking which way to go — OVM or UVM?  The answer depends a lot on where you are in code development and what your risk tolerance is.  The good news is that neither is a bad choice. One thing is certain: OVM is not dead yet.  It will be around for a long time.  Across the industry a lot of IP has been built and testbenches have been put into production all with OVM.  These must remain operational and supported for a similarly long time. Right now, OVM is the lowest risk choice overall.  There is tons of tool support and lots of IP available along with training and other material from a variety of vendors.  We know OVM is stable and production-worthy just by how widespread its use is.

In its current state UVM is for the more adventurous.  By and large it is OVM with the Os changed to Us.  That’s why we can say it is stable and not necessarily a bad choice.  The risk comes not from whether or not UVM itself works, but in how much support of various kinds is currently available.  Vendors are now updating their tool sets to support UVM, but that work is far from complete.  I imagine as the Accellera committee gets close to releasing UVM-1.0 we’ll see announcements from vendors around their tool support for UVM. Training, examples, and other material is under development as well and will probably be available from their respective  sources shortly after UVM-1.0 is out.

Another aspect to the risk involves 3rd party IP.  IP vendors are also working on converting their IP to be UVM compatible.  If you use 3rd party IP you will need to know when your vendor will make available the components you need converted to run under UVM. The biggest risk comes from the potential of UVM not being entirely backward compatible with OVM (factoring out the simple syntactic name changes).  The VIP-TSC has stated that backward compatibility is a goal, but not a hard requirement.  For example, the VIP-TSC is now looking deeply at phasing.  Proposals are being considered that enable phases to run in parallel and to add additional default phases.  If done properly these changes would add significant capability to UVM and be entirely backward compatible.  If not, UVM could require architectural changes in drivers and monitors to accommodate new phases.  Exactly which way this will go is not clear right now. Mentor, of course, is making a case to retain backward compatibility.

The availability of UVM-EA in advance of the standard affords a prime opportunity to kick the tires and to start some early planning.  Go ahead and download it and start evaluating it.  Try it out on small- to medium-sized pieces of code.  The UVM-EA includes a script to change the Os to Us.  It’s the same script that was used to import OVM as the seed for UVM development.  You can use UVM-EA to figure out what you need to do to convert your environment from OVM to UVM.

Eventually there will be a tipping point and UVM will become the obvious choice for a testbench methodology.  That day is still in the distance.  In the mean time OVM is around and provides all the features necessary to build sophisticated testbenches.

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25 June, 2010

I’ve always loved the Chinese proverb, “Give a man a fish and you feed him for a day. Teach a man to fish and you feed him for a lifetime.” Yet, why merely settle for fish when you can have sushi! My point is, to remain strategically relevant in today’s competitive landscape, it is necessary to constantly reinvent ourselves and evolve our technical skills. To that end, we have created the Verification Academy to help you evolve your advanced functional verification skills.

Since we launched the Verification Academy, we have had numerous requests for training on the Open Verification Methodology (OVM). Hence, in February we launched a new module titled Basic OVM that has been received with overwhelming enthusiasm.  It’s currently our top viewed module. The Basic OVM module consists of 2.5 hours of content, and is divided into eight 20-minute sessions. The module is primarily aimed at existing VHDL and Verilog engineers who recognize they have a functional verification problem, but have little or know experience with constrained-random verification or object-oriented programming. Our goal for releasing the Basic OVM module is to raise your skill level to the point where you have sufficient confidence in your own technical understanding. In turn, you will have the confidence required to start the process of adopting advanced functional verification techniques.

This month, we are excited to announce the next step in evolving your Open Verification Methodology skills. Our new module is titled Advanced OVM (&UVM) and provides a higher level of OVM understanding beyond what is presented in our previously released Basic OVM module. What’s particularly exciting about this release is that we are addressing the numerous requests from you concerning advanced functional verification and creating contemporary testbenchesusing the OVM. The Advanced OVM module is presented by our own subject matter expert, Tom Fitzpatrick, who has been a driving force behind the OVM development and standardization. Tom is one of my favorite technical presenters. He is both informative and entertaining, so I’m sure you will really enjoy our new Advanced OVM module.

Now, as shown in Table 1, the Verification Academy covers a wide variety of topics, which enables you to start evolving your advanced functional verification skills.

Table 1. Verification Academy Modules

Module Name

Number of
Sessions

Description

Evolving Capabilities

1

This module provides a framework for all the modules within the Verification Academy, while introducing a tool for assessing and improving an organization’s advanced functional verification capability

Assertion-Based Verification

11

This module provides a comprehensive introduction to ABV techniques, include an introduction to SystemVerilog Assertions

CDC Verification

7

This module provides an understanding of the clock-domain crossing problem, in terms of metastability and reconvergence, and then introduces verification solutions

FPGA Verification

8

This module, although targeted at FPGA engineers, provides an excellent introduction to anyone interested in learning various functional verification techniques

Basic OVM

8

This module provides a step-by-step introduction to the basics of OVM

Advanced OVM

5

This module provides the next level of understanding beyond the skills introduced in the Basic OVM module

Another exciting announcement is that we have added a language capture option to most (and eventually all) Verification Academy modules.  The language options include: Chinese Simplified and Traditional, Japanese and Russian.

In the next few weeks we have another exciting announcement related to the Verification Academy.  Stay tuned!

I would like to encourage you to check out all our new and existing content at the Verification Academy by visiting www.verificationacademy.com.


18 June, 2010

In the classic Sherlock Holmes story, “Silver Blaze,” Holmes realizes that the family dog didn’t bark when the suspect entered the house to commit the crime. This leads Holmes to deduce that the suspect was familiar to the dog and, from there, he of course unravels the rest of the mystery (which I won’t spoil for you). Since then, “the dog that didn’t bark” has been used to denote something seemingly innocuous that reveals a lot more under the surface.

I was reminded of “the dog that didn’t bark” this week at DAC. I did a number of presentations on OVM and UVM in the OVMWorld booth and participated in a panel discussion on UVM at the Accellera breakfast on Tuesday. It was great to see the amount of interest shown by the audiences at all of these events. As you may know, Accellera chose OVM as the basis for UVM, and a lot of the discussion was on where we go from here. One question that kept coming up was whether Mentor and Cadence would continue development of OVM, now that UVM is coming closer to reality. The implication clearly was that it would somehow be a bad thing if we did, although I’m not sure exactly why. Our answer was that Mentor will continue supporting OVM as long as our customers are using it (which could be for some time given how long it sometimes takes for standards to come to fruition), but that we would put our energy into developing new functionality in UVM. It didn’t occur to me until later that there was a dog that didn’t bark at DAC.

The question that I never heard asked nor answered, especially at the Accellera breakfast, is this. If everyone is so concerned that continuing OVM development outside of UVM is somehow a bad thing, will Synopsys show a similar commitment to the success of UVM by suspending any further VMM development? After all, if further OVM development will somehow deter adoption of UVM, further VMM development would as well. So I think Synopsys should make the same commitment to the success of UVM that Mentor and Cadence have.

15 June, 2010

Denali Finale

While I ponder the hundreds of partners I work with to support a vibrant ecosystem of ModelSim and Questa users (thank you to all of you, by the way!) tonight was a special night for a long standing partner: Denali.

Looking back into the archives, the first communication from Sanjay (Srivastava), Mark (Gogolewski) and David (Lin) pondering our possible collaborative efforts in the late nineties to the first of your party invitations to the Bourbon Street Bash held at Patout’s Bourbon Vieux Room give me pause.  Last in the archive is, of course, the invitation to the Monday Denali Party at the House of Blues. (And it is amazing what Jeannette Zelaya can do in two weeks!  My hats off to you!)

Karen Bartleson as Paula at Denali Party In the frivolity before the musical festivities, the EDA Idol judges gathered for the fourth (and final) Denali EDA Idol competition.  I must say, there are a lot of very talented musicians from within EDA and our customers.  This year’s crop of contestants were very good.  But fellow judges Simon Davidmann and Karen Bartleson reminisced about the past contests and an end of an era.  Karen  Bartleson even out did her wardrobe of prior years and was stunning as our EDA Idol “Paula.”  I sure hope she can change her hair color back overnight.  The picture to the left is actually Karen.  Can you recognize her?

ModelSim Fender One can only hope the “music” continues on.  The Mentor ModelSim team has made a small dent in EDA music with the creation of a“ModelSim” Fender Stratocaster guitar this year.  (No, I don’t play, but maybe one day we can share it with those who can.)

Mentor Fender Statocaster

If the contestants tonight prove anything, hope rises eternal for more music, fun and camaraderie in the future.  We can hope.

On an endnote, the start of tonight’s party was a moving tribute from Mark Gogolewski to fellow Denali employees, customers, partners and his best treasure, his “better half” as he said, his wife.  You touched a chord with many.

To all of Denali (present and past), thank you for the opportunity to collaborate with you for more than a decade of mutual customer success.  I wish all of you well, always.

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9 June, 2010

EDACafe Guest Blog DAC Attendees Invited to Accellera’s Breakfast sponsored by Mentor, Cadence & Synopsys

The full statement can be read at EDA Cafe, click here.

The Big-3 EDA companies point out in the statement the work within Accellera to create an interoperability guide and kit to ensure verification IP and testbenches written in either the Verification Methodology Manual (VMM) or the Open Verification Methodology (OVM) can work together.  This preserves the investments made to date by users of those two methodologies.

The joint statement also says the Accellera Universal Verification Methodology (UVM) is based on OVM 2.1.1 and firmly rooted in SystemVerilog.  While we know today UVM is OVM 2.1.1 with a few small changes or additions, it is made clear that Accellera has just begun.  What happens next is the topic of the Accellera breakfast meeting.  (Have you registered yet for it?)

The joint statement asked these questions:

  • If we fast forward by a year, what would UVM base class release X look like?
  • What features should it have to solve the problems faced a year from now? 3 years from now?
  • Are we looking at adding more of the same or make a quantum leap in our ability to deal with much larger and significantly more complex designs?
  • What specifically are we doing to improve our ability to find bugs in the design and then fix them?

What questions do you have?  If you want to share them here, please do.  If you cannot attend the breakfast in person, I’ll bring your questions along to ask and report back after DAC on what happened at the Accellera breakfast.

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7 June, 2010

After spending years verifying ASICs with dynamic simulation, I started working on static verification 10 years ago in a startup called 0-In Design Automation. I firmly believe that static verification can complement dynamic simulation. Static verification uses synthesis and formal technologies to find bugs in the design. It does not rely on simulation stimulus. You do not need to exercise the bugs, propagate the results, and check the outputs to detect them.

Static verification includes RTL lint, static checks, formal checks, automated and assertion-based formal property checking. To read more on static verification, you can take a look at my white paper: Getting Started With Static Verification. If you are interested in formal methods, you can take a look at Harry Foster’s white paper: Why Now for Formal Property Checking. Both can be found in the Knowledge Center of DAC.com.

In the future, we are going to talk about individual static verification technologies and its application in areas such as RTL verification, clock domain crossing verification, low power verification, timing constraint verification, etc. Your feedback and comments are most welcome.

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3 June, 2010

Visit Booth 1350 – The hub of OVM/UVM Activity at DAC

OVM_LogoThe OVM World booth at the Design Automation Conference (#1350) will feature user and partner presentations on OVM/UVM, a live discussion by prominent verification experts and a Tuesday cocktail reception from
4:30 p.m. to 6:00 p.m.

UVM_LogoThe Open Verification Methodology (OVM) is the industry’s open and  interoperable solution, guaranteed to run on multiple simulators, supporting multiple design languages, and is the basis for the Accellera UVM standard. The OVM enables scalability and reuse, fostering a vibrant verification ecosystem. OVMworld.org is the one-stop site for the OVM open-source library, documentation, and community contributions.

Featured half-hour presentations at the booth will include those listed below.  In addition to the presenting company and presentation title, full presentation abstracts can be found at http://www.ovmworld.org/tradeshows.php.

Monday (June 14th)

10 a.m.

Silicon Interfaces
OVM-based Verification Methodology VIP permits Silicon Interfaces to release Gigabit Ethernet MAC to industry with zero defect guarantee

11 a.m.

Accellera
VIP Technical Subcommittee Update

1 p.m.

Verilab
Simulation-Based FlexRay™ Conformance Testing – an OVM success story

2 p.m.

AMIQ
OVM Support in DVT

3 p.m.

Mentor Graphics & Cadence
OVM and UVM Update

4 p.m.

Nsys
SuperSpeed your USB 3.0 Verification with OVM based nSys Verification IP

5 p.m.

Duolog
OVM/UVM from a single spec

Tuesday (June 15th)

9 a.m.

Aldec
OVM/UVM for FPGAs: The End of Burn and Churn?

10 a.m.

Sunburst Design
Virtual Interface Techniques for OVM

1 p.m.

Xilinx
Beyond a common base class library: reduce work by reusing OVM agents on common interfaces

2 p.m.

Doulos
The Communication and Customization Mechanisms in OVM and UVM

3 p.m.

Mentor Graphics & Cadence
OVM and UVM Update

4 p.m.

Methodology Experts Discussion

5 p.m.

Cocktail Networking Event

Wednesday (June 16th)

9 a.m. Denali
Denali’s PureSpec: OVM-compatible VIP for bus and I/O protocols
10 a.m. Sibridge
Successful OVM deployment
11 a.m. Agnisys
Agile methods for OVM
2 p.m. TSMC
ESL to RTL Verification – Progressive Refinement and Reuse Paradigm.
TSMC Open Innovation Platform.
3 p.m. Mentor Graphics & Cadence
OVM and UVM Update
4 p.m. Agnisys
Automatic Generation of OVM Registers
5 p.m. Duolog
GNAT

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3 June, 2010

I’d like to encourage you to attend the technical panel titled Bridging Pre-Silicon Verification and Post-Silicon Validation at this year’s  DAC.  The panel will be held on Tuesday, June 15, 2010 between 2:00 PM—4:00 PM.

Chair:

Alan Hu – Univ. of British Columbia, Vancouver, BC, Canada

Organizers:

Rajesh Galivanche – Intel Corp., Santa Clara, CA

 

Amir Nahir – IBM Corp., Haifa, Israel

 

Avi Ziv – IBM Corp., Haifa, Israel

 

 

Speakers:

Miron Abramovici – Tiger’s Lair, Inc., Vienna, VA

 

Sean Baartmans – Intel Corp., Hillsboro, OR

 

Valeria Bertacco – Univ. of Michigan, Ann Arbor, MI

 

Albert Camilleri – Qualcomm, Inc., San Diego, CA

 

Harry Foster – Mentor Graphics Corp., Plano, TX

 

Shakti Kapoor – IBM Corp., Austin, TX

Why do I think this is an important topic?  At 65nm, we witnessed the post-silicon validation effort often consuming more than 50% of an SoC’s overall design effort, as measured in cost, and the problem grows as the industry continues to move to even smaller geometries. Unlike pre-silicon verification, which has historically (and conveniently) partitioned the verification effort into separate concerns (such as, electrical, functional, performance, and software), identifying failures in post-silicon requires skills spanning multiple validation disciplines. Furthermore, the process of post-silicon validation is hindered by both poor observability and poor controllability. To address today’s escalating validation effort requires establishing a stronger link between the pre-silicon verification and post-silicon validation processes. Certainly assertions are one technique that can bridge pre- and post-silicon by providing improved observability on critical functionality. However, the improvements obtained by silicon assertions are only as effective as the quality of their pre-silicon form. Realistically, only a small set of critical assertions could be shared between the pre- and post-silicon processes. What is needed is a means to instrument into the silicon observability in a reconfigurable fashion, thus allowing the post-silicon validation engineer to shift focus on specific areas of concern. Concerning test generation, pre-silicon test provides insufficient coverage to stress the post-silicon design. Hence, what is needed is a means to capture post-silicon test associated with a failure in an abstract form that can be demonstrated on a pre-silicon model. Finally, concerning triage and error isolation, both the pre-silicon verification and post-silicon validation processes could benefit from automatic techniques that identify a set of candidate causes behind the detected failure.

For more information about the upcoming panel, visit: http://www2.dac.com/panels.aspx?event=30&topic=11

dac

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2 June, 2010

accellera UVM: Charting the New Territory

At this year’s DAC, Accellera introduces UVM (Universal Verification Methodology) to the world at its Tuesday breakfast and panel discussion.  While Accellera may call this “Charting the New Territory,” it is not terra incognita to Mentor Graphics nor to tens of thousands of OVM users.  UVM is at is simplest, just OVM.  If you know OVM; you know UVM.

While OVM and UVM are much alike, what is uncharted territory is how users will respond to and adopt UVM.  Unique to UVM is public support by the Big-3 EDA companies.  Other than that, nothing is really new for an OVM user.

What will be new next year at DAC 2011?  The Accellera panel abstract invites you to the breakfast to listen to a panel of expert verification engineers and methodology developers debate what they would like to see in UVM by DAC 2011.  And it encourages attendees to be vocal as well to share their views about what they would like to see by DAC 2011.

Breakfast Details

Tuesday, June 15, 2010
7:30 am – 9:00 a.m.
Anaheim Convention Center Room 203B

Please register for this event here

Moderator: Gabe Moretti, Gabe on EDA

Panelists:
Sharon Rosenberg, Cadence
Hillel Miller, Freescale
Mohamed Elmalaki, Intel
Tom Fitzpatrick, Mentor Graphics
Janick Bergeron, Synopsys
Stacey Secatch, Xilinx

On a light note: In prior DACs, the Accellera breakfast always seemed to follow the Denali party.  As you can imagine, a 7:30 a.m. start (or end to the night before) was always a challenge.  While many might have looked forward to break with tradition this year, we were informed by Denali that a second party (actually the first party if taken in chronological order) was being added.  For those who will register for a Denali party ticket, the Accellera breakfast will be a full breakfast to soak up any sins of the night before offered with plenty of coffee to wake you up.

I’ll see you at the Accellera breakfast and at the Denali party!

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