Archive for May, 2010
In an earlier blog post, I discussed a sequence layering technique that Mentor verification technologists had created and presented on at DVCon 2010, based on OVM. This package has been updated and tested to work with UVM 1.0 EA and is ready for download.
As a reminder, the UVM Layering 1.0 Package, like the OVM one, provides the means to add layers of tests (sequences) without modifying the underlying testbench and without extending components or using the factory to override implementations. The package also provides the DVCon paper and presentation that describes it in more detail in case you did not attend DVCon.
Users have found layered sequences can make verification life easier as sequences and sequencers are natively parallel and have arbitration and other communication process hooks already built-in. The package is a companion to the UVM 2.0 Register Package that was also updated from OVM to UVM.
You Are Invited – Register Now!
(seating is limited)
Sunday, June 13
2:30pm – 6:00pm
Anaheim Hilton, California Ballroom A
On the Sunday before DAC, the North American SystemC User’s Group (NASCUG) will hold NASCUG XIII and they invites all DAC attendees to this special event featuring the latest advancements in sustainable and flexible solutions for ESL design.
As a global sponsor of OSCI events, Mentor encourages the SystemC community to meet at this event to learn more about SystemC advances and applications.
Technical presentations on architectural modeling, transaction-level modeling and analog/mixed-signal design using SystemC™ will be featured. You will be able to interact with colleagues and industry experts, and find out first-hand how system-level design with SystemC has become a nuts-and-bolts part of the designer’s toolbox.
|2:30pm – 3:00pm||Registration|
|3:00pm – 3:10pm||Welcome & Agenda|
|3:10pm – 3:30pm||OSCI and Technical Working Group Update
Eric Lish, OSCI Chairman
|3:30pm – 5:50pm||Technical Presentations:|
|5:50pm – 6:00pm||Meeting Close and Prize Drawing|
6:00pm – 7:30pm
Anaheim Hilton, Pacific Ballroom
The DAC Executive Committee and the EDA Consortium invite the NASCUG XIII participants to attend their annual DAC Kick-Off Reception at this year’s conference in Anaheim, California. The reception begins just as the user group meeting concludes. Both events are in the Anaheim Hilton and located close to each other. Register Now to attend the Sunday reception.
This package introduces a very simple class called uvm_container. In this package Mentor shows how to use this class to link a Design Under Test (DUT) and a testbench. The UVM Container can be downloaded here as a companion to the Accellera UVM 1.0 EA.
This extension also introduces the dual top methodology. This methodology isolates the connections between the DUT and interface in a protocol module as well as provide a convenient site to add protocol specific assertions. These protocol modules automatically register the virtual interface with the UVM configuration using the uvm_container so that they can be used later by the testbench.
A technical paper, UVM Configuration and Virtual Interfaces, accompanies the UVM Container extension in the docs directory. The paper explores some more complex issues related to the best use of the configuration in the context of large, scalable testbenches. The two examples provide small but sufficiently complicated examples of this methodology.
This package will be of interest to anyone who has struggled to find a consistent and scalable methodology to integrate a DUT and testbench using the UVM configuration mechanism. It has been built to work with UVM 1.0 EA.
As I mentioned in my earlier blog post to disclose Mentor’s support of UVM-EA on the Questa Verification Platform, we would bring forward other OVM elements and make them UVM ready. We have done this for the OVM register package.
Users noted that the HTML documentation for the OVM version was missing. This been corrected and complete online documentation is now at your fingertips. You can use the navigation bar at the left to expand categories and click on the topic of choice. The body of the documentation is also hyperlinked for convenient navigation to related topics and more detailed descriptions of the particular class method or variable.
For completeness, the updated OVM Register Package 2.0 that has corrected HTML documentation can be found here.
The Accellera VIP-TSC makes the Early Adopter release of the Universal Verification Methodology (UVM) available.
While Accellera does not use the Latin word Omnimodus in place of the English word Universal, what Accellera does make available is for all practical intents and purposes just OVM. In April 2010, we made available at www.ovmworld.org an early version of UVM EA. It has now been updated with Accellera’s version here.
Accellera VIP-TSC has toiled for about a year following the completion of the VIP Interoperability Recommended Practices, which allowed verification specialist to use their legacy VMM code in an OVM environment, to produce UVM 1.0 EA. EA stands for Early Adopter to signify a release intended for wider community testing before further additions and changes are made, which will then to be followed by formal Accellera standards approval and release of the official UVM 1.0 standard.
UVM EA Content
For OVM users, UVM 1.0 EA offers no substantive technical advances from OVM. In changing “O’s” to “U’s” and “tlm’s” to “uvm_tlm’s” it has the promise, however, of wider public EDA vendor support. It offers no compelling reason for current OVM users to move now. For those who wish to test their code’s readiness to adopt UVM, we have tested the EA release with the most current version of Questa. We also maintain our commitment to offer versions of the OVM Register Package and the OVM Sequence Layering solution for those who wish to experiment with native UVM. Stay tuned for more information on that in the future.
UVM 1.0 Standard Proposed Content
The Accellera VIP-TSC now embarks on the hard task to address development of the official UVM 1.0 standard. At its last technical committee meeting, it began to discuss how to start the process to identify requirements for the UVM 1.0 register package. That feature, along with others currently on the committee’s list of features include the following:
|Register Memory package|
|Non-interpreted field macros|
|TLM 2.0 Support|
|Pre-defined run-time phases|
|Auto-documentation of configuration options|
|Virtual interface connection|
I will share ongoing progress towards the official UVM 1.0 release as developments merit.
Getting Started with UVM EA
You can download UVM from OVM World contributions area where other OVM contributions are being readied for UVM. Your feedback is always welcome.
I’ve had the pleasure of participating in the IEEE International High-Level Design Validation and Test (HLDVT) workshop off and on for the past ten years. In fact, of all the workshops and conferences I attend each year, I would probably rank this workshop up there as as one of my favorites. Each year, I look forward to re-connecting with many wonderful thought leaders from both industry and academia who regularly participate.
At this year’s HLDVT, I am honored to have the opportunity to participate on a panel titled “Clock Domain Verification Challenges.” I’d be interested in hearing your views on the subject, particularly emerging challenges around network-on-chip architectures.
In addition to the panel, this year’s HLDVT provides a rich program with five regular sessions, five special sessions, one tutorial, one keynote speech. There are several areas of intense focus. First, there is a session on firmware validation and one on HW-dependent software, to highlight the importance of embedded software. A session and panel are devoted to multi-clock systems and clock domain crossing verification, deployed in a variety of scenarios. One session is devoted to transaction-level modeling and another one deals with high-level arithmetic circuit descriptions to obtain more from circuits. Industry leaders in Electronic System Level (ESL) design will share their perspectives on verification challenges at ESL, and a variety of papers will deal with formal verification advances, constraint solving, coverage, and verification accelerators and emulators.
This year’s HLDVT workshop, which is scheduled for June 11-12, is co-located with 47th Design Automation Conference, June 13-18, 2010 at the Anaheim Convention Center, Anaheim, CA. For more information, visit http://www.hldvt.com/10/.
A new OVM Layering Package that provides a means to add layers of tests (sequences) without modifying the underlying testbench and without extending components or using the factory to override implementation is available for download.
The DVCon 2010 paper on this topic, You Are In a Maze of Twisty Little Sequences, All Alike – or Layering Sequences for Stimulus Abstraction, is also part of the download kit. The paper demonstrates building layered stimulus using OVM sequences and sequencers. Virtual sequences and virtual sequencers are highlighted by building a small collection of examples that can be used in layered stimulus verification environments. The main contribution of this paper is a new layering component that performs the standard layering task while minimizing user programming without requiring exotic connectivity, extended components or the use of the factory.
Using layered sequences can make your verification life easier, since sequences and sequencers are natively parallel and have arbitration and other communication process hooks already built-in. To learn more, download the kit. You will also find a presentation in the kit and how to use it with the OVM 2.0 Register Package mentioned in my last blog.
In January 2010 we released the OVM 1.0 Register Package. It has now been updated to enhance capabilities and address issues raised by users. The updated contribution can be downloaded from OVM World.
The OVM 2.0 Register Package builds on 1.0 with new built-in register tests, easier cloning and copying of registers and register maps. The code has been ported to other implementations besides Questa.
A list of some of the new features for OVM 2.0 Register Package include:
- Added built-in tests
- register_alias – write one register, read all
- power_on_reset – read all registers, check against reset value
- walking_zeros – write walking zeros, read back, compare
- walking_ones – write walking ones, read back, compare
- write_read – do a write then a read
- Ported to other implementations
Certain SystemVerilog features and capabilities are re-implemented for other implementations. Those changes are wrapped with the appropriate `ifdef. You can run Questa with those turned on if you like.Due to the port, any function that returned a list had to be changed to return the list as an output argument to the function.
- Added UNPREDICTABLEMASK
- Added compare_read_only_bits for selective inclusion or exclusion of read-only bits in the compare
- Added mapped_register_container (replaces ovm_register_map_base)
You can now add a register file to another register file (in addition to all previous behavior)
- ‘resetvalue’ in register constructor is now deprecated
Download OVM Configuration and Virtual Interface Extensions from OVMWorld.org
Creating configurable testbench elements is critical for reuse. If you write some OVM code in one particular testbench and never intend to use it in any other testbench, then there is no need to make it configurable. As soon as you wish to take code and turn it into reusable IP which can be used in a variety of applications, not all of which are immediately known, then you need to think about how to make the code configurable. Making code configurable means that you need to think about the breadth of applications where it will be used and the degrees of freedom you want to make available to the user of this IP.
The author of any verification IP needs to think about how to make that VIP sufficiently flexible to be used in a variety of different scenarios. In order to achieve this, OVM components need to have a number of settings associated with which can be varied by the testbench integrator. These settings may include things such as error injection rates, protocol modes supported or not supported, whether an agent is active or passive, to name but a few.
Future OVM Directions
If you download the OVM Configuration and Virtual Interface Extensions, you will find information on future directions for OVM in the documentation directory. In particular, detaching the configuration scoping mechanism from the OVM component hierarchy is an active area of investigation which might enhance the existing configuration mechanisms in important ways. This would allow one to naturally use the scoping mechanism with “behavioral VIP,” such as sequences, in addition to the current “structural scoping” mechanism that works with OVM components.
Additionally, the current configuration database is limited to storing strings, integers, and objects derived from ovm _ object. Another area of active investigation is enabling the database to store values of any type to solve the efficiency problems when storing and retrieving integral types.
It is also possible to improve and expand the existing wildcarding mechanisms to deal with the full regular expression syntax.
We invite you to join us in the this endeavor and share your thoughts here or on OVM World. To get started, you can download the OVM Configuration and Virtual Interface extensions to learn more.
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- Even More UVM Debug in Questa 10.2
- IEEE Approves New Low Power Standard
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- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
- May 2011 (2)
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- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
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- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
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- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
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