IEEE Standards Meetings in India
EDA & VLSI Standards Focus Meeting on 12 March 2010
As part of its continuing program to reach out to global technologists, the IEEE Standards Association will be conducting a series of outreach sessions throughout Bangalore from 10-12 March 2010. The IEEE-SA will also visit key governmental agencies in Delhi this week as well. While there is a focal technical point for each outreach session, the outreach sessions will address technical subjects in a general manner.
The use of IEEE standards in India, like IEEE 1800™ (SystemVerilog), is quite strong. In a SystemVerilog Users Group meeting I participated in and blogged about last year, we had 100’s of users at both the Noida and Bangalore events participate. Given the large number of users of IEEE standards to do electronic design and verification in India, it is fitting that the IEEE come and share the standards development process and update the community of users on the current status of many areas in a series of outreach meetings.
Not only are there a large number of users in India, many people in India contribute to the development of EDA standards as well. It is also fitting that the IEEE recognize the importance of the large community of standards supporters and developers in India.
The EDA & VLSI standards focus outreach is scheduled for Friday morning, 12 March 2010 at the IBM’s Embassy Golf Links location. There are other outreach meetings scheduled that cover Networking and Communication, Industrial Electronics, Power/Smart Grid, Academic research and standardization, and lastly, Security and Software standardization. For more information about the other outreach meetings, click here.
IEEE-SA Open Seminar: “Global Standards at IEEE”
To begin the week the IEEE-SA Corporate Advisory Group will present “Global Standards at IEEE ” on Tuesday, 9 March 2010, in Bangalore, India at the Royal Ballroom, Leela Palace Hotel.
The seminar is a premier event for those in industry and government who are involved in the advancement of technology and interested to learn more about the global impact of IEEE standards. It will provide an overview of several technical areas undergoing standardization at IEEE, as well as illustrate how local entities can participate in and make use of IEEE’s standards and best practices.
Leaders from industry will provide their insight through presentations and case studies on areas such as smart grid, software life cycle, IEEE 802®, and electronic design automation.
If you want to attend any of the meetings, please register. I look forward to see many familiar faces this coming week in India.
Posted March 7th, 2010, by Dennis Brophy
- Loading tweets...
- Loading tweets...
- Loading tweets...
- Epilogue: The 2012 Wilson Research Group Functional Verification Study
- New Verification Horizons Issue Available
- Happy Halloween from ARM TechCon
- IEEE Standards Association Symposium on EDA Interoperability
- STMicroelectronics: Simulation + Emulation = Verification Success
- A Decade of SystemVerilog: Unifying Design and Verification?
- Part 12: The 2012 Wilson Research Group Functional Verification Study
- Part 11: The 2012 Wilson Research Group Functional Verification Study
- Part 10: The 2012 Wilson Research Group Functional Verification Study
- Part 9: The 2012 Wilson Research Group Functional Verification Study
- November 2013 (2)
- October 2013 (3)
- September 2013 (2)
- August 2013 (4)
- July 2013 (6)
- Part 7: The 2012 Wilson Research Group Functional Verification Study
- Walking in the Desert or Drinking from a Fire Hose?
- Part 6: The 2012 Wilson Research Group Functional Verification Study
- A Short Class on SystemVerilog Classes
- Part 5: The 2012 Wilson Research Group Functional Verification Study
- Part 4: The 2012 Wilson Research Group Functional Verification Study
- June 2013 (2)
- May 2013 (4)
- April 2013 (2)
- March 2013 (2)
- February 2013 (5)
- January 2013 (1)
- December 2012 (1)
- November 2012 (1)
- October 2012 (4)
- September 2012 (1)
- August 2012 (1)
- July 2012 (6)
- June 2012 (1)
- May 2012 (3)
- March 2012 (1)
- February 2012 (6)
- January 2012 (2)
- December 2011 (2)
- November 2011 (2)
- October 2011 (3)
- September 2011 (1)
- July 2011 (3)
- June 2011 (6)
- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
- May 2011 (2)
- April 2011 (7)
- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
- March 2011 (5)
- February 2011 (4)
- January 2011 (1)
- December 2010 (2)
- October 2010 (3)
- September 2010 (4)
- August 2010 (1)
- July 2010 (3)
- June 2010 (9)
- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
- February 2010 (5)
- January 2010 (5)
- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
- September 2009 (2)
- July 2009 (1)
- May 2009 (1)