Archive for February, 2010
… To Advance Technology for Humanity
It is a humbling honor to have been elected chair of the IEEE Standards Association’s (SA) Corporate Advisory Group (CAG). While Corporate Membership in the IEEE SA has been an element of the organization from its inception, it has only been in recent years that it has started to bring the voice of global industry into the IEEE’s standards making process. As CAG chair I plan to work with fellow CAG members to continue to encourage industry to extend its role to guide the IEEE SA and deepen its impact to foster consensus standards that meet industry needs.
The EDA industry and users of EDA technology have played a big role to help the corporate program to take shape. Prior to any EDA standards adopting the IEEE corporate process, “consumer” members of the IEEE 1076 (VHDL) team offered specific feedback in a letter writing campaign to EDA company leadership. Consulted on this campaign prior to its start, I was given an opportunity to weight in, in case I was able to offer a solution to avoid the campaign.
While I agreed with the need for greater direct and clear industry involvement, a revenue tax was probably not the answer. I also indicated I was almost certain that such a request to the highest levels in Mentor Graphics would probably find its way right back to me. The letter to Wally, Mentor Graphics’ CEO, did just that. It found its way to me. And the response back promised to reflect on Mentor’s commitment and that of industry to standards.
The VHDL team planted a seed to consider the question of what industry can do to foster better standards development that binds technologist with industry that I took to heart. A good model was underway in Accellera where SystemVerilog was being crafted that had strong support from Mentor Graphics and Synopsys along with vocal planned user adoption by Intel when their representative spoke at an Accellera press conference on the need for the industry to adopt the language.
While the rest is history for Accellera (and SystemVerilog), it was just the beginning for the IEEE SA. In the year ahead, Gabe Moretti, a member of the IEEE SA New Standards Committee at the time, told me (chair of Accellera at the time) of a growing corporate program in the IEEE SA. The corporate process to make SystemVerilog the IEEE 1800 standard was adopted and used. I also encouraged the VHDL team to follow the same path. The VHDL team was even more inventive and did some of their prep work within Accellera. However, when it came time to return to the IEEE SA, they retained their historical way to complete their work in the IEEE.
My preference is to have active industry participation during standardization. I like to know up front what backing the standard has from industry. The faster we can get industry to back and adopt standards, the faster humanity can benefit from the application of standards.
It is the pace part of industry involvement that has me add something to the new IEEE tag-line: “I do it to advance technology for humanity, quickly.”
The SystemVerilog IEEE 1800-2009 Language Reference Manual (LRM) was published a few months ago with an unprecedented 472 updates. That’s in addition to the changes required as part of the merging process with the Verilog 1364-2005 LRM. And in that five year timeframe, the Mantis system that tracks all of the LRM issues has grown to 986 open issues, becoming a black hole for issues. The SystemVerilog Working Group is collecting input for the next revision.
Inconsistencies in Implementations
There’s a lot of variety in what’s in the latest LRM versus what’s actually implemented in simulators today. Vendors have different sets of customers with different sets of priorities that drive implementing SystemVerilog features. Ambiguities in the LRM that have yet to be addressed wind up as inconsistencies in vendor‘s simulators.
Even some of what was specified in IEEE 1800-2005 has yet to be implemented. Take pattern matching of tagged union for example. This feature was put into Accellera SystemVerilog before IEEE standardization, but to my knowledge, had yet to be implemented in any simulator.
Why? There are several reasons. The most likely reason is that no customer has asked for it, or it has been below the threshold level to make it into anyone’s list to be implemented. Another reason is that there might be ambiguities in the LRM that need to be resolved before the feature can even begin to be implemented.
The result of all this is that users who want vendor interoperability are forced into restricted coding rules that limit themselves to a much smaller subset of SystemVerilog. Those same users often fail to realize that they need to drive their vendors to follow and fix the standard (See the recent discussion at Cool Verification).
How did we get into this situation? Part of the problem lies with the PAR process. This is the IEEE process mandated to produce a revision of a standard. Five years is too long between revisions for an actively used standard. Users running into gaping holes in SystemVerilog functionality usually drive their vendors to bypass the PAR process and introduce proprietary extensions.
A Proposed Solution
After such a long revision process with so many changes, both users and vendors need to catch their breath. While it may be too radical to say no changes, we can propose a short period of stabilization where the main focus would be to address errata and ambiguities that drive convergence in implementations. We can improve the process that lets enhancements into the standard by making sure there is widespread support for that enhancement before work begins on it. Other areas for improvement could be to split the LRM is to separate standards (DPI/PLI) with their own schedules.
Input from users is welcome and needed.
Duolog Joins Agnisys to Add Reg Pac Support
The OVM 1.0 Register Package has had a lot of interest since uploaded a few weeks back. With more than 1,100 downloads and counting, it is being qualified for use and deployment in a growing number of user verification environments.
Complementing the availability of the OVM 1.0 Register Package is support by partners with their applications that promote greater verification efficiency and use of the register package. Today, Duolog joined Agnisys to announce an update to their OVM auto-generation solution to now support the OVM 1.0 Register Package on the Mentor Questa verification platform.
OVMWorld offers a unique, active and vibrant contributions area tfor the OVM community to explore supplemental packages from any source to augment the base OVM kit. There are a large number of partners that, as in the case of Doulog and Agnisys, have added to the user experience with the direct support of the OVM 1.0 Register Package..
You can catch Duolog representatives around DVCon this week to see how they can help you take advantage of the ever expanding OVM contributions.
What OVMWorld contributions have you liked the best? Which ones should be added to the base OVM kit? Do you have something to share? We would like to understand what your priorities are to promote community contributions into the main kit.
SystemC User Group Meeting & DVCon Tutorial Featured
The Open SystemC Initiative (OSCI), an independent non-profit organization dedicated to support and advance SystemC™ as an industry-standard language for electronic system-level (ESL) design, announced its lineup of events at DVCon 2010, most notably the first annual SystemC Day on Monday, Feb. 22.
Mentor Graphics is one of the sponsors for the event and we will share updates on products that support SystemC during the SystemC Supplier Showcase between 10:00 a.m. – 2:00 p.m. Visit us at the Showcase or at the DVCon tradeshow.
How to Register
Admission is free with advance registration to the North American SystemC Users Group Meeting (NASCUG 12) and complimentary lunch. The afternoon tutorial is part of the DVCon program and requires separate registration.
- NASCUG 12 Meeting and Lunch
Register at: www.mod-marketing.com/osci (FREE)
- DVCon Tutorial: The OSCI TLM-2.0 Standard and Synthesis Subset
Register at: www.dvcon.org/reg.html ($60 DVCon Fee)
|8:30 am – 12:00 pm||NASCUG 12 Meeting (Full agenda at www.nascug.org)|
|10:00 am – 2:00 pm||Sponsor Tabletop Exhibits|
|12:00 pm – 1:30 pm||OSCI Sponsored Lunch|
|1:30 pm – 5:00 pm||DVCon Tutorial: “The OSCI TLM-2.0 Standard and Synthesis Subset
|5:00 pm||DVCon Hosted Reception|
As I mentioned in a previous blog, the Accellera OVM/VMM Interoperability kit code that is a companion to the Verification Intellectual Property Recommended Practices (1MB PDF) was nearing readiness. As of today, it is now ready for download and use. With qualification tests run on verification platforms from the Big-3 EDA companies, no objection was voiced at a recent Accellera VIP-TSC meeting against it being released for general industry use and adoption.
Congratulations to the Accellera VIP-TSC for hitting this huge milestone!
This kit contains an OVM/VMM interoperability library that meets and exceeds the requirements recently approved by the Accellera VIP-TSC. It includes a growing collection of adapters and utilities that enable easy and flexible reuse of existing IP in both OVM and VMM environments. Both library’s use-models are fully preserved, and no modifications to existing IP are needed.
Team OVM has created a version of the VMM 1.1b kit that needs to be downloaded from OVM World to work with the Accellera interoperability kit. In addition to modifications needed to get VMM 1.1 in compliance with standard SystemVerilog and to workaround differences in simulator implementations, the VMM 1.1b kit also incorporates changes to enable interoperability with OVM.
To setup your environment requires making sure you have installed and are pointing to qualified versions of simulators, libraries, and utilities. The release notes and overview documentation contained in the kit offer full details on how to use the kit. Basic information is shown below.
The Accellera VIP-TSC welcomes suggestions for improvements to the Verification Intellectual Property Recommended Practices and Interoperability Kit. They should be sent to the VIP email reflector: email@example.com.
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- Even More UVM Debug in Questa 10.2
- IEEE Approves New Low Power Standard
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- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
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- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
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- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
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- Part 3: The 2010 Wilson Research Group Functional Verification Study
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- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
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- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
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