Archive for January, 2010
No, this is not an early Olympics update.
But none the less, these three organizations have all earned 10’s. Thursday, 28 January 2010 at EDSFair, JEITA EDA-TC the Japan Electronics and Information Technology Industries Association’s standards group, celebrated their 10-year anniversary. The JEITA EDA-TC collaborates with the IEEE, Accellera and the Open SystemC Initiative. During the EDSFair opening remarks, JEITA announced their 10-year anniversary and recognized SystemC’s and Accellera’s 10-year anniversaries as well. Three organizations celebrated 10 years of bringing standards to the electronics industry.
Accellera and OSCI were invited to offer a welcome speech of congratulations to JEITA. As vice-chair of Accellera, I spoke on behalf of Accellera to a standing-room only crowd. Dr. Stan Krolikoski, treasurer of OSCI spoke on behalf of OSCI.
The engineers assembled heard from JEITA speakers under the theme that each of them is the best engineer in their company. Accellera and OSCI both reinforced their commitments to evolve and advance design automation standards to forge productivity and interoperability to help all the “number one” engineers to continue to be the “best engineers” they can be.
The following day, at the joint IEEE Design Automation Standards Committee (DASC) and JEITA EDA-TC standards meeting, Shigemi Saito (from Sony) and EDSF2010 executive committee chair and past chair of the EDA-TC standards activities announced his retirement from Sony effective at the end of the day. After 31 years with Sony, Saito-san will cast his sail and set a new course. He has been a friend of EDA standards for many years. And I thank him for this friendship and his help two years ago when the IEEE Standards Association held an educational seminar at “Sony Square” in Tokyo. The seminar opened with a welcome keynote from Sony’s Keiji Kimura, EVP, Corporate Executive Officer, Officer in Charge of Technology Strategies, Intellectual Property and Electronics Business Strategies. Kimura-san cited the importance of EDA standards as they underpin all electronic design and called out by name many that are used by Sony. I know Saito-san was instrumental to bring out the importance of EDA standards for Kimura-san to share. Saito-san, I wish you a happy retirement!
After months of field testing and several beta releases the past few years, Mentor Graphics has released the OVM 1.0 Register Package. The package can be download from the OVMWorld.org contributions area.
The download includes complete online HTML-based documentation at your fingertips. You can use the navigation bar at left to expand categories and click on the topic of choice. The body of the documentation is also hyperlinked for convenient navigation to related topics for more detailed descriptions of a
particular class method or variable. The download also includes the OVM Register Package User Guide and the OVM Register Package Reference Guide to help you.
Requirements for continue verification productivity improvements show no signs of easing. Demands on OVM to manage and control registers in SOC designs is just one example of the pressing productivity improvement requirements. SOC’s not only have high registers counts, but the relationship between operating modes defined by the resisters can be very complex. The OVM 1.0 Register Package addresses those issues.
We continue to seek feedback on your application of the OVM 1.0 Register Package at firstname.lastname@example.org to enhance and advance verification productivity.
Users Can Start Migration to OVM Today
Accellera’s Verification Intellectual Property (VIP) Technical Committee (TC) co-chair issued a public status report that highlights the group’s progress on its first phase of work, the OVM/VMM Interoperability Guide and companion software interoperability kit, and its second phase of work, a common base class library (CBCL) with OVM as its basis.
As the market accelerated its adoption of OVM in 2009, a smooth exit for VMM developers and users became increasingly apparent.
To address the exit and facilitate a smooth transition, Mentor Graphics drove the first phase of the committee’s work to protect users’ prior investments in VMM-based VIP so they can be reused in OVM testbenches. The companion open-source interoperability kit works in Questa now and should shortly pass all tests in other industry verification tools as well as highlighted in the VIP-TC status report.
As the Big-3 EDA companies embraced the Accellera VIP-TC phase one project, the worst kept secret was OVM was, by necessity, running in all their verification tools.
Now that Accellera has selected OVM, all the reasons for VMM developers and users to plan and make the transition to OVM today are clear. Team OVM has made sure there is no need to wait to start your transition with a large resource base on OVMWorld.org to help.
- OVM Download – here
- OVM Documentation Resources – here
- OVM Recorded Webinar – here
- VMM that works with the Accellera Interoperability Kit – here
- Accellera Interoperability Kit – here
As Accellera holds meetings to discuss additional common base class library features, Mentor understands users have a need to get down to the business of verification today. The OVM Team has all the necessary elements on OVMWorld.org to make your transition smooth. You can start your transition today with confidence.
OSCI Expands Use of Social Media to Promote SystemC
It is a challenge for the global SystemC community to participate in conference update sessions and regional user group meetings in person to keep abreast of the SystemC developments. The OSCI website is full of information to help keep current on SystemC, but one often has to use a standard computer to access more advance audio and video content making it inconvenient. With the advent of net-ready devices that are YouTube capable (televisions, DVD/blue-ray players, Smartphones, etc.) or social media aggregation sites like MobileTribe, OSCI has created a YouTube channel you can subscribe to where you will find short clips posted to share informational and educational sessions from recent technical conferences and user group meetings
An example of a short discussion by John Anysley of Dolous on SystemC TLM 2.0 is offered here as a sample of what can be found on the SystemC YouTube channel.
While YouTube cannot substitute for the richer video synced with the actual slides presented that can be found at the OSCI website, like those for the 11th North American SystemC Users Group (NASCUG) meeting, it certainly offers a more convenient outlet to get information. I only wonder what a family response would be to the question “Do you mind if I change the station to the SystemC YouTube channel?” [Yes, I’ve watched me on full screen HD via YouTube, and it is convenient.]
If you would like to be alerted to new videos on SystemC as they are posted, you can subscribe to OSCI’s YouTube channel for notification. Web-based video sessions from DVCon and DAC are generally made available to YouTube six months after first publication at systemc.org.
The SystemC Promotions Group, which I chair, will meet shortly to review promotional activities in 2010 and I anticipate we will continue to expand the use of web-based offerings to help bring timely information to more people globally. Do you have a preferred way to learn about SystemC that we should know about? Let me know and I will share it with the OSCI promotions group.
As OSCI promotion group chair, I thank those companies that sponsor global SystemC promotion activities for adding video content from select technical conferences and user group meetings this past year and for their continued support in 2010.
PROLOGUE: Over the weekend, I was thinking about a recent visit I had with an advanced ASIC team manager who told me that they had optimized most aspects of their verification flow to such an extent that most of their remaining effort was spent in debugging. So, I decided to work up a draft blog on debugging. However, this morning, when I was preparing to post my blog, I noticed that Richard Goering had beat me to the punch and had posted a blog on debugging about two weeks ago. Having reviewed his blog, I think we are both in agreement—debugging is a huge bottleneck in the flow. I think that debugging must be looked at as a solution, and not a tool feature. However, there are many aspects of debugging beyond traditional simulation triage of design models and testbench components—ranging from embedded software, to power and performance analysis, to code and functional coverage closure, etc. There really isn’t a unified solution—debugging must be considered an integral part of each aspect of design and verification.
ACT 1: My original blog from this weekend….
“Bloody instructions, which, being taught, return to plague the inventor….”
William Shakespeare, Macbeth, act 1, scene 7
All right, even Shakespeare had issues with debugging. But before I get into all of that, let me set the stage with a little background info…
First, let me say that I love my job. My role at Mentor Graphics consists of a diverse set of tasks. Yet, probably my most rewarding work involves studying and assessing today’s electronics industry. The objective of this work is to help Mentor identify discontinuities in today’s EDA solutions, as well as understand emerging verification challenges. But what I like most about my work is that it allows me to participate in detailed discussions with various project teams and multiple industry thought leaders across multiple market segments.
A couple of years ago, I was performing a detailed verification assessment for an ASIC project team. As I usually do when I conduct these kinds of assessments, I asked the team what was the biggest bottleneck in their flow. This one enthusiastic, young engineer started waving his hand vigorously at me and said: “I know, I know…..it’s layoffs!” Okay, so after the group recovered itself from an outburst of nervous chuckles, I pressed forward with my question. It turned out that the group unanimously agreed that debugging was generally a significant, yet often underestimated, effort associated with their flow. Perhaps this shouldn’t surprise anyone, when you consider that the Collett International 2003 IC/ASIC Design Closure study found that 42 percent of the verification effort was consumed in writing test and creating testbenches, while 58 percent was consumed in debugging. More recently, a 2007 Farwest Research study, chartered by Mentor Graphics, found that 52 percent of a dedicated verification engineers effort was consumed in debugging.
The problem with debugging is that the effort is not always obvious since it applies to all aspects of the design and verification flow and often involves many different stakeholders. For example, architectural modeling, RTL coding, testbench implementation, transaction modeling, embedded software, coverage modeling and closure, and on and on and on. What makes it particularly insidious is that it is extremely difficult to predict or schedule. In fact, what you will find is that a mature organization relies on historical data extracted from their previous project’s debugging effort metrics in order to estimate their future project effort. However, due to the unpredictable nature of debugging, history doesn’t always repeat itself. And unfortunately, there is no silver bullet in terms of a single debugging tool or strategy. Multiple solutions, ranging from RTL implementation debugging, to OVM object-oriented testbench component debugging, to embedded software debugging capabilities, to coverage closure are required. Fortunately, multiple good solutions have emerged, ranging from assertions for reducing RTL debugging effort, to SystemVerilog dynamic structures analysis and debugging, to processor-driven verification debugging solutions for embedded software verification, to the intelligent testbench for automating coverage closure.
EPILOGUE: I opened this blog humorously with a quote from Shakespeare. Yet, today’s debugging effort is no laughing matter, and it contributes significantly to a project’s overall design and verification effort. I’ll conclude this blog with a sobering quote from Brian Kernighan (the K in the K&R C language) who once pointed out:
Debugging is twice as hard as writing the code in the first place.
I’m curious about your thoughts. Does debugging consume a significant amount of effort in your flow? If not, what is the biggest bottleneck in your flow?
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- Even More UVM Debug in Questa 10.2
- IEEE Approves New Low Power Standard
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- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
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- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
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- User-2-User’s Functional Verification Track
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- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
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- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
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- Truth in Labeling: VMM2.0
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- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
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- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
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