Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)

Back to the Future; Unleash the Past

No, I’m not talking about the Michael J. Fox and Christopher Lloyd movie. Nor am I a talking about unleashing zombies from the Zombieland to make the present the dead past.  I’ve given more thought to the DTC after reading some questions Brian Bailey asked in his “I don’t understand this new IEEE EDA User group.” His post that led me to dig deeper, ask questions and issue a Zombie Alert.  (OK, the zombie alert is just humor.)

It appears that after more than a decade the Design Technology Council (DTC) has announced it has abandoned Si2 in favor of IEEE CEDA (Council on EDA) and it has changed its name to the Design Technology Committee.  It keeps the DTC acronym, presumably in a move to save on a redo of letterhead. (OK, I can’t resist a bit of sarcasm.)

The announcement made me think we are either going back to the future or unleashing the dead past.  Watch out – the zombies just might just be on the loose.

Given that CEDA is a collection of IEEE Societies that are replete with immense technical talent and brainpower to help address next generation design issues, the DTC may well be in a better home.  They also intend to interact with other standards setting organization as well.  For these reasons, I think think this is a great move!

Yet, when I read the whole of their press release again, I’m left with skepticism that was only fed by Brian’s words on the topic as well.

1.   Captive EDA Represents themselves as the User and Commercial EDA as not?
Are they really users?  The corporate affiliations of the DTC members is impressive! Their corporations are associated with some of the most advanced designs being done today. If anyone knows hard problems, they do.  If anyone wants solutions, EDA should listen to them.

But when I read the titles of the current members I see a majority of them have CAD or EDA in them.  Are they actually designers or Captive EDA representatives?  Is Captive EDA any different from a Commercial EDA company?  (I came from a Captive EDA group to Mentor Graphics, so I have some history here.  Maybe that’s a topic of a future blog.)

Is this action to form inside CEDA being taken due to a lack of technology response by Commercial EDA or to represent Captive EDA self-interests?  Can Captive EDA be seen as yet another middleman in a vendor/supplier relationship?  Does that promote business efficiency of is it suboptimal?

Can a closed group like this that segregates Captive and Commercial EDA be seen as restraining and hampering trade?  Or could it be that Captive EDA seeks to be a focal point for Commercial EDA business relationships to rationalize its existence?  I do note that Gary Smith has presented his findings on a resurgence of Captive EDA. One can only conclude the resurgence is borne out of necessity and lack of Commercial EDA to address some pressing technical design challenges.

2.   Something “NEW” was announced; but it is the same “OLD” thing
Can a group that announces it is new by concealing its past be that trusted?  I’ve seen some blog comments that support a conclusion of confusion.  Questions are asked is the DTC still in Si2?  Does the industry need another DTC?

The truth is this group is has been around for a long time, not “newly formed” as they would suggest to all. The simple fact is the DTC moved.  Concealing this information makes no sense to me.  It just heightens my suspicion.

3.   It is a CLOSED group
The press release says they “consists of leaders exclusively from semiconductor and systems companies who use EDA tools.”  And they seek to expand as they say “nominations for new members are actively being solicited.”

Don’t get me wrong. I think it is great the DTC explores ways to rejuvenate itself and drive greater self relevance. It is good they have made a call for nominations for additional members. The DTC needs to expand their ranks as they are more cloistered in their configuration and out of touch with the current design practice in the world.

While no one group may be able to address all problems and solve all issues at once, a group that does not have representatives that play important roles in an age of design reuse where IP suppliers are important or when it does not represent the swelling ranks of programmable logic designers, it is not relevant to the majority of design practice today.

Since EDA vendors are not invited to participate, may I offer this thought through this venue: Don’t stay parochial. Don’t go back to the past. Recognize the future encompasses more than who you have been or are today. The challenges of a majority of designers globally should be part of your focus as you encourage interoperable design flows.  To be the voice, you must be the body.

4.   The DTC will communicate; but they will make it hard for anyone to hear what they say.
How can a group that is to be the voice of users be heard when they are closed?

If they want to be the user voice, what have they said the past decade?  The voice of the user has been center to their theme since their inception under Si2.  Yet there is no easily found record of the users’ voice being recorded.  Even Google has a hard time to find any recording of this.  It can find the promise to be the voice way back to 2001, but no recording of the actual voice.

Is a long standing promise unfulfilled just hallow when committed to today?

5.   Are the proposed DTC business models anti-competitive?
The DTC says in their press release they will “communicate with each other … [on] business models through which [they] access design tools.”  Yet such an action in the opposite direction (all EDA vendors getting together to say how they will sell) would be seen as anti-competitive and a restraint of trade.

Collective price negotiation is potentially anti-competitive if it results in the exercise of market power by buyers.  Are the large EDA consumers banding together to exert monopsony power to create a buyer’s monopoly?

The DTC Vice-Chair, Thomas Harms, is looking to both grow DTC membership (users-only) and start a business model discussion on Twitter. Could those membership actions make the DTC a more powerful buyers collective? A conversation on business models has already been started on Twitter.  Thomas and Cadence CMO have exchanged thoughts, as have many others.  In one of Thomas’ tweets, it seems there is some thought that the world would be better if there was one of anything from EDA to bring to a halt the duplicating of products and the waste of R&D resources.  Humm, are we soon to see one CPU architecture and one supplier, one semiconductor fabricator, one IP supplier, one bus interconnect model – one  of everything?

HarmsTweet

Is IEEE CEDA’s goal to foster collective bargaining on the part of buyers?  Can you guess if this is where I want my IEEE dues and profits from the Design Automation Conference being spent?

My Hope
Go Forward to the Future. Unleash the Present. Don’t call all zombies from the past back to life.  Become an active voice of the users.  Share what you learn with all.  From where I sit, we seek input from a wide body of users.  We hope this group joins a larger community of users who seek more from EDA, give advice to EDA and in turn get more as we listen to you.

You have my ear….

What do you think?

Post Author

Posted December 10th, 2009, by

Post Tags

,

Post Comments

No Comments

About Verification Horizons BLOG

This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool. Verification Horizons BLOG

@dennisbrophy Tweets

  • Loading tweets...

@dave_59 Tweets

  • Loading tweets...

@jhupcey Tweets

  • Loading tweets...

Comments

Add Your Comment

Archives

September 2014
  • Portable and Productive Test Creation with Graph-Based Stimulus
  • Supporting A Season of Learning
  • August 2014
  • DVCon Goes Global!
  • Better Late Than Never: Magical Verification Horizons DAC Edition
  • July 2014
  • Accellera Approves UVM 1.2
  • May 2014
  • Getting More Value from your Stimulus Constraints
  • The FPGA Verification Window Is Open
  • April 2014
  • UVM DVCon 2014 Tutorial Video Online
  • Mentor Enterprise Verification Platform Debuts
  • March 2014
  • New Verification Academy ABV Course
  • DVCon 2014 Issue of Verification Horizons Now Available
  • February 2014
  • DVCon–The FREE Side
  • More DVCon–More Mentor Tutorials!
  • UVM 1.2: Open Public Review
  • DVCon 2014: Standards on Display
  • Just because FPGAs are programmable doesn’t mean verification is dead
  • January 2014
  • Managing Verification Coverage Information
  • November 2013
  • Epilogue: The 2012 Wilson Research Group Functional Verification Study
  • New Verification Horizons Issue Available
  • October 2013
  • Happy Halloween from ARM TechCon
  • IEEE Standards Association Symposium on EDA Interoperability
  • STMicroelectronics: Simulation + Emulation = Verification Success
  • September 2013
  • A Decade of SystemVerilog: Unifying Design and Verification?
  • Part 12: The 2012 Wilson Research Group Functional Verification Study
  • August 2013
  • Part 11: The 2012 Wilson Research Group Functional Verification Study
  • Part 10: The 2012 Wilson Research Group Functional Verification Study
  • Part 9: The 2012 Wilson Research Group Functional Verification Study
  • Part 8: The 2012 Wilson Research Group Functional Verification Study
  • July 2013
  • Part 7: The 2012 Wilson Research Group Functional Verification Study
  • Walking in the Desert or Drinking from a Fire Hose?
  • Part 6: The 2012 Wilson Research Group Functional Verification Study
  • A Short Class on SystemVerilog Classes
  • Part 5: The 2012 Wilson Research Group Functional Verification Study
  • Part 4: The 2012 Wilson Research Group Functional Verification Study
  • June 2013
  • Part 3: The 2012 Wilson Research Group Functional Verification Study
  • Part 2: The 2012 Wilson Research Group Functional Verification Study
  • May 2013
  • Texas-Sized DAC Edition of Verification Horizons Now Up on Verification Academy
  • IEEE 1801™-2013 UPF Standard Is Published
  • Part 1: The 2012 Wilson Research Group Functional Verification Study
  • What’s the deal with those wire’s and reg’s in Verilog
  • April 2013
  • Getting AMP’ed Up on the IEEE Low-Power Standard
  • Prologue: The 2012 Wilson Research Group Functional Verification Study
  • March 2013
  • Even More UVM Debug in Questa 10.2
  • IEEE Approves New Low Power Standard
  • February 2013
  • Verification Horizons DVCon Issue Now Available
  • Get your IEEE 1800-2012 SystemVerilog LRM at no charge
  • IEEE 1800™-2012 SystemVerilog Standard Is Published
  • See You at DVCon 2013!
  • Get Ready for SystemVerilog 2012
  • January 2013
  • VHDL Update Comes to Verification Academy!
  • December 2012
  • IEEE Approves Revised SystemVerilog Standard
  • November 2012
  • Coverage Cookbook Debuts
  • October 2012
  • IoT: Internet of Things
  • Check out the October, 2012 Verification Horizons
  • Improving simulation results with formal-based technology
  • Introducing “Verification Academy 2.0”
  • September 2012
  • OVM Gets Connected
  • August 2012
  • OpenStand & EDA Standardization
  • July 2012
  • Synthesizing Hardware Assertions and Post-Silicon Debug
  • Virtual Emulation for Debugging
  • Verification Academy: Up Close & Personal
  • SystemC Standardization Cycle Completes
  • Verification Standards Take Another Step Forward
  • New UVM Recipe of the Month: Scoreboarding in UVM
  • June 2012
  • Intelligent Testbench Automation – Catching on Fast
  • May 2012
  • Two Articles You Need to Check Out
  • Off to DAC!
  • Dave Rich Featured on EEWeb
  • March 2012
  • How Did I Get Here?
  • February 2012
  • Expanding the Verification Academy!
  • Get on the Fast Track to Advanced Verification with UVM Express
  • Introducing UVM Connect
  • Tornado Alert!!!
  • UVM: Some Thoughts Before DVCon
  • UVM™ at DVCon 2012
  • January 2012
  • SystemC 2011 Standard Published
  • Verification solutions that help reduce bug cost
  • December 2011
  • Instant Replay for Debugging SoC Level Simulations
  • 2011 IEEE Design Automation Standards Awards
  • November 2011
  • Getting started with the UVM – Using the Register Modeling package
  • TLM Becomes an IEEE Standard
  • October 2011
  • Worlds Standards Day 2011
  • VHS or Betamax?
  • Verification Issues Take Center Stage
  • September 2011
  • New UVM Recipe-of-the-Month: Sequence Layering
  • July 2011
  • Combining Intelligent Testbench Automation with Constrained Random Testing
  • Going from “Standards Development” to “Standards Practice”
  • Verification Academy Now Includes OVMWorld Content
  • June 2011
  • Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
  • Part 9: The 2010 Wilson Research Group Functional Verification Study
  • Verification Horizons DAC Issue Now Available Online
  • Accellera & OSCI Unite
  • The IEEE’s Most Popular EDA Standards
  • UVM Register Kit Available for OVM 2.1.2
  • May 2011
  • Part 8: The 2010 Wilson Research Group Functional Verification Study
  • Getting Your Standards Update @ DAC 2011
  • April 2011
  • User-2-User’s Functional Verification Track
  • Part 7: The 2010 Wilson Research Group Functional Verification Study
  • Part 6: The 2010 Wilson Research Group Functional Verification Study
  • SystemC Day 2011 Videos Available Now
  • Part 5: The 2010 Wilson Research Group Functional Verification Study
  • Part 4: The 2010 Wilson Research Group Functional Verification Study
  • Part 3: The 2010 Wilson Research Group Functional Verification Study
  • March 2011
  • Part 2: The 2010 Wilson Research Group Functional Verification Study
  • Part 1: The 2010 Wilson Research Group Functional Verification Study
  • Prologue: The 2010 Wilson Research Group Functional Verification Study
  • Language Transitions: The Dawning of Age of Aquarius
  • Using the UVM libraries with Questa
  • February 2011
  • DVCon: The Present and the Future
  • Free at Last! UVM1.0 is Here!
  • Parameterized Classes, Static Members and the Factory Macros
  • IEEE Standards in India
  • January 2011
  • Accellera Approves New Co-Emulation Standard
  • December 2010
  • New Verification Horizons: Methodologies Don’t Have to be Scary
  • The Survey Says: Verification Planning
  • October 2010
  • Towards UVM Register Package Interoperability
  • IEC’s 47th General Assembly Meeting Opens
  • UVM: Giving Users What They Want
  • September 2010
  • UVM Takes Shape in the Accellera VIP-TSC
  • Accellera VIP-TSC Selects RAL for UVM 1.0 Register Package
  • OVM Cookbook Available from OVMWorld.org
  • UVM Register Package Candidate News
  • August 2010
  • Redefining Verification Performance (Part 2)
  • July 2010
  • Making formal property checking easy to use
  • Redefining Verification Performance (Part 1)
  • SystemVerilog Coding Guidelines: Package import versus `include
  • June 2010
  • The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
  • New Verification Academy Advanced OVM (&UVM) Module
  • OVM/UVM @DAC: The Dog That Didn’t Bark
  • DAC: Day 1; An Ode to an Old Friend
  • UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
  • Static Verification
  • OVM/UVM at DAC 2010
  • DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
  • Accellera’s DAC Breakfast & Panel Discussion
  • May 2010
  • Easier UVM Testbench Construction – UVM Sequence Layering
  • North American SystemC User Group (NASCUG) Meeting at DAC
  • An Extension to UVM: The UVM Container
  • UVM Register Package 2.0 Available for Download
  • Accellera’s OVM: Omnimodus Verification Methodology
  • High-Level Design Validation and Test (HLDVT) 2010
  • New OVM Sequence Layering Package – For Easier Tests
  • OVM 2.0 Register Package Released
  • OVM Extensions for Testbench Reuse
  • April 2010
  • SystemC Day Videos from DVCon Available Now
  • On Committees and Motivations
  • The Final Signatures (the meeting during the meeting)
  • UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
  • UVM-EA (Early Adopter) Starter Kit Available for Download
  • Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
  • March 2010
  • The Art of Deprecation
  • OVM 2.1.1 Now Ready for Download
  • February 2010 Verification Horizons Newsletter Now Available
  • IEEE Standards Meetings in India
  • February 2010
  • I Do It …
  • SystemVerilog: A time for change? Maybe not.
  • Partners Offer Support for OVM 1.0 Register Package
  • SystemC Day at DVCon
  • OVM/VMM Interoperability Kit: It’s Ready!
  • January 2010
  • Three Perfect 10’s
  • OVM 1.0 Register Package Released
  • Accellera Adopts OVM
  • SystemC (IEEE Std. 1666™) Comes to YouTube
  • Debugging requires a multifaceted solution
  • December 2009
  • A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
  • Truth in Labeling: VMM2.0
  • IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
  • December Verification Horizons Issue Out
  • Evolution is a tinkerer
  • It Is Better to Give than It Is to Receive
  • Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
  • DVCon is Just Around the Corner
  • The “Standards Corner” Becomes a Blog
  • I Am Honored to Honor
  • IEEE Standards Association Awards Ceremony
  • ABV and being from Missouri…
  • Time hogs, blogs, and evolving underdogs…
  • Full House – and this is no gamble!
  • Welcome to the Verification Horizons Blog!
  • September 2009
  • SystemVerilog: The finer details of $unit versus $root.
  • SystemVerilog Coding Guidelines
  • July 2009
  • The Language versus The Methodology
  • May 2009
  • Are Program Blocks Necessary?