ABV and being from Missouri…
The last industry project I worked on, before joining EDA, was an advanced chip set for a very large, high-end server product line. The project consisted of a large team, spanning multiple years, with numerous physical, design, and verification challenges. During the project’s postmortem, where all the various engineering teams get together to discuss what worked well and what did not, I overhead one of the design engineers say that he would never do another design project without assertions. In fact, his opinion was universally shared among all the project designers. Now, wait a minute, notice I said designers. What gives? When questioning the design team further, I heard them say that assertions actually made their life easier. The team claimed that the extra time it took them to add assertions during the RTL coding stage was more than made up for by the reduction in debugging time during verification. Not only that, they claimed that often the act of adding an assertion forced them to think about the design in a different way and even exposed a design error prior to any form of verification. Now that’s productivity!
All right, so if this stuff is so great, then why isn’t everyone doing it? In fact, a large industry study conducted by Farwest Research in conjunction with Mentor Graphics late in 2007 revealed that only 37 percent of the industry had adopted and integrated ABV techniques into their flow. This intrigues me—particularly since there have been numerous case studies published by best in class companies over the past 15 years that quantitatively demonstrate the benefits of adopting ABV into the project flow. So I decided to dig a little deeper into this situation, and this is what I found:
Project teams need help in understanding the methodological aspects of integrating ABV into their existing flow.
There are a number of myths held by non-believers that need to be addressed before adoption can proceed.
If you look at the myriad of material that has been published on ABV over the past few years, what you will find is that most of the discussions focus on value propositions and specific ABV tools, or the discussion delves into details of a particular assertion language. However, what I hear from various teams trying to adopt ABV often takes a more methodological bent, particularly related to the required steps for successfully integrating ABV into existing flows.
To address these concerns, at DAC 2008, with the sponsorship of Accellera, I organized a successful workshop titled: Beyond Syntax and Semantics: Industry Experiences with OVL/SVA/PSL.
I recognized that successful application of these assertion language standards in an industrial setting requires the development of project team member skills and verification process maturity beyond a simple understanding of assertion language syntax and semantics. Hence, the workshop was organized so that folks from multiple industry projects would share their experiences of applying ABV on real projects—with a focus on answering these questions:
What is required to mature a project team’s ABV skills for successful adoption?
What needs to be considered in terms of a project’s ABV infrastructure (beyond commercial tools)?
What metrics need to be defined (and gathered) to measure progress?
What benefits are real-industry projects seeing using OVL/SVA/PSL?
Going forward, what I plan to do in the next few weeks is create a set of related blogs where I address both the methodology aspects of integrating ABV into a project flow and a number of commonly held myths about ABV.
I’d like to hear from you. Who has successfully integrated ABV into the flow? For those who have not started, what are the obstacles you see to adoption?
Posted December 6th, 2009, by Harry Foster
- Loading tweets...
- Loading tweets...
- Portable and Productive Test Creation with Graph-Based Stimulus
- Supporting A Season of Learning
- DVCon Goes Global!
- Better Late Than Never: Magical Verification Horizons DAC Edition
- Accellera Approves UVM 1.2
- Getting More Value from your Stimulus Constraints
- The FPGA Verification Window Is Open
- UVM DVCon 2014 Tutorial Video Online
- Mentor Enterprise Verification Platform Debuts
- New Verification Academy ABV Course
- September 2014 (2)
- August 2014 (2)
- July 2014 (1)
- May 2014 (2)
- April 2014 (2)
- March 2014 (2)
- February 2014 (5)
- January 2014 (1)
- November 2013 (2)
- October 2013 (3)
- September 2013 (2)
- August 2013 (4)
- July 2013 (6)
- Part 7: The 2012 Wilson Research Group Functional Verification Study
- Walking in the Desert or Drinking from a Fire Hose?
- Part 6: The 2012 Wilson Research Group Functional Verification Study
- A Short Class on SystemVerilog Classes
- Part 5: The 2012 Wilson Research Group Functional Verification Study
- Part 4: The 2012 Wilson Research Group Functional Verification Study
- June 2013 (2)
- May 2013 (4)
- April 2013 (2)
- March 2013 (2)
- February 2013 (5)
- January 2013 (1)
- December 2012 (1)
- November 2012 (1)
- October 2012 (4)
- September 2012 (1)
- August 2012 (1)
- July 2012 (6)
- June 2012 (1)
- May 2012 (3)
- March 2012 (1)
- February 2012 (6)
- January 2012 (2)
- December 2011 (2)
- November 2011 (2)
- October 2011 (3)
- September 2011 (1)
- July 2011 (3)
- June 2011 (6)
- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
- May 2011 (2)
- April 2011 (7)
- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
- March 2011 (5)
- February 2011 (4)
- January 2011 (1)
- December 2010 (2)
- October 2010 (3)
- September 2010 (4)
- August 2010 (1)
- July 2010 (3)
- June 2010 (9)
- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
- February 2010 (5)
- January 2010 (5)
- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
- September 2009 (2)
- July 2009 (1)
- May 2009 (1)