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SystemC 2011 Standard Published

January 16th, 2012, by | Permalink | 1 Comment

IEEE Std. 1666™-2011 Available as Free Download

In November 2011 I blogged the IEEE Standards Association (SA) approved a revision to the popular SystemC standard, known officially as IEEE Std. 1666™-2011.  One of the key elements of this standard includes the addition of Transaction Level Modeling (TLM).  I pointed to several online resources to learn more about the revised SystemC standard in that blog.  But missing from the list of resources was information on how to get the revised standard from the IEEE.  As I concluded my blog, I indicated that the final editorial review and formatting for publication was underway and that I would report back when this work was completed.

IEEE Std 1666-2011I can report that the IEEE SA concluded their editing of the specification and it is now ready for download.  Many of you know the prior version of the SystemC standard was available for free download and have wondered if this would be the same for this revision update.  The good news is the revision update is available as a free download as well.  If you wish to have a printed and bound copy, that too is available, but that will have to be purchased.

IEEE Std. 1666-2011 is part of the “IEEE Get Program” that offers individuals the ability to retrieve, download and print one copy of the standard for free.  Click on the link above to get your personal copy of the standard.  You will need to share some basic information with the IEEE on your user type (Academic, System/Semiconductor Company,  EDA Company, IP Company or Other).  This is certainly worth if for a free copy.

The original standard, IEEE Std. 1666™-2005, had more than 50,000 free downloads since it was made available and I expect this version to do even better.  With the addition of TLM to the standard and the move up in abstraction to handle system design requirements, the need for this standard is even more pressing today.

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Verification solutions that help reduce bug cost

January 8th, 2012, by | Permalink | 1 Comment

I think very few engineers would argue with the claim that the longer a bug goes undetected, the more expensive it is to fix. In fact, the general rule-of-thumb is that the cost to fix a bug increases by an order of magnitude as a project progresses from one milestone to the next. Bugs found before simulation obviously have the lowest cost. Bugs found at block or subsystem simulation are generally easier to debug and incur a lower cost to fix versus bugs found at high levels of integration—such as chip- and system-level simulation. Bugs found during post-silicon validation might require a new spin of the chip, while bugs found after product release can be devastating, costing millions of dollars to fix.

Years ago, while conducting an assessment on a project team trying to improve their processes, I learned that a simple bug had escape through the project’s verification process and resulted in a  respin. I refer to this as a simple bug since it could have been easily caught by running a static linting tool. The interesting fact related to this particular bug was that the project team was fairly mature in its verification processes—having adopted constrained-random and coverage-driven verification approaches.

Now, don’t misunderstand what I’m saying—I’m certainly not claiming that you only need static linting to solve all your verification challenges. The same could be said for any single verification solution—after all, verification is an exponential problem. However, there are a few valuable lessons in the simple bug example I just gave. That is, the longer a bug goes undetected, the more expensive it is to fix—and that multiple verification solutions are required to minimize risk for today’s complex designs.

One interesting verification solution that has emerged recently uses formal verification technology to automatically perform a set of design checks for a common set of RTL problems. The key point here is that the user does not need to be an expert with formal technology. This aligns well with my philosophy that any solution that is easy to use and finds bugs as early as possible within a verification flow is worth investigating. What’s interesting about this verification solution is that it can verify a class of problems that cannot be found using static linting tools as well as a class of problems that cannot be found with traditional four-state RTL simulation.

If you are interested in learning more about this verification solution, I would like to invite you to check out the web seminar “Questa Formal’s AutoCheck – The Push-Button Way to Find Bugs,” which is part of our free Transforming Verification On Demand Series of webseminars.

Instant Replay for Debugging SoC Level Simulations

December 13th, 2011, by | Permalink | 1 Comment

Instant Replay Offers Multiple Views at Any Speed

If you’ve watched any professional sporting event on television lately, you’ve seen the pressure put on referees and umpires.  They have to make split-second decisions in real-time, having viewed ultra-high-speed action just a single time.  But watching at home on television, we get the luxury of viewing multiple replays of events in question in high-definition super-slow-motion, one frame at a time, and even in reverse.  We also get to see many different views of these controversial events, from the front, the back, the side, up close, or far away.  Sometimes it seems there must be twenty different cameras at every sporting event.

Wouldn’t it nice if you could apply this same principle to your SoC level simulations?  What if you had instant replay from multiple viewing angles in your functional verification toolbox?  It turns out that such a technology indeed exists, and it’s called “Codelink Replay”.

Codelink Replay enables verification engineers to use instant replay with multiple viewing angles to quickly and accurately debug even the most complex SoC level simulation failures.  This is becoming increasingly important, as we see in Harry Foster’s blog series about the 2010 Wilson Research Group Functional Verification Study that over half of all new design starts now contain multiple embedded processors.  If you’re responsible for verifying a design with multiple embedded cores such as ARM’s new Cortex A15 and Cortex A7 processors, this technology will have a dramatic impact for you.

Multi-Core SoC Design Verification

Multi-core designs present a whole new level of verification challenges.  Achieving functional coverage of your IP blocks at the RTL level has become merely a pre-requisite now – as they say “necessary but not sufficient”.  Welcome to the world of SoC level verification, where you use your design’s software as a testbench.  After all, since a testbench’s role is to mimic the design’s target environment, so as to test its functionality, how better to accomplish this than to execute the design’s software against its hardware, albeit during simulation?

Some verification teams have already dabbled in this world.   Perhaps you’ve written a handful of tests in C or assembly code, loaded them into memory, initialized your processor, and executed them.  This is indeed the best way to verify SoC level functionality including power optimization management, clocking domain control, bus traffic arbitration schemes, driver-to-peripheral compatibility, and more, as none of these aspects of an SoC design can be appropriately verified at the RTL IP block level.

However, imagine running a software testbench program only to see that the processor stopped executing code two hours into the simulation.  What do you do next?  Debugging “software as a testbench” simulation can be daunting.  Especially when the software developers say “the software is good”, and the hardware designers say “the hardware is fine”.  Until recently, you could count on weeks to debug these types of failures.  And the problem is compounded with today’s SoC designs with multiple processors running software test programs from memory.

This is where Codelink Replay comes in.  It enables you to replay your simulation in slow motion or fast forward, while observing many different views including hardware views (waveforms, CPU register values, program counter, call stack, bus transactions, and four-state logic) and software views (memory, source code, decompiled code, variable values, and output) – all remaining in perfect synchrony, whether you’re playing forward or backward, single-step, slow-motion, or fast speed.  So when your simulation fails, just start at that point in time, and replay backwards to the root of the problem.  It’s non-invasive.  It doesn’t require any modifications to your design or to your tests.

Debugging SoC Designs Quickly and Accurately

So if you’re under pressure to make fast and accurate decisions when your SoC level tests fail, you can relate to the challenges faced by professional sports referees and umpires.  But with Codelink Replay, you can be assured that there are about 20 different virtual “cameras” tracing and logging your processors during simulation, giving you the same instant replay benefit we get when we watch sporting events on television.  If you’re interested to learn more about this new technology, check out the web seminar at the URL below, that introduces Codelink Replay, and shows how it supports the entire ARM family of processors, including even the latest Cortex A-Series, Cortex R-Series, and Cortex M-Series.

http://www.mentor.com/products/fv/multimedia/verifying-complex-soc-designs-with-questa-codelink

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2011 IEEE Design Automation Standards Awards

December 5th, 2011, by | Permalink | 1 Comment

The DASC Participates in IEEE Standards Association Gala Event

The IEEE Computer Society Design Automation Standards Committee (DASC) participated in the annual IEEE Standards Association (SA) Award ceremony held in New Brunswick, NJ USA  on 4 December 2011.  Hundreds met to recognize the work of thousands who volunteer daily to develop standards and to honor the few who are exceptional examples.

The DASC recognized Larry Saunders as its “Ron Waxman Design Automation Standards Committee Meritorious Service Award” recipient.  Larry was recognized “for pioneering the standardization of VHDL that fundamentally changed the electronic system design process.”

As someone who has worked with Larry on and off over the years to promote the use of VHDL, I know firsthand he is very deserving of this recognition and it was a pleasure to be present as he, one of the renowned VHDL fathers, was given this award.  Yatin Trivedi, vice-chair of the DASC and director of standards at Synopsys gave a glowing tribute to Larry, not just from his DASC leadership role, but as a colleague, friend and mentor.

Pearl & Ron Waxman, myself, Larry Saunders, April Mitchell, Yatin Trevidi and Karen Bartleson from the DASC pose for a photo after the ceremony.

In addition to the “Ron Waxman” award, the IEEE-SA Working Group Chair Awards were also officially recognized.  From the DASC, two of the working groups completed standards development and published their work and a few members of each of those groups were given Working Group Chair awards.

1076.1.1™-2010 IEEE Standard for VHDL Analog and Mixed-Signal Extensions – Packages for Multiple Energy Domain Support
Tom Alderton, Peter J. Ashendon, Ernst Christen, David W. Smith

1647™-2011 IEEE Standard for the Functional Verification Language e
Mike Bartley, Darren Galpin, Amy Witherow

Yatin’s citation for the Ron Waxman Award, Ron’s additional background on Larry’s contributions and Larry’s acceptance video can be seen below.  The microphone was a bit away from the speakers and it was recorded at some distance from the speakers so the sound may be a bit hard to hear unless you use headphones.  But for those who were not there and might like to see it, it is offered for you.

Larry Saunders Accepts DASC Ron Waxman Meritorious Service Award

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Overridden with Overrides

November 22nd, 2011, by | Permalink | 1 Comment

The word override is heavily overloaded in object oriented programming. This concept can make object-oriented programming very difficult to understand. Ironically, the very concept of object-oriented programming came from a simulation language called “Simula” in the 1960′s. Both Verilog and C++ are descendants of this language, but took different paths along the way to represent objects.

In Verilog, we override the value of a parameter. We can override that value with an expression that could reference another parameter. An override is really a fixed assignment at elaboration, before simulation time begins. Unfortunately, the words override and overwrite sound so similar in English that people often use them interchangeable; overwrite would have been a better choice of words for this concpet in the LRM.

module top;
 parameter ADDR = 5;
 bot #(.ADDR(ADDR)) b();
 endmodule
module bot #(parameter  ADDR = 7);
endmodule

In the example above, there are two parameters, top.ADDR and top.b.ADDR, and the value of top.ADD is assigned to top.b.ADDR, which is 5. The fact that both parameters are named ADDR is not important. I could have used address in top, and then instantiated bot with the assignment

bot #(.ADDR(address)) b();

In SystemVerilog, when we talk about inheritance and overriding a parameter, variable or method in an extended class, we are adding a new identifier with the same name that hides the parameter, variable or method declared in the base class in name only.

class A;
 localparam ADDR = 5;
 localparam DATA = 6;
 function void printA;
  $display(ADDR,, DATA); // displays 5 6
 endfunction
endclass
class B extends A;
 localparam DATA = 7;
 function void printB;
  $display(ADDR,, DATA); // displays 5 7
 endfunction
endclass

When we call printB(), it displays DATA as 7 not because we have overridden the value of class A’s DATA, but we have hidden it by defining another DATA with the same name as the parameter in class B. Calling printA() still displays DATA as 6. So in this case we say that inheritance has overridden the name DATA by hiding it with a new symbols with the same name. So with inheritance, it is important that the name be the same when overriding. You could even override a parameter with a function if you wanted to. Things can get complex quickly when you combine the concepts from a Verilog parameter override with a SystemVerilog inheritance override together in the same class.

class A #(parameter int ADDR);
 localparam DATA = 6;
 function void printA;
  $display(ADDR,, DATA); // displays 5 6
 endfunction
endclass
class B #(int address=5) extends A #(.ADDR(address));
 function int DATA;
  return 7;
 endfunction
 function void printB;
 $display(ADDR,, DATA); // displays 5 7
 endfunction
endclass
module top;
 B#() b;
 initial begin
 b = new();
 b.printA();
 b.printB();
 end
endmodule

In this example above, the value of parameter ADDR in class A is overridden with the value of parameter address in class B. The parameter DATA in class A is overridden with the function DATA of the same namein class B.

A few other general notes about parameters in in the example above. The keyword parameteris optional when you are declaring them inside the header of the module or class as I have done with the parameter address in class B. The default value of a parameter is optional as I have omitted with ADDR in class A. This means that whenever class A is referenced, a parameter override is required. Class B does not require an override; I have specified B#() b; to show my intent that I wanted the default parameter values for B and not that I forgot about them.

Take the time to understand that last example and you will be well on your way to understanding parameterized classes in SystemVerilog.

Some more resources are available here:

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Getting started with the UVM – Using the Register Modeling package

November 11th, 2011, by | Permalink | 1 Comment

Adopting SystemVerilog can be challenging to some, and learning the UVM at the same time might seem overwhelming. There is no getting over the fact that if you are going to develop any reasonably sized testbench in SystemVerilog, you need to learn how to declare and construct a class. You also need to learn a few Object-Oriented programming principles so you can extend a UVM class into something for your particular needs.

Once you lean those principals, adopting the UVM can significantly reduce the amount of time it takes to build your testbench because it provides the infrastructure to handle many of the common tasks used in functional verification today. Just a few examples of some of the features included in the UVM are:

By using a common set of industry standard verification methodology and practices, engineers are given the ability to develop modular, reusable verification IP developed by project teams internal or external to their company. Another benefit of the UVM is that it is extensively documented as well as having a considerable amount of tutorial and example material readily available. Mentor Graphics provides the Verification Academy Cookbook and the Cookbook Recipe of the Month Seminar Series to get you started.

One of the significant features of the UVM that differentiates it from what was lacking in the OVM is its Register Layer (it was so lacking that Mentor back-ported the UVM Register Layer to the OVM for those users not yet able to migrate to the UVM). The compelling use model for the UVM Register Layer is that it abstracts away much of the UVM that one needs to learn as a test writer. You write much of your test as you would in software:

…

spi_rm.ctrl.read(status, read_data, .parent(this));

spi_rm.ctrl.write(status, write_data, .parent(this)); 
…

Here we are issuing read and write commands to the control register of an SPI register model. All of the underlying translations to a specific DUT interface with its specific protocol are handled by Register Layer with configuration information set up by the testbench architect.

Our October Recipe of the Month gives a brief introduction to the UVM Register Layer. Our November Recipe will provide more details on implementing them in your environment.

Dave Rich

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TLM Becomes an IEEE Standard

November 10th, 2011, by | Permalink | 2 Comments

IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support

A significant step forward to address standards for advanced system-on-chip (SoC) designs has taken place by the IEEE.  The IEEE announced the new revision of the SystemC standard, known as IEEE 1666™-2011, has been approved.  While it is a revision of the current SystemC standard, IEEE 1666™-2005, the major new feature added was Transaction-Level Modeling (TLM), which is new to an IEEE standard.

For many years now, the TLM specification and accompanying open source code has been incubating in the Open SystemC Initiative (OSCI).  OSCI’s TLM Working Group has developed the TLM 1.0 and TLM 2.0 specifications, both of which are part of the revised IEEE 1666 standard.  TLM is important to SystemC, but it has also been leveraged outside of it.

We at Mentor Graphics pioneered the use of TLM in SystemVerilog (IEEE 1800™-2009) when our seminal open-source work on the Advanced Verification Methodology (AVM) brought an implementation to the verification community based on SystemVerilog.  This lives on today, as AVM motivated the Open Verification Methodology (OVM), which became the basis for Accellera’s Universal Verification Methodology (UVM).

If you don’t already know what TLM is and how the verification community is using it in OVM and UVM, the Verification Academy has a lot of written material and video training modules that will help you learn how this important new IEEE standard is used from simulation to emulation and has boosted verification productivity.  The “Understanding TLM” module is featured in the Advanced UVM section, so if you are still a novice to UVM, you may wish to start with the Basic material first.  This module is presented by fellow Verification Horizons Blogger, Tom Fitzpatrick and offers subtitles in English, Russian, Japanese and Chinese (Traditional & Simplified) to help drive rapid global adoption.

As we brought TLM into the modern verification methodology practice with a SystemVerilog implementation, it also surfaced that there is an opportunity for the creator of TLM, OSCI, and an adopter of it in UVM, Accellera, to discuss what they could do together.  And as I’ve blogged before, those two organizations announced their intention to unite before the end of 2011, as others have seen the potential when both are brought together.  I expect to see more great ideas come from these two groups when they join forces, just like the TLM work that is now an IEEE standard.

For those who want a copy of the revised IEEE 1666 standard, it is still in final IEEE editorial review as the they do their last formatting.  I will share with you when it is ready to use as well as how to get it and where to find it.

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Worlds Standards Day 2011

October 13th, 2011, by | Permalink | No Comments

Creating Confidence Globally

Today, 14 October 2011, is the day the world celebrates standards.  The leadership of the IEC, ISO and ITU issued a message in support of it that clearly articulates the role standards play in safety, reliability, interoperability, their impact on business efficiency and more.

And from time-to-time, I have had the opportunity to join the celebration the American National Standards Institute (ANSI) in the United States hosted when the international community for electronic design automation specialists would gather in Washington, D.C.  The highlight of the celebration in the United States is the presentation of the “Ronald Brown Standards Leadership Award” and the results from the Worlds Standards Day Paper Competition.

Ron Brown, Commerce Secretary in the United States until his untimely death in a plane crash in Croatia in 1996, is the namesake of the award.  He was an inspiration to promote the role of standardization to eliminate global barriers to trade.  ANSI honors this spirit annually, by naming their award after him.  When this year’s award recipient is announced, they will join a long list of other important people recognized as well.

The winner of the 2011 World Standards Day paper competition will also be announced.  This year, ANSI selected the theme of “Advancing Safety and Sustainability Standards.”  Past year winners and their papers can be found here.  One of my favorite papers was the 1999 paper,  The Yin and Yang of Standards Development. The paper juxtaposed formal standards development against that of consortia.

While I won’t say one is right or wrong, I can say I offer leadership to the international bodies, like IEC, the formal bodies, like the IEEE and consortia like Accellera.  If you have some take on this, I would be more than interested to hear.  For electronic design automation, a good example of respecting the value of each of these is offered by SystemVerilog.  We know that SystemVerilog started as donations from many sources that became an Accellera standard.  After a year of stabilization, it was transferred to the IEEE for further maintenance and updates.  And when the IEEE finished its work, it was offered to the IEC under the IEEE/IEC dual-logo program as an international standard.  At each phase of development, a new level of “confidence” was established for consumers and producers.

This brings me back to this year’s tag line of creating confidence globally.

I would like to see some finality from Accellera to complete its initial Universal Verification Methodology (UVM) commitments.  A large overhang exists given the fact the commitment to close on an update to Phasing remains unsatisfied and incomplete.  Maybe one thing to recognize is we can’t do everything at once and so a little is better than none right now.  Or, maybe even, keeping OVM’s phasing scheme is sufficient and add no phasing extensions.  The lack of finality does not engender nor instill confidence in the global market that UVM should be adopted now.  We need to be doing what we can to create the global confidence that sets the perception UVM is ready to use and adopt now.

While we celebrate Worlds Standards Day 2011, let us think of what we can do to Create Confidence Globally.  And maybe we should focus on UVM.

Note: Click here for information on prior World Standards Day themes.

2010

2009

2008

2007

VHS or Betamax?

October 13th, 2011, by | Permalink | No Comments

Legacy’s Luster Lost

As a follow-on to my last blog, where I shared information about Harry Foster speaking live about the research he has been reporting on the last year and where I noted legacy might hold some back, I was going to finish on some of the work we have done at Mentor Graphics to move forward while trying to keep some of those held back by legacy, whole.

Buy why this title?  For some, there may be no recollection of what VHS or Betamax are.  And if I were to say it is a format used to tape record video, that still might not help given DVD, MP4, etc.  If I were to even say there was once a format war over these two, one could easily shrug one’s shoulder and proclaim they both lost.  And that is true.

What do we record on today?  Precisely, the answer is neither of these for all but an obscure few.  But it was towards the end of this format war I left one area to move to another.  VHS had all but become the format of that area for video rentals, while the area I moved to was evenly split between the two formats.  I had selected Betamax.  I can go into great detail to explain the technical advantages of the format.  But those words are all lost on the market forces that ushered in VHS.  And thanks to continued innovation, these legacy formats have lost their luster.  We have all moved on.

Be Kind – Rewind

As SystemVerilog has become the dominant language standard for verification, the methodology work aggregated in Accellera’s Verification IP Technical Subcommittee (VIP-TSC) where it built the Universal Verification Methodology (UVM).  While UVM leverages SystemVerilog, the market’s move from legacy formats has left some who still use those formats to ask if the industry can be “kind, and rewind” – to still support them.

While Accellera’s UVM has been open to bring the dogma of all market participants together to create a single coherent standard, that has not met with total satisfaction of legacy users.  What now appears to be more liked by them is a wholesale translation of UVM in SystemVerilog to legacy languages.  What’s the value in that?  Does one gain greater productivity from this?

Accellera hopes to bridge this divide with a return to its first phase of verification IP interoperability work to suggest additional ways to interoperate.  For up-to-the-minute information on this, I suggest you get involved with the group.  Full information about the group is only available in the membership area – and everyone is invited to be an observing member.  But we should expect Accellera to talk about better bridges to those formats important to those sitting around the standardization table.

Fast Forward

But I still come back to the question about what’s the value in this. It is time to move forward or be stuck in the past? The format is not the value; the algorithms to do better and faster verification are.  To that end, for the users of the e language, Mentor Graphics has extended its Intelligent Testbench Automation (iTBA) technology to work in an e environment.

Many UVM (and OVM) users have found they have been able to achieve their coverage goals 10x to 100x faster than before with this innovative technology.  And it  is now readily available to the 10-15% who still use e.  For more information about leveraging iTBA, you can visit the Verification Academy where one of the new modules that was added in the iTBA section, titled Integrating iTBA into an ‘e’ Environment, is ready for viewing and explains how this is done.  [Note: Registration is required to view the module and certain restrictions apply.]  This module describes integrating Intelligent Testbench Automation into an e environment, re-using existing eVCs, and achieving functional coverage >10X faster.

While legacy language users may fret about their preferred language, the market has already spoken.  Maybe it is time to explore how advanced verification algorithms can be back ported to support legacy to ease the transition.  After all, its not the language, it’s the algorithms.  Go online and see what the advance algorithms can offer you.  Or, join us next week in San Jose, CA at the Verification Seminar.

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Verification Issues Take Center Stage

October 5th, 2011, by | Permalink | 1 Comment

Is Legacy Holding You Back?

Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on the pressing SoC verification issues as he highlights recent research he has been reporting on in his numerous blogs. The first event will be held in San Jose, CA USA (18 October 2011) and the second event will be held in Reading, UK (15 November 2011).

Harry has been reporting on the 2010 Wilson Research Group Functional Verification Study that has shown a rapid market move towards the broadly supported SystemVerilog (IEEE 1800) language standard and ubiquitous support of the OVM/UVM methodologies. While humans have a general disdain for change, human nature also seems to wait to respond to the “crowd effect” to make a change. It appears the market is in the throes of this strain as the market moves in a direction leaving legacy behind.

To learn firsthand from Harry, I recommend attending two upcoming events where he will speak:

Date: 18 October 2011 (Tuesday)
Event: Design & Verification in the SoC Era
Location: DoubleTree – San Jose, CA USA
Website: http://www.mentor.com/events/verification/
Cost: Free; registration restrictions apply

Date: 15 November 2011 (Tuesday)
Event: Verification Futures: The Next Five Years
Location: Hilton Hotel, Reading, UK
Website: http://verificationfutures2011.eventbrite.com/
Cost: Free

Legacy set for replacement?

Have you ever noticed that one restaurant alone may get little traffic, but if there are many restaurants clustered together, they garner much greater traffic than going it alone? The crowd effect demonstrates its power and user benefit with choice and bounty. After DVCon 2011, I blogged about Wally Rhines’ keynote address and pointed to one slide that showed SystemVerilog is the clear language winner and pointed to another slide that showed OVM/UVM, built on top of SystemVerilog, as the clear methodology winner.

This has impact on legacy. And those with entrenched legacy may find it hard to adopt market driven standards practice quickly. This is to be expected.

When Accellera began its Verification IP Technical Subcommittee (VIP-TSC), I argued that the first step is to preserve legacy investment and offer a path to reuse that which has proven valuable in the past. The vote to move in this direction was close with consumer input saying all efforts should focus on a single industry supported base class library and standard. My point was we could build it, but if there was no path from where consumers were, there would be limited uptake. In a short time, a proof that OVM and VMM could interoperate demonstrated that we knew how to do this. It also gave hope that other proprietary and single-supplier solutions could take this work and adapt it for their paths forward.

With that finished, the Accellera VIP-TSC set to create the Universal Verification Methodology (UVM) standard. This has now been completed, short of finishing one commitment to expand the Phasing scheme and address a few lingering issues. While Accellera could focus on completing this work, users and owners of legacy verification languages and proprietary environments have come to realize a startling truth: the market has moved away from them. And, proprietary and single-solution suppliers have offered little in terms of paths forward. They now look for Accellera to address legacy preservation requirements and do it for them.

While this was to be expected, their shock has exposed the fact that more work could have been done on building the bridges to legacy’s past in the initial phase rather than now when the market demands time and focus on its adopted standards practice instead.

Why bring all this up?

We now find the Accellera VIP-TSC has a bifurcated focus. Part of the focus is to complete the content promises for UVM 1.0 and the other is to preserve legacy investment. But can Accellera overcome the crowd effect? The crowd effect, after all, has taken hold. In terms of product choice, legacy offers one product from a single supplier to SystemVerilog’s multiple competitive suppliers. When it comes to bounty, the availability of legacy verification IP has fewer and fewer sources while OVM/UVM offer an expanding bounty.

In the face of this rapid market move, one can expect single solution suppliers will extol features of their solution over the market’s choice. Users faced with the grim prospect of having to adapt to market changes will praise the past in hopes others will depart from the crowd. I am at a loss to think of a time when actions like this have worked to change the market. Maybe someone knows of examples and can share them.

In fact, I was a user who praised the technical benefits of one format over another. I made further investments in it. I even moved to a new job in a new area to find the community I moved to seemed to favor my selected format equally with what was to be the market winner. In time, in very short time, even my new community gave way to the market and the crowd. Can you guess what that format was?

I will share the details this with you next week when I discuss how one might actually bring value to legacy while allowing the market to continue its move forward. In the meantime, if you are close to the San Jose, CA or Reading, UK events, I suggest you register to attend.

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This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.

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