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In my previous blog, I introduced the 2012 Wilson Research Group Functional Verification Study (click here). The objective of my previous blog was to provide background on this large, worldwide industry study. I will present the key findings from this study in a set of upcoming blogs.
This blog begins the process of revealing the 2012 Wilson Research Group study findings by first focusing on current design trends. Let’s begin by examining process geometry adoption trends, as shown in Figure 1. Here, you will see trend comparisons between the 2007 Far West Research study (gray line), the 2010 Wilson Research Group study (blue line), and the 2012 Wilson Research Group study (green line).
Figure 1. Process geometry trends
Worldwide, the median process geometry size from the 2007 Far West Research study was about 90nm, while the median process geometry size is about 65nm in 2010. Today, the mean process geometry size for a typical project is about 45nm—although you can see that over a third of projects today are designing below 32nm.
In addition to the industry moving to smaller process geometries, the industry is also moving to larger design sizes as measured in number of gates of logic and datapath, excluding memories (which should not be a surprise). Figure 2 compares design sizes from the 2002 Collett study (dark blue line), the 2007 Far West Research study (gray line), the 2010 Wilson Research Group study (light blue line), and the 2012 Wilson Research Group study (green line).
Figure 2. Number of gates of logic and datapath trends, excluding memories
The study revealed that about a third of the non-FPGA designs today are less than 5M gates, while a third range in size between 5M to 20M gates, and about a third of all designs are larger than 20M gates.
It’s important to note here that the data on the mean design size trends does not reflect volume in terms of semiconductor production. For example, you could have fewer projects designing at a small geometry, yet they have higher volume in terms of production.
In Figure 3, I show the mean design size trends between the 2002 Collett study (dark blue line), the 2007 Far West Research study (gray line), the 2010 Wilson Research Group study (light blue line), and the 2012 Wilson Research Group study (green line). Obviously, gate counts have increased over the years, yet a significant number of designs continue to be developed with smaller (and larger) gate counts as indicated by the mean calculation. Another observation is that, as you would expect, the mean gate count trend is essentially following Moore’s law.
Figure 3. Mean design size trends
Figure 4 presents the current design implementation trends for non-FPGAs as identified by the survey participants.
Figure 4. Non-FPGA current design implementation trends
The data in Figure 4 presents trends in design implementation approaches for non-FPGA designs, ranging from the 2002 Collett study (dark blue bar), the 2004 Collet study (dark green bar), the 2007 Far West Research study (gray bar), the 2010 Wilson Research Group study (blue bar), and the 2012 Wilson Research Group study (green bar). Note that the study seems to indicate that there is a downward trend in standard cell design implementation.
Figure 5. FPGA design implementation trends
For the 2012 study, we decided that we wanted to get a sense of the percentage of FPGA projects that target the very complex programmable SoC FPGAs that have recently emerged, which is shown in Figure 5. Examples of these programmable SoC FPGAs include: Xilinx’s Zynq, Altera’s Arria/Cydone, and Microsemi’s SmarFusion.
In my next blog (click here), I’ll continue discussing current design trends, focusing specifically on embedded processors, power, and clock domains.
A unique concept most beginners have trouble grasping about the Verilog, and now the SystemVerilog, Hardware Description Language (HDL) is the difference between wire’s (networks) and reg‘s (variables). This concept is something that every experienced RTL designer should be familiar with, but there are now many verification engineers with no prior Verilog experience trying to pick up SystemVerilog for their testbench. Verification methodology courses tend to concentrate on the Object-Oriented programming aspects of testbench design, but do not cover this topic thinking that it is for designers only. Not true. If you have to communicate with a DUT then you need to understand the difference between wire’s and reg’s (nets and variables).
Anyone tasked with having to design or verify a piece of hardware should have some basic programming skills and understand the concept of a variable. If not, you had better stop right here and brush up on some programming basics. The key concept that you need to take away from programming is that you write a value into a variable and that value is saved until the next assignment to that variable. This concept is referred to as a procedural assignment which is part of executing an ordered set of statements. An HDL may add some notion of time in between assignments and other statements. The last assignment determines the current value of the variable.
|Combinatorial Logic||Sequential Logic|
Initially, Verilog used the keyword reg to declare variables representing sequential hardware registers. Eventually, synthesis tools began to use reg to represent both sequential and combinational hardware as shown above and the Verilog documentation was changed to say that reg is just what is used to declare a variable. SystemVerilog renamed reg to logic to avoid confusion with a register – it is just a data type (specifically reg is a 1-bit, 4-state data type). However people get confused because of all the old material that refers to reg. Just forget about it and use logic from now on.
Another distinctive characteristic of an HDL is that it models massive amounts of parallel processes. At the lowest level of digital design, every primitive gate (AND, OR, DFF) is an independent concurrent process. Modules are containers representing processes modeled at different levels of abstraction. Groups of primitives and modules pass values to each other via networks of signals. In Verilog, a wire declaration represents a network (net) of connections with each connection either driving a value or responding to the resolved value being driven on the net. The output of each of these concurrent processes drives a net in what is called a continuous assignment because the process continually updates the value it wants to drive on the net. There are various ways to declare a continuous assignment, all of which represent permanent behaviors:
wire A, B, C;
assign A = B| C; // continuous assignment construct.
or(A,B,C); // gate-level instance terminal connection
mymodule m1(A,B,C); // module instance port connection
Although these are all different forms of continuous assignment constructs, none of them directly assign a value to the net like a procedural assignment would. All of the values being concurrently driven onto the net are passed into a built-in resolution function. The result of that resolution function is based on the strengths of each driver representing the hardware technology in use. For example, an interrupt request signal might use the wired-or (wor) kind of net to indicate that at least one device is driving a ’1′, otherwise it will resolve to a ’0′. Some signals will have weaker pull-up/down resistors that will be overridden by the values of a stronger driver. Most technologies do not allow driving different values on the same net and the net will resolve to an unknown ‘x’ when that happens. In this case only one driver is actively assigning a ’0′ or ’1′ and the other drivers are effectively turned off by driving a high-impedance or ‘z’ state. The consequence of this is that a bi-directional port must be modeled using a net in order to have multiple drivers on either side of the port.
See my recent DVCon paper for an example of modeling bidirectional signals along with other tips for connecting the Testbench to your DUT.
It turns out that the vast majority of nets in a design will only have a single driver, so no strength information or resolution function is needed. SystemVerilog added a feature that allows a single continuous assignment to drive a variable. The expression driving the continuous assignment is assigned to the variable every time the expression changes its value. As soon as you have more than one driver or need strength information, you must go back to using a net. You cannot mix procedural and continuous assignments to the same variable. The reason for that restriction is that there is no way to resolve the “last write wins” semantics of a procedural assignment with a driver that wants to continually assign the variable (i.e. when is the last write finished and the continuous assignment supposed to take over?).
In summary, you should now be using logic for 4-state variables (or bit for 2-state variables) to represent all of your single drive signals. Any signal with more or the potential for more than one driver should be declared as a wire.
Power Aware Verification Course Modules Released
I guess I could continue the puns on the low-power theme as a few readers may get a charge out of it. And there is a reason I seem to gravitate to puns from the start. The first chair of the IEEE 1801 committee and I exchanged puns one time that resulted in him shipping me a Pun DVD that recorded a pun contest in which one person and another tried to out do the other when it came to puns. So it is understandable why the topic of low power standards takes me back to these fun exchanges.
But low power design and verification is a serious issue that design teams continue to grapple. To take advantage of emerging support of the new low power standard takes time and energy on part of practicing engineers and design teams. More information on what IEEE Std. 1801™-2013 (Unified Power Format) is and how you can use it is needed.
Back in March 2013 I blogged that the revised IEEE low power standard had been approved. I also mentioned there would be a short wait until the standard itself was published. And, indeed, we continue to wait for the final editing of the standard. I shared a link to a short article on the content of the standard, but more information is needed.
To address this need, the Verification Academy has added a course on Power Aware Verification. There are six (6) sessions that will introduce you to power aware verification, UPF and walk you through an example to illustrate the use of the standard in more detail in about 1.5 hours. In order to access the course material you will need to be a “full access” registrant of Verification Academy. There is no fee for this, but restrictions apply.
In addition to watching the video course sessions online, you can also download the presentations and MP4 videos of the course for offline viewing.
The six course sessions are:
- Introduction to Power Aware Verification (9 minutes)
- Overview of UPF (13 minutes)
- Getting Started with UPF (23 minutes)
- A Simple UPF Example (17 minutes)
- UPF 2.0 Enhancements (11 minutes)
- Using Supply Set (18 minutes)
We are interested to get your feedback on the Power Aware Verification course and learn what additional sessions you think would help you get AMP’ed up to further the need to conserve energy. Let us know!
This is the first in a series of blogs that presents the results from the 2012 Wilson Research Group Functional Verification Study.
In 2002 and 2004, Ron Collett International, Inc. conducted its well known ASIC/IC functional verification studies, which provided invaluable insight into the state of the electronic industry and its trends in design and verification. However, after the 2004 study, no other industry studies were conducted, which left a void in identifying industry trends.
To address this void, Mentor Graphics commissioned Far West Research to conduct an industry study on functional verification in the fall of 2007. Then in the fall of 2010, Mentor commissioned Wilson Research Group to conduct another functional verification study. Both of these studies were conducted as blind studies to avoid influencing the results. This means that the survey participants did not know that the study was commissioned by Mentor Graphics. In addition, to support trend analysis on the data, both studies followed the same format and questions (when possible) as the original 2002 and 2004 Collett studies.
In the fall of 2012, Mentor Graphics commissioned Wilson Research Group again to conduct a new functional verification study. This study was also a blind study and follows the same format as the Collett, Far West Research, and previous Wilson Research Group studies. The 2012 Wilson Research Group study is one of the largest functional verification studies ever conducted. The overall confidence level of the study was calculated to be 95% with a margin of error of 4.05%.
Unlike the previous Collett and Far West Research studies that were conducted only in North America, both the 2010 and 2012 Wilson Research Group studies were worldwide studies. The regions targeted were:
- North America:Canada,United States
- Asia (minusIndia):China,Korea,Japan,Taiwan
The survey results are compiled both globally and regionally for analysis.
Another difference between the Wilson Research Group and previous industry studies is that both of the Wilson Research Group studies also included FPGA projects. Hence for the first time, we are able to present some emerging trends in the FPGA functional verification space.
Figure 1 shows the percentage makeup of survey participants by their job description. The red bars represents the FPGA participants while the green bars represent the non-FPGA (i.e., IC/ASIC) participants.
Figure 1: Survey participants job title description
Figure 2 shows the percentage makeup of survey participants by company type. Again, the red bars represents the FPGA participants while the green bars represents the non-FPGA (i.e., IC/ASIC) participants.
Figure 2: Survey participants company description
In a future set of blogs, over the course of the next few months, I plan to present the highlights from the 2012 Wilson Research Group study along with my analysis, comments, and obviously, opinions. A few interesting observations emerged from the study, which include:
- FPGA projects are beginning to adopt advanced verification techniques due to increased design complexity.
- The effort spent on verification is increasing.
- The industry is converging on common processes driven by maturing industry standards.
My next blog presents current design trends that were identified by the survey. This will be followed by a set of blogs focused on the functional verification results.
Also, to learn more about the 2012 Wilson Reserach Group study, view my pre-recorded Functional Verification Study web-seminar, which is located out on the Verification Academy website.
Quick links to the 2012 Wilson Research Group Study results (so far…)
- Part 1 – Design Trends
Tags: accellera, Assertion-Based Verification, formal verification, functional coverage, functional verification, IEEE, Simulation, Standards, SystemVerilog, UVM, Verification Academy, Verification Methodology, verilog, vhdl
We’re really excited about the recent Questa 10.2 release, and I’m sure you’ll be just as excited when you check it out. For you UVM-philes out there, we’ve extended our industry-leading UVM Debug features to make your life even easier. I’ll present a quick overview of the new features here, but you’ll really want to get your hands on 10.2 and take a more in-depth look for yourself.
The first thing you’ll notice is that we’ve enhanced to Structure Window (usually located in the upper left of the debugger) to show the class type of each UVM component in your testbench. This will make it easier to know exactly what your factory settings and other configuration settings have yielded as you built your testbench.
One of the most common requests we’ve gotten is to provide a way to see what exactly is happening with the configuration database (uvm_config_db). In the UVM Details window, you can now see the values that are available to the selected component, and by right-clicking you can see who wrote the value and where the write occurred.
In the Stream view of the Details window, you can see all of the transaction streams being recorded by the selected component.
Also, when debugging UVM processes, the Processes Window now includes the hierarchical path to the component that initiated the process.
Lastly, for those of you who may not be GUI-centric, we’ve added a new “uvm” command to the command-line interface in the transcript window (or via “.do” files):
uvm subcommand [args...]
where the “subcommand” lets you choose from a number of options. The default subcommand (and in my opinion, the coolest) is the “call” command, which allows you to call UVM functions directly from the command line. You can even call functions in UVM components by referring to the components via their hierarchical name
uvm call test_top.env1.fab.get_full_name
or via a handle provided by Questa (as seen in the Class Instances window).
There are other useful UVM commands that I won’t go into here, but you should definitely check them out. So, what are you waiting for? To find out more information about Questa with this link: http://www.mentor.com/products/fv/questa/
IEEE 1801™-2013 Enters Pre-Publish Phase
The completion and approval of electronic design automation standards has seemed to be the order of the day for several months now. Added to this list is the IEEE Standards Association (SA) approval of their newly revised low power standard (IEEE 1801™-2013). The IEEE SA’s Review Committee (RevCom) unanimously recommended approval and that was confirmed by the IEEE SA’s Standards Board last week.
If you don’t recognize IEEE 1801, you may also know it as the Unified Power Format (UPF).
As with all the IEEE standards, after approval, they are sent to editorial staff to prepare them for publication. So while you might expect me to suggest you get a copy of the standard, if low power design and verification is important to you, I know you cannot get a copy yet. So I won’t do that. If you do need something, the superseded version from 2009 is the only one available at this moment. I will keep you updated as to when it is published and ready for access to the global design community.
Mentor Graphics’ Erich Marschner and vice chair of the IEEE 1801 working group has published a short article in the DVCon edition of Verification Horizons titled The Evolution of UPF: What’s Next? (Free access; no registration required; 81KB)
Erich gives a good introduction to the new standard, also known as UPF 2.1. He describes that UPF 2.1 is an incremental update of UPF 2.0 and not a major revision. He shares that UPF 2.1 contains a large number of small changes, ranging from subtle refinements of existing commands to improve usability, to new concepts that help ensure accurate modeling of power management effects. His article describes some of the more interesting enhancements and refinements that can be found in the new standard.
Erich also shared that the 1801 working group is composed of more than 16 user and vendor companies with even many more participating in the final ballot. This gives us good confidence in the content of this standard and that the group will be ready to tackle the next issues and emerging requirements to further improve low power design and verification. If you are interested to join in with the IEEE 1801 team, visit here for more information.
DVCon UPF Tutorial
The IEEE 1801 leadership hosted a half day tutorial on the new standard in late February at DVCon. For those who registered for the conference, the tutorial presentation is still available online. Unfortunately, the material has not yet been made available to the general public. If you know someone who attended DVCon, and went to the tutorial, you might want to see if you can borrow their copy. The conference did an audio recording and I believe plans are to sync the audio with slides for those who were unable to attend DVCon. Stay tuned for this and I will share information when this becomes available.
As for planning you can do now. The IEEE 1801 team will host a tutorial at DAC on Sunday. I will share more information with you on that once the DAC registration site goes live. Until then, I guess we all have to wait and be patient – and plan our trips to DAC in Austin, TX.
Just wanted to let you all know that the new issue of Verification Horizons is now available. You can get the full edition online at the Verification Academy. Please be sure to check it out. There are a few articles in particular that I’d like to call your attention to.
Using Formal Analysis to “Block and Tackle” by Paul B. Egan of Rockwell Automation is a great case study in how apply formal to reduce verification time at both the block and chip level by plugging coverage holes missed by simulation. In the article, Paul describes a straightforward three-step process to add formal analysis to your verification flow.
In Bringing Verification and Validation under One Umbrella my colleagues Hemant Sharma and Hans van der Schoot present a unified flow for RTL verification and pre-silicon validation of hardware/software integration by reusing your transaction-level testbench from simulation to emulation.
Be sure the check out The Evolution of UPF: What’s Next? by Erich Marschner. Erich is the chair of the IEEE 1801 committee, which just released UPF 2.1, so there is no one better to explain the new features in this latest release. You can also read about the evolution of features in UPF from 1.0 to 2.1 in a previous issue of Horizons here.
Our friends at CVC list the Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features, and Mark Litterick of Verilab (and recent Best Paper winner at DVCon 2013 – congratulations!) shares his experiences of OVM-to-UVM migration in OVM to UVM Migration, or “There and Back Again: A Consultant’s Tale.”
We’re already working on our DAC edition of Verification Horizons, so if you’d like to submit an article, we’d love to have you.
Today at this week’s DVCon 2013 conference, the IEEE Standards Association (IEEE-SA) and Accellera Systems Initiative (Accellera) have jointly announced the public availability of the IEEE 1800 SystemVerilog Language Reference Manual at no charge through the IEEE Get Program.
As I posted a few weeks ago, the 1800-2012 is not a major revision of the standard, but does contain a few enhancements that will be of interest to design and verification engineers alike. However, providing the standard as freely available download is major news.
Even though the relative cost of the LRM was minor compared to the cost of most projects utilizing the standard, there seemed to be a barrier in most engineer’s minds in justifying the expense. So most just continued to use the last freely available SystemVerilog 3.1a LRM, which was 9 years old and very obsolete for such a rapidly changing technology.
Download the standard now – at no charge!
The latest update to the SystemVerilog standard is now ready for download. It joins other EDA standards, like SystemC in the IEEE Get™ program that grants public access to view and download current individual standards at no charge as a PDF. (If you wish to have an older, superseded and withdrawn version of the standard or if you wish to have a printed copy or have it in a CD-ROM format, you can purchase older and alternate formats from IEEE for a fee.)
Over the years Accellera came to understand that many people continued to use the freely available version that seeded the initial IEEE 1800 SystemVerilog standard. Since it is significantly out of date, Accellera collaborated with the IEEE Standards Association to ensure the latest version of the SystemVerilog standard would be freely available in electronic form to all whom wish to download it. Accellera now hopes all those old 3.1a versions that everyone has and uses can now be placed in the archives.
The new version of standard should be used by the UVM (Universal Verification Methodology) community as the definitive specification of the SystemVerilog standard upon which UVM is built. It goes very well with the UVM Cookbook and the Coverage Cookbook.
From Mentor’s perspective, it also makes a good companion to the Questa verification platform and complements our latest product update in which we announced support for the IEEE 1800-2012 SystemVerilog standard among other things.
If you have not done so already, download your copy now by clicking here.
Learn about new standards, industry surveys and trends
This year’s DVCon is set and if you have not yet registered, you can do it now – or just show up! If you want to secure seating at some of the Monday tutorial events, I strongly encourage pre-registration to ensure you can secure a seat. And if you just want to see the exhibits and chat with suppliers, that’s free.
The IEEE low power format is set to close on its current round standardization shortly and DVCon is a great place to learn all about it from the experts. Harry Foster will update the DVCon attendees on design and verification trends over lunch on Tuesday and later that afternoon, Mentor CEO, Wally Rhines will offer this year’s DVCon keynote. His keynotes are always insightful and entertaining. And if you want to catch me, you can find me with the Mentor staff at the Mentor exhibit booth. Or just follow @dennisbrophy on Twitter and I will share info on paper presentations and other happenings. For more details on the events mentioned above, see below. For more information DVCon in general, visit the website at www.dvcon.org.
Monday | February 25th | 1:30pm – 4:30 | Fir Ballroom
Low Power Design, Verification, and Implementation with IEEE 1801™ UPF™
The past few years, the IEEE P1801™ (Unified Low Power – UPF) Working Group has been busy working on an update to the industry’s standard for low power design, verification and implementation. Accellera has brought together experts from many EDA tool suppliers and users for this tutorial. Attendees can expect to gain a detailed understanding of of the IEEE standard (concepts, terminology & features) as well as an understanding of the practical aspects to apply UPF in real world flows.
The following experts will be help you learn about the new standard – and will be available to interact with at the conclusion of the tutorial.
Tuesday | February 26th | 11:30am – 12:45pm | Pine/Cedar Ballroom
The Changing Landscape in Functional Verification: Industry Trends, Challenges, and Solutions
Presented by Harry Foster
Mentor Graphics invites you to join us for lunch—where we will present, for the first time publicly, highlights from this year’s Wilson Research Group Functional Verification Study. Be the first on your block to learn the latest verification trends, challenges, and solutions.
Learn more, then register.
Tuesday | February 26th | 3:30pm – 4:30pm | Oak/Fir Ballroom
Speaker: Wally Rhines, Chairman and CEO of Mentor Graphics
As a thought provoking, timely, and informative presentation, this keynote session will focus on functional verification trends and the accelerated adoption of advanced functional verification technologies, methodologies and languages.
Learn more, then register.
Tuesday & Wednesday (February 26th & 27th)
3:30pm – 6:30pm
I look forward to meet up with those who attend DVCon. You can catch me at or around the Mentor booth for the last three hours of the conference.
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- Even More UVM Debug in Questa 10.2
- IEEE Approves New Low Power Standard
- May 2013 (2)
- April 2013 (2)
- March 2013 (2)
- February 2013 (5)
- January 2013 (1)
- December 2012 (1)
- November 2012 (1)
- October 2012 (4)
- September 2012 (1)
- August 2012 (1)
- July 2012 (6)
- June 2012 (1)
- May 2012 (3)
- March 2012 (1)
- February 2012 (6)
- January 2012 (2)
- December 2011 (2)
- November 2011 (2)
- October 2011 (3)
- September 2011 (1)
- July 2011 (3)
- June 2011 (6)
- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
- May 2011 (2)
- April 2011 (7)
- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
- March 2011 (5)
- February 2011 (4)
- January 2011 (1)
- December 2010 (2)
- October 2010 (3)
- September 2010 (4)
- August 2010 (1)
- July 2010 (3)
- June 2010 (9)
- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
- February 2010 (5)
- January 2010 (5)
- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
- September 2009 (2)
- July 2009 (1)
- May 2009 (1)