Tom Hausherr's Blog

New component package technology and CAD library standards.

14 January, 2011
CAD Library Zero Component Orientations
 
In 2005 IPC and IEC (International Electrotechnical Commission) established a joint standard for land pattern geometries (IPC-7351/IEC 61188-5-1). In order to maintain a consistent method where these two important standards describe the component mechanical outlines, and their respective mounting platforms, a single concept must be developed that takes into account various factors within the global community.

The land pattern standards clearly define all the properties necessary for standardization and acceptability of a “One World CAD Library”. The main objective in defining a one world CAD library is to achieve the highest level of “Electronic Product Development Automation”. This encompasses all the processes involved from engineering to PCB layout to fabrication, assembly and test. The data format standards need this type of consistency in order to meet the efficiency that electronic data transfer can bring to the industry.

Many large firms have spent millions of dollars creating and implementing their own unique standards for their own “Electronic Product Development Automation”. These standards are proprietary to each firm and are not openly shared with the rest of the industry. This has resulted in massive duplication of effort costing the industry millions of man hours in waste and creating industry chaos and global non-standardization.

The Land pattern standards (both IPC-7351 and IEC 61188-5-1) put an end to the “Proprietary Intellectual Property” and introduce a world standard so every electronics firm can benefit from Electronic Product Development Automation. The data format standards (IPC-2581 and IEC 61182-2) are an open database XML software code that is neutral to all the various CAD ASCII formats. For true machine automation to exist, the world desperately needs a neutral CAD database format that all PCB manufacturing machines can read.

One of the factors in global standardization is that of establishing a CAD component description and land pattern standard that adopts a fixed Zero Component Orientation so that all CAD images are built with the same rotation for the purpose of assembly machine automation. The IPC-7351 indicates that in the CAD library, all pin 1 locations are in the upper left corner for multiple pin components and pin 1 on left for 2-pin components. Figure 1 represents IPC-7351 default and IEC 61188-7 “Level A” zero component orientation.

Figure 1 - IPC-7351 Pin 1 Upper Left (IEC 61188-7 Level A)

Figure 1 - IPC-7351 Zero Orientation with Pin 1 Upper Left (IEC 61188-7 Level A)

 In May 2009, IEC land pattern committee voted and approved a new Level B Zero Component Orientation and redefined the IPC-7351 Zero Orientation as Level A. The new IEC 61188-7 defines Zero Component Orientation pin 1 locations in the bottom left corner except 2-pin components Pin 1 is on the left side and labeled it “Level B”. Figure 2 represents IEC 61188-7 “Level B” zero component orientation.

Figure 2 – IEC 61188-7 “Level B” Zero Orientation with Pin 1 in Lower Left Corner

Figure 2 – IEC 61188-7 “Level B” Zero Orientation with Pin 1 in Lower Left Corner

  Since the basic rules allow two variations of levels in the description of the CAD system library, it is a mandatory requirement to define which level was used (level A or Level B) for the component descriptions in the data file. This information is a mandatory requirement in the Header of any file that incorporates land patterns using these principles of zero-based orientation. See Figure 3 for the “Level A” zero orientation and machine rotation.

Figure 3 – Example of “Level A” Orientation Concepts

Figure 3 – Example of “Level A” Orientation Concepts

The industry association EIA (Electronics Industry Association) is responsible for component descriptions and tape and reel orientation in the EIA-481-D standard. EIA has tried valiantly to influence the industry by making good standards that describe the component outlines and how they should be positioned in the delivery system to the equipment on the manufacturing floor. Suppliers of parts have either not adhered to the recommendations or have misunderstood the intent and provided their products in different orientations.

Here are the EIA-481-D standard tape and reel pictures (Figures 4 & 5) that illustrate quadrant designations.

Figure 4 – EIA-481-D Quadrant Designations

Figure 4 – EIA-481-D Quadrant Designations

 

Figure 5 – CAD Library Zero Orientation Quadrants

Figure 5 – CAD Library Zero Orientation Quadrants

IPC and IEC use consistent rotations throughout their standard where EIA uses multiple rotation variations

  • IPC-7×51 “Level A” uses Quadrant 2 for Pin 1 Upper Left and Quadrants 2-4 for Upper Center
  • IEC 61188-7 “Level B” uses Quadrant 1 for Pin 1 Lower Left and Quadrants 1-2 for Left Center
  • EIA-481-D uses Quadrant 1 for Pin 1 Lower Left BGA, SOIC, SOP, QFN (rectangle), DIP
  • EIA-481-D uses Quadrant 2 for Pin 1 Upper Left TO-252, TO-263, QFN (square), TSOP
  • EIA-481-D uses Quadrant 3 for Pin 1 Lower Right for all SOT and miniature parts
  • EIA-481-D uses Quadrants 1-2 (Pin 1 Left Center) for PLCC, LCC
  • None of the 3 standards use Quadrant 4 for Pin 1 locations

The main purpose of creating the land pattern standards is to achieve reliable solder joint formation platforms; the reason for developing the data transfer structure is to improve the efficiency with which engineering intelligence is converted to manufacturing reality. Even if the neutral CAD format can drive all the manufacturing machines, it would be meaningless unless the component description standard for CAD land patterns was implemented with some consistency. Zero Component Orientation has a key role in machine automation.

The easiest way to illustrate the 3 world standards is to list every component family and their respective Zero Component Orientation for each standard. The big question is – Which standard will prevail?  

Figure-6 IPC, IEC & EIA Zero Component Orientations

Figure-6 IPC, IEC & EIA Zero Component Orientations

Note: The EIA-481-D rotations marked in Red conflict with both IPC and IEC

Download the complete IPC-7351B Electronic Component Zero Orientation document here – http://www.mentor.com/resources/appnotes/upload/zero-orientation-cad-libaray.pdf

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8 January, 2011

The BGA or Ball Grid Array has been around since the 1980′s but the pin pitch started out with 1.5 mm and then quickly went to 1.27 mm (50 mils) for about 15 years. Then in the late 1990′s, the 1 mm pitch BGA was introduced and every couple years a smaller pin pitch was introduced. Today 0.4 mm pitch BGA’s are in every cell phone and 0.3 mm pitch BGA’s are the next generation. Figure 1 displays the lead type for this component family.

Figure 1

Figure 1

There are 2 types of BGA Ball Leads –

  1. Non-collapsing – this is normally 0.5 mm pitch and smaller, where the Land (pad) is larger than the ball to allow for via-in-pad technology and provide an adequate annular ring. The solder mask can be the same size as the Land. In some cases the Land for fine pitch BGA’s is solder mask defined where the solder mask encroaches slightly over the land. This provides protection for any trace routing between the lands but the most significant benefit is to help secure the Land to the PCB. During cell phone “drop testing”, the BGA solder joint normally holds better than the land to the Prepreg. i.e.: drop tests prove that the non-solder mask land will rip from the PCB before the solder joint breaks. So the solder mask defined land is secured better to the PCB for drop testing.
  2. Collapsing - this is normally 0.65 mm pitch and higher, where the Land (pad) is smaller than the Ball size to allow the Ball to collapse around the sides of the Land. This requires a non-solder mask defined Land where the solder mask must be larger than the Land.

 See Figure 2 for examples of non-collapsing and collapsing BGA balls.

Non-collapsing and Collapsing BGA Balls

Figure 2: Non-collapsing and Collapsing BGA Balls

The BGA Land (pad) size is determined by the ball size as seen below in Table 1 from IPC-7351B land pattern standard. Notice the correlation between the “reduction” and the “land pattern density level”. The 3 density levels change the land size reduction percentage, but they also determine the Placement Courtyard Excess. See Table 3.

Table 1: Land Approximation for Collapsible Solder Balls

Table 1: Land Approximation for Collapsible Solder Balls

Note:  The IPC-7351B LP Calculator Uses this chart for calculations

It is very important to note that IPC prefers the Maximum Material Condition for all BGA Land sizes; they do not use the Nominal Land Diameter, but do use the Maximum Land Variation Diameter (notice the Bold numbers in the Chart “Land Variation” column). Notice that the standard ball sizes are in 0.05 mm increments until the pin pitch hits 0.5 mm and less. However, even though the world standards try to keep BGA balls sizes in 0.05 mm increments, component manufacturer’s sometimes do not adhere to the standard and create BGA ball sizes in 0.01 mm increments, but I have never seen a BGA ball size less than a 0.01 mm increment. Also, the BGA pin pitches are in 0.05 mm increments. As a result, the BGA land (pad) sizes are in 0.05 mm increments including the via fanout padstacks and hole sizes.

IPC-7351B has a 3-Tier BGA formula for Placement Courtyard Excess that uses the BGA ball size to calculate an adequate placement courtyard for BGA rework tools. If the BGA has a large ball size, larger rework equipment is necessary to unsolder the increased solder volume.

With a small ball size, the placement courtyard can be smaller as less heat is then required to unsolder the BGA component for rework.  However, the end user may not plan to rework the BGA if it fails.  In that case, there is no need to have a robust placement courtyard, but a recommended minimum placement courtyard excess is 0.5 mm.

Non-collapsing” ball BGA components

Table 2 below is used for land size calculations for non-collapsing BGA balls.

Table 2: Non-Collapsing BGA Ball Land Calculations

Table 2: Non-Collapsing BGA Ball Land Calculations

It is very important to note that IPC prefers the Maximum Material Condition for all BGA Land Sizes, meaning that the Maximum Land Variation Diameter is used; not the “Nominal Land Diameter”.

Figure 3 is a 0.5 pitch non-collapsing BGA ball. Instead of shrinking, the non-collapsing land size gets larger to handle the solder volume that creates the solder joint. This technology is new to the electronics industry and was created as a solution for lead-free BGA balls and via-in-pad technology as a routing solution for fine pitch BGA components.

Figure 3: Non-Collapsing 0.5 mm pitch BGA

Figure 3: Non-Collapsing 0.5 mm pitch BGA

  • Via-in-Land Technology          Trace/Space & Grid Data
  • BGA Ball Size: 0.15                               Trace Width: 0.075
  • BGA Land Dia: 0.275                          Trace/Trace Space: 0.075
  • Hole Size: 0.15                                       Trace/Via Space: 0.075
  • Thermal Relief Required                   Trace/BGA Land: 0.075
  • Plane Clearance: 0.425                     Routing Grid: 0.05
  • Solder Mask: 1:1 scale                        Part Place Grid: 1

IPC-7351A has a 3-Tier BGA formula for Placement Courtyards that uses the BGA ball size to calculate an adequate placement courtyard for BGA rework tools.

If the BGA has a large ball size, larger rework equipment is necessary to unsolder the large solder volume. With a small ball size, the placement courtyard can be smaller as less heat is then required to unsolder the BGA component for rework.  However, the end user may not plan to rework the BGA if it fails.  In that case, there is no need to have a robust placement courtyard.

Table 3 below represents the 3-Tier scenario and the different placement courtyard excess size determination.

Table 3: BGA Density Levels for Placement Courtyard Size Determination

Table 3: BGA Density Levels for Placement Courtyard Size Determination

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2 December, 2010

Padstacks

Padstack creation is something every CAD tool will eventually have to incorporate because it expedites and optimizes CAD library construction. You can download the IPC-7351B Padstack Naming Convention here – AppNote 10833: IPC-7251 & 7351 Padstack Naming Convention or http://www.mentor.com/products/pcb-system-design/library-tools/lp-wizard/import-docs

The SMT Padstack is easy -

  • Top Land
  • Top Solder Mask
  • Top Paste Mask
  • Top Assembly

Part 7 of this blog explains the Land Calculation for SMT land patterns, so let’s discuss Plated Through-hole calculations in this segment.

The Through-hole (PTH) Padstack is complex -

  • Drill Hole
  • Top Assembly
  • Top Solder Mask
  • Top Land
  • Inner Land
  • Plane Thermal Relief
  • Plane Anti-pad (Clearance)
  • Bottom Land
  • Bottom Solder Mask
  • Bottom Assembly

Here is a picture of a through-hole padstack.

PTH Padstack

PTH Padstack

The PTH padstack creation can be fully automated via the maximum lead diameter.
Round PTH Lead

Round PTH Lead Rectangle PTH Lead

Rectangle PTH Lead

Rectangle PTH Lead

Square PTH Lead

Square PTH Lead

In the IPC-2222 standard there is a hole size calculation chart -
IPC-2222 Table 9-3

IPC-2222 Table 9-3

 Once you calculate the hole size, the minimum annular ring is 0.05 mm.

IPC-2221 Minimum Annular Ring

IPC-2221 Minimum Annular Ring

Next we need to add the IPC-2221 Minimum Fabrication Allowance to the pad size.
IPC-2221 Table 9-1

IPC-2221 Table 9-1

So the Minimum Annular Ring X 2 + Minimum Fabrication Allowance + Maximum Lead + Hole Over Lead = Pad Diameter

Next we need to calculate the Plane Thermal Relief ID, OD and Spoke Width sizes.
Thermal Relief Calculations

Thermal Relief Calculations

The Plane Anti-pad or Plane Clearance is the same size as the Thermal Relief OD (Outside Diameter).
 
In both the SMT and PTH padstack, the IPC recommended Solder Mask and Paste Mask size is 1:1 scale of the Top and Bottom land size. The PCB fabrication shop can automatically oversize (swell) the solder mask to any size they need to insure high yield production per their specific manufacturing capabilities. This is where automation of padstack generation comes in. The entire concept is to generate a padstack that meets the environment class of your design specification.  

The IPC-7251 Through-hole land patterns have the capability of accommodating all three performance classifications.

Producibility Levels: When appropriate this standard will provide three design producibility levels of features, tolerances, measurements, assembly, testing of completion or verification of the manufacturing process that reflect progressive increases in sophistication of tooling, materials or processing and, therefore progressive increases in fabrication cost. These levels are:

  • Level A General Design Producibility – Preferred [Maximum land\lead to hole relationship]
  • Level B Moderate Design Producibility – Standard [Nominal land\lead to hole relationship]
  • Level C High Design Producibility – Reduced [Least land\lead to hole relationship]

The producibility levels are not to be interpreted as a design requirement, but a method of communicating the degree of difficulty of a feature between design and fabrication/assembly facilities. The use of one level for a specific feature does not mean that other features must be of the same level. Selection should always be based on the minimum need, while recognizing that the precision, performance, conductive pattern density, equipment, assembly and testing requirements determine the design producibility level. The numbers listed within the tables of IPC-7251 are to be used as a guide in determining what the level of producibility will be for any feature. The specific requirement for any feature that must be controlled on the end item shall be specified on the master drawing of the printed board or the printed board assembly drawing.

Download the IPC-7251 padstack charts here – AppNote 10835: IPC-7251 Padstack Charts

Density Level A: Maximum Land/Lead to Hole Relationship The ‘maximum’ land pattern conditions have been developed to accommodate the most robust producability of the solder application method. The geometry furnished may provide a wider process window for solder processing. The level A land patterns are usually associated with low component density product applications.

Density Level B: Nominal Land/Lead to Hole RelationshipProducts with a moderate level of component density may consider adapting the ‘median’ land pattern geometry. The median land patterns furnished for all device families will provide a robust solder attachment condition for most soldering processes and should provide a condition suitable for wave, dip, drag or reflow soldering.

Density Level C: Least Land/Lead to Hole RelationshipHigh component density typical of portable and hand-held product applications may consider the ‘minimum’ land pattern geometry variation. Selection of the minimum land pattern geometry may not be suitable for all product use categories.

 

The “Proportional” PTH Padstacks are a mixture combination of all the IPC Levels. Small holes use Level C and medium hole sizes use Level B and large hole sizes use Level A. When a hole size exceeds 2 mm, the Proportional padstack annular ring will incrementally grow with every hole size.  I have used the proportional padstacks for the past 20 years and it is proven technology that works. Its flexible flow is more compliant with the PTH components and their pin pitch density. The main point is that Proportional padstacks meet or exceed the IPC-7251 standard.
 
Download the Proportional padstack chart here – Appnote 10836: Proportional Through-hole Padstacks
 
Note: the “Producibility Levels” are not necessarily related to the IPC Preformance Classifications. i.e.: The IPC-7251 land patterns have the capability of accommodating all three performance classifications.

IPC Performance Classifications: Three general end-product classes have been established to reflect progressive increases in sophistication, functional performance requirements and testing/inspection frequency. It should be recognized that there may be an overlap of equipment between classes.

The end product user has the responsibility for determining the ‘‘Use Category’’ or ‘‘Class’’ to which the product belongs. The contract between user and supplier shall specify the ‘‘Class’’ required and indicate any exceptions or additional requirements to the parameters, where appropriate.

Class 1 General Electronic Products – Includes consumer products, some computer and computer peripherals, and hardware suitable for applications where the major requirement is function of the completed assembly.

Class 2 Dedicated Service Electronic – Products Includes communications equipment, sophisticated business machines, and instruments where high performance and extended life is required, and for which uninterrupted service is desired but not mandatory. Typically the end-use environment would not cause failures.

Class 3 High Reliability Electronic Products – Includes all equipment where continued performance or performance-on-demand is mandatory. Equipment downtime cannot be tolerated, end-use environment may be uncommonly harsh, and the equipment must function when required, such as life support systems and other critical systems.

 

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24 November, 2010

Land Calculations

IPC-7351 for SMT technology defines the rules for creating optimized land pattern CAD library parts using a 3-Tier system – Least (high density), Nominal (controlled environment) and Most (ruggedized & shock resistant). Many PCB designers and CAD Librarians have heard about the IPC-7351B standard, but few people know how they work. The IPC LP Calculator has made life easy for the PCB design industry by automatically generating accurate land pattern data derived from component dimensions. Part 7 of this series will describe the basic fundamental aspects of defining the optimized land (pad) size for a CAD library part and the mathematical model of the LP Calculator.

Land (Pad) Size and Location:

These 7 factors are used to calculate the optimum Land Size –

  1. Component Body Tolerance 
  2. Component Terminal Tolerance
  3. Fabrication Tolerance
  4. Placement Tolerance
  5. Land Size Round-off
  6. Land Spacing Round-off
  7. Solder Joint Goals for Toe, Heel and Side
IPC-7351 identifies two component body dimensions “A” (body width) & “B” (body length).  The one SMT Component Body Tolerance that affects the land pattern is the minimum and maximum sizes of the component “Lead Span” (the dimension from lead tip to lead tip) dimension “L”. This varies for different component packages. For Gull Wing or J-Lead it’s the distance from outside lead tip to tip. For Chip Resistors or Capacitors it’s the full tolerance of the overall body. The picture below represents the “L” dimension of a Gull Wing lead component.
 
Component Lead Span

Component Lead Span

 

The Component Terminal Tolerance is the size of the metalized area that actually touches the land area. IPC refers to this as the component footprint. The footprint must compensate for the minimum and maximum lead tolerance for the calculation of an optimized Land Size. The component lead footprint is then synchronized with the appropriate land pattern.
Component Terminal Tolerance

Component Terminal Tolerance

 

The Fabrication (Manufacturing) Tolerance compensates for the fabrication allowance for etch back. By adding a fabrication tolerance, we calculate the land area that we need after the fabrication etching process. If your manufacturer over-sizes the land areas during the CAM process to compensate for their own etching tolerances, this is referred to as “double tolerance” because of double compensation for the same allowance. Ask your manufacturer if they over-size the land features. If they do, tell them that you already compensated for that in your CAD library. The IPC-7351 fabrication tolerance is 0.05mm.

Fabrication Tolerance

Fabrication Tolerance

The Placement (Assembly) Tolerance compensates for the pick and place machine accuracy. When parts are manually placed or machine placed, there is a small margin of placement accuracy that must be accounted for. The IPC-7351 assembly tolerance is 0.05mm.

Land Place (Spacing) Round-off relates to the land center to land center spacing. The goal in the IPC-7351 is to place all lands on a 0.05mm grid, so the space between the land span is rounded to 0.1mm increments so that the distance from the center of the land pattern to the center of the land is in 0.05mm increments. This plays a critical role in trace routing to achieve the highest packing density. In this picture example of a common Chip Component, the land snap grid is 0.05 mm from the center of the part to the center of the lands. The C1 & C2 dimensions.

Land Place and Size Round-off

Land Place and Size Round-off

Land Size Round-off is the value that the land size rounds up or down to. The IPC-7×51 standards round  land sizes to 0.05mm increments with the exception of micro-miniature component packages that are typically less than 1.6mm in size. The micro-miniature part land size round-off is set to 0.01mm increments. In the picture above, the “X” & “Y” dimensions are rounded off in 0.05 mm increments. Even the land corner radius is rounded in 0.05 mm increments.

Solder Joint Goals for Toe are usually the outside the component lead with two exceptions, the J-Lead and the Molded Body components the Toe is under the component body. The Heel goals are normally on the inside of the component lead and the side goals are for both sides of the component lead.  In Part 5 of this series I listed the component Lead Forms. Every lead form has it’s unique solder joint goal table. Here is a sample table for the Least, Nominal and Most “Toe, Heel and Side” goals and the Placement Courtyard Excess for the Gull Wing component family. Notice the Round-off factor is in 0.05 mm increments.

Gull Wing Solder Joint Goal Table

Gull Wing Solder Joint Goal Table

 

When all of the Tolerances, Round-offs and Solder Joint goals are applied the end result is a perfect land pattern.

Land Pattern & Component with Tolerances

Land Pattern & Component with Tolerances

 

If all the Tolerances and Solder Joint Goals were removed from the mathematical model, the component lead would be equal to the land size. This is the starting point for all land size calculations. The picture below illustrates a Chip Component (black) without Tolerances, Round-offs, or Solder Joint Goals and the land size (cyan).

Land Pattern & Component with no Tolerances

Land Pattern & Component with no Tolerances

 

The resulting solder joint for a chip component should look similar to this picture. Note that the component terminal never touches the land. There must be solder paste between the component lead and the land to form the best solder joint. Here’s a note from the IPC J-STD-001D “Requirements for Soldered Electrical and Electronic Assemblies”. Section 4.14 Solder Connection: All solder connections shall indicate evidence of wetting and adherence where the solder blends to the solder surface.

Chip Solder Joint

Chip Solder Joint

 

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18 November, 2010
Placement Courtyards
I promised to post “The Anatomy of a Land Pattern” in Part 6 of my blog, but the subject must be broken down into mini-blogs as the topic covers too many issues. So let’s start with the IPC-7351B “Placement Courtyard”.

The IPC-7351B standard only focuses on 2 two major aspects of the CAD library:

  1. The land size and spacing
  2. Placement courtyard

All of the other aspects of the CAD library part such as silkscreen & assembly outlines, polarity markings, ref des, centroid marking, etc. are considered user definable drafting items. This includes all of the rules that pertain to these items such as line widths, silkscreen to land spacing, polarity sizes, ref des height, etc. are not part of the standard. But the Placement Courtyard Boundary is defined in the IPC-7351B standard, but the line width used to create the outline is user definable. The default solder mask and paste mask values are mentioned in the IPC-7351 as to be 1:1 scale of the land size, but this is only a recommendation.

See Courtyard Determination pictures below to see the 3 outlines defined by IPC-7351 as:

  1. Maximum Component Boundary
  2. Minimum Placement Courtyard
  3. Courtyard Manufacturing Zone
Surface Mount Courtyard Determination

Surface Mount Courtyard Determination

Plated Through-hole Courtyard Determination

Plated Through-hole Courtyard Determination

Here are the standard spacing rules from the Maximum Component Boundary to the Minimum Placement Courtyard:

  1. Least Environment = 0.1 mm
  2. Nominal Environment = 0.25 mm
  3. Most Environment = 0.5 mm

There are different Placement Courtyard spacing rules for Grid Array packages based on ball size:

  1. Ball size above 0.50 mm = 2 mm
  2. Ball size between 0.50 mm & 0.25 mm = 1 mm
  3. Ball size below 0.25 mm = 0.5 mm

One of the key aspects of the placement courtyard is that it allows room for rework. In the case of the BGA’s, the larger the Ball Size, the larger the heat nozzles and removal equipment is for getting around and under the component to unsolder the contacts. An important note to make here is that if you have no intentions of ever reworking (remove and replace) a BGA component then the 2 mm placement courtyard is not necessary and a 0.5 mm courtyard excess is OK. This also is relevant to the “Most Environment” where the minimum courtyard excess is 0.5 mm on all SMT land patterns. i.e.: the military and medical instrument industry might use the Most Environment and require “Class 3″ High Reliability Electronic Products where continued high performance is critical and product downtime cannot be tolerated. The “Class 3″ fabrication is very expensive and if a component on the PCB fails, rework becomes necessary to reduce cost. Rework requires additional land pattern placement courtyard excess to allow adequate space for rework equipment. Alternatively, the “Least Environment” for High Density PCB Layout, like handheld devices, has a courtyard excess of 0.1 mm with no room for rework equipment. So if a component fails in your Cellular Phone it will not be sent back to the shop for rework, but instead, it will be discarded.

The Placement Courtyards can be placed next to each other so the outline overlaps, however you need to discuss this with your assembly shop if they require an additional Manufacturing Zone for their process. The Placement Courtyard round-off snap grid is 0.5 mm. The question of “why don’t you place the silkscreen outline outside the land pattern boundary” is a FAQ and this is the answer - ”It is important that all silkscreen outline data be located inside the Placement Courtyard”.

This includes the Post Assembly Inspection Dot, which sometimes gets partially placed outside the placement courtyard. This is why in the upcoming IPC-2614 for Board Fabrication Documentation and drafting standards the “Post Assembly Inspection Dot” will become the “Post Assembly Inspection Line” and it will look like this to keep them inside the Placement Courtyard:

Dip & SOP Post Assembly Inspection Line

DIP & SOP Post Assembly Inspection Line

The Placement Courtyard or Courtyard Excess is the smallest area that provides a minimum electrical and mechanical clearance of the maximum extremities of the land pattern and/or the component body. However it is the responsibility of the user to verify the land patterns used for achieving an undisturbed mounting process including testing and an ensured reliability for the product stress conditions in use.
For many through-hole parts and connectors, the placement courtyard will follow the contour of the component body outline and land pattern.
Axial Lead Courtyard

Axial Lead Courtyard

Most Enterprise CAD tools like Mentor Expedition have a different DRC checking feature that the user can define the component type to component type spacing rules. In this case, the placement courtyard excess should be turned off and the placement courtyard would be identical to the Maximum Component Boundary.

Enterprise CAD Tool Courtyard

Enterprise CAD Tool Courtyard

The Enterprise CAD tool placement courtyard is not defined in the IPC-7351 standard. This concept is based on the Enterprise CAD tools ability to determine various component body to body spacing that is user definable.

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15 October, 2010
Component Lead Forms

Before we go deeper into the various component families, we need to clarify the component lead forms of today’s component packaging technology and what is going to be eventually phased out and what is new and why.

The pin (component lead) pitch and the overall body height are continually shrinking. This is why the SSOP and TSOP land pattern names have to be dropped from the standard. S = Shrink for Fine Pitch and T = Thin for low profile height. If these 2 values are constantly changing then where is the line drawn? Whose part is Thin or Fine Pitch and by what measure? The Gull Wing lead has hit the wall at 0.4 mm pitch. Most assembly shops will try to convince you to swap that part out of your design for a larger pin pitch however, No-lead SON and QFN lead styles are being produced and manufactured at 0.4 mm pitch with no problems. The finer pitch parts have more I/O’s and a smaller footprint with a much lower profile than J-Lead or Gull Wing packages, so it’s obvious that the component industry is going to be no-lead or bottom only flat lead or side lead packages.

Let’s review the existing component lead forms in alphabetical order. The BGA or Ball Grid Array has been around since the 1980′s but the pin pitch started out with 1.5 mm and then quickly went to 1.27 mm (50 mils) for about 15 years. Then in the late 1990′s, the 1 mm pitch BGA was introduced and every couple years a smaller pin pitch was introduced. Today 0.4 mm pitch BGA’s are in every cell phone and 0.3 mm pitch BGA’s are the next generation.

There are 2 types of BGA Ball Leads -

  1. Collapsing – this is normally 0.65 mm pitch and higher, where the Land (pad) is smaller than the Ball size to allow the Ball to collapse around the sides of the Land. This requires a non-solder mask defined Land where the solder mask must be larger than the Land.
  2. Non-collapsing – this is normally 0.5 mm pitch and smaller, where the Land (pad) is larger than the ball to allow for via-in-pad technology and provide an adequate annular ring. The solder mask can be the same size as the Land. In some cases the Land for fine pitch BGA’s is solder mask defined where the solder mask encroaches slightly over the land. This provides protection for any trace routing between the lands but the most significant benefit is to help secure the Land to the PCB. During cell phone “drop testing”, the BGA solder joint normally holds better than the land to the Prepreg. i.e.: drop tests prove that the non-solder mask land will rip from the PCB before the solder joint breaks. So the solder mask defined land is secured better to the PCB for drop testing.

For more information about BGA’s, read my white paper “Metric Pitch BGA and Micro BGA Routing Solutions”.

Ball Lead

Ball Lead

Here is a picture that shows the non-collapsing BGA in the left and the collapsing BGA ball on the right.
Non-collapsing Ball vs: Collapsing Ball

Non-collapsing Ball vs: Collapsing Ball

While we’re on the subject of “Grid Array Lead Forms” let’s move on down the list of bottom only lead types. The next lead form in the “bottom only” category is the “Bump” lead. This is widely used in a package called “Land Grid Array” or LGA. The Land (pad) size can be the same as the Bump diameter and via-in-pad can be much more forgiving than BGA voids due to a dimple in the Land after the plug and plate process. This lead form is also highly lead-free compatible.

Bump Lead

Bump Lead

The next Grid Array lead form is the “Bottom Flat” and is also used in Land Grid Array (LGA) component packages. Linear Technologies is the leading provider of Bottom Flat Lead LGA packages. This lead form is also highly compatible with lead-free solder alloys as there is no reason for wetting (flow) properties in the solder.

We can also categorize the Pull-back Lead SON and QFN component packages with this solder joint goal as a slight periphery land is required to allow the solder to move from under the lead to the periphery to surround the protruding lead for a solid solder joint.

Bottom Flat Lead

Bottom Flat Lead

The next Grid Array component lead is the “Column”. Actel and Xilinx are the leading manufacturers for this lead style. You will not find any pin pitches smaller than 1 mm for the Column Lead. The Land must be slightly larger than the column to form a good solder joint.

Column Lead

Column Lead

Column Lead Solder Joint.

Column Lead Solder Joint

Column Lead Solder Joint

The last SMT Grid Array is the newest lead form in the industry is the “Pillar Column”. Recently introduced by Actel, this component lead has much promise for an improved solder joint. But time will tell how long this one will last.

Pillar Column Lead

Pillar Column Lead

Here is a solder joint for the Pillar Column Lead. Nice connection!

Pillar Column Lead Solder Joint

Pillar Column Lead Solder Joint

The “Corner Concave” lead form is primarily used for the Oscillator component family. It’s perfect for Oscillators because it only has 4 leads that are necessary for the standard Oscillator requirements.

Corner Concave Lead

Corner Concave Lead

“Cylindrical End Cap” goes with the Metal Electrode Lead Face (MELF) component family for resistors and diodes. I still can’t figure out why the industry still produces round components, but engineers continue to design them into their schematics. I would like to know why?
Cylindrical End Cap Lead

Cylindrical End Cap Lead

“Flat Lead” components are coming on strong. These are the SODFL (Small Outline Diode Flat Lead) 2 leaded components and the SOTFL (Small Outline Transistor Flat Lead) packages that come in 3, 5, 6 and 8 lead components. Both of these component families are the direct replacement for the Gull Wing Lead SOD and SOT-23 packages.

Flat Lead

Flat Lead

“Flat No-lead” is used in the SON (Small Outline No-lead) with terminals on 2 sides and QFN (Quad Flat No-lead) with leads on 4 sides. The most common SON & QFN today is the “Edge” lead, where the component lead starts under the component and goes out to the component body edge. This solder joint goal requires a Toe, Heel and Side solder fillet where the toe joint is visible for inspection.

Flat No-lead Edge

Flat No-lead Edge

The other Flat No-lead is referred to as a “Pull-back” lead or “Bottom Only”. The solder joint goal is a periphery land around the terminal. Pull-back leads come in 2 lead shapes -

  • D-Shape or Bullet in some CAD tools
  • Rectangle

This lead style has the same solder joint goals as the Bottom Only LGA lead.

Bottom Only Lead

Bottom Only Lead

The “Flat Thermal” lead comes in a DPAK where the signal pins and Gull Wing and the thermal lead is Flat. The ”Flat Thermal” lead is also used as the heat sink for SON, QFN, SOP and QFP packages. It is usually embedded in the plastic component body and therefore the solder joint goals are usually 1:1 scale for the maximum component lead size and Land size.

Flat Bottom Only Lead

Flat Bottom Only Lead

Every PCB designer is familiar with the Gull Wing lead, but it has 2 separate rule sets that are defined by the pin pitch -

  1. Less than 0.625 mm pitch
  2. Greater than 0.625 mm pitch

We need to note that 70% of the solder strength in the Gull Wing lead is in the “Heel” joint.

Gull Wing Lead

Gull Wing Lead

Gull Wing lead solder joint. A good solder joint has visible wetting under the component lead.
Gull Wing Solder Joint

Gull Wing Solder Joint

The “Inward Flat Ribbon L” is used for the Molded Body component family. This includes Polarized and Non-polarized Capacitors, Inductors, Resistors and LED’s. The most popular is the Tantalum Capacitor.

Inward Flat Ribbon L Lead

Inward Flat Ribbon L Lead

The “J-Lead” is one of the original SMT leads that became popular with the PLCC (Plastic Leaded Chip Carrier) and then the SOJ (Small Outline J-Lead). This lead form was very popular because the leads were stable and easy to manually solder. And the solder joint was easy to inspect. However, with the advent of High Speed technology, lead-free solder, low profile fine pitch component packages, this lead form will be one of the first SMT leads to become obsolete.

J-Lead

J-Lead

Here is a J-Lead solder joint.
J-Lead Solder Joint

J-Lead Solder Joint

The “Outward Flat Ribbon L” lead is used to reduce the footprint size of SOT and SOP components. It’s similar to a Gull Wing lead, but the lead bends downward immediately coming out of the component body and then is bent flat. The flat lead is very compatible to lead-free solder alloys and takes up less PCB real-estate. Since there is no heel and these components are so “low profile”, the land is usually trimmed at the nominal component body. If the land (pad) protrudes under the component body, it will end up with solder on the bottom of the component during reflow.

The Outward L lead also has 2 separate rule sets that are defined by the pin pitch -

  1. Less than 0.625 mm pitch
  2. Greater than 0.625 mm pitch
Outward L Lead

Outward L Lead

The first component lead was the Plated Through-hole (PTH) and it’s still used today for almost every type of discrete component and connector. The through-hole components are mostly used for today’s power supply boards and proto-type boards that require hand soldering and rework.

Plated Though-hole Lead

Plated Though-hole Lead

The “Rectangular End Cap” is used for discrete resistors, capacitors and inductors. This lead type is by far the most popular due to the component count. An average PCB has 80 – 90% of the total part quantity using the Rectangular End Cap lead form. These components are easy to manually solder and easy to rework if necessary. However, the new DFN (Dual Flat No-lead) component with Bottom Only terminations is better for lead-free solder and part placement density.

Rectangular End Cap Lead

Rectangular End Cap Lead

Here is a rectangular end cap solder joint.

Rectangular End Cap Solder Joint

Rectangular End Cap Solder Joint

The “Side Lead” comes in 3 different lead styles -

  • Concave
  • Convex
  • Flat

The Side Lead is on the outside perimeter of the component body and normally runs from the bottom to the top of the component. It is used widely for Chip Array’s and LCC (Leadless Chip Carriers) and has 2 different sets of solder joint goals depending on the lead pitch -

  • Pitch is less than or equal to 1 mm
  • Pitch is greater than 1 mm

Here is the Concave “Side Lead” -

Concave Lead

Concave Lead

Here is the Flat “Side Lead” -

Side Flat Lead

Side Flat Lead

Here is the Convex “Side Lead” -

Side Convex Lead

Side Convex Lead

The last component lead form in the list is the “Under Body Outward L”. This lead form is used for Aluminum Electrolytic Capacitors and 2-pin SMT Crystals. This lead form has 2 different solder joint goals that are based on the component height. Once the component height exceeds 10 mm, the solder joint goals have to be more robust.

Under Body Outward L Lead

Under Body Outward L Lead

Now that we covered all the component lead forms, we can dive into the various component families and relate their lead forms back to this post. It’s going to be interesting to find out what new component lead will be invented by a component manufacturer in the years to come, but when they do, the IPC-7351 land pattern committee will be there to develop the optimized solder joint goal chart.

Next week I’m planning on posting “The Anatomy of a Land Pattern” and all the various elements that a quality land pattern must have in order to qualify for PCB design perfection. Here is a sample picture of the details we’ll cover -

Anatomy of a Land Pattern

Anatomy of a Land Pattern

, ,

8 October, 2010

SOT (Small Outline Transistor) Components

The SOT23 is the most popular of this component family. It has 3, 5, 6 and 8 pin variations and 3 popular pin pitches.

  • 0.50 mm Pitch
  • 0.65 mm Pitch
  • 0.95 mm Pitch 
  • Note: All pictures are shown in the “Nominal Environment” land pattern.

    Figure 19 illustrates 0.5 mm pitch SOT23 3-pin and 8-pin examples.

    FIGURE 19

    FIGURE 19

    0.5 mm pitch SOT23 fanout examples. Figure 20 illustrates 4 different 0.5mm pitch 3-pin SOT23 land pattern via fanout techniques. The SOT23 parts are placed on a 0.5 mm grid system and all the vias snap to a 1 mm grid.

    • There are two 0.1 mm trace/space technology on all layers.
    • Via land size is 0.5 mm, hole size is 0.25 mm and plane anti-pad is 0.7mm
    FIGURE 20

    FIGURE 20

    0.5 mm pitch SOT23 fanout examples. Figure 21 illustrates 4 different 0.5mm pitch 8 pin SOT23 land pattern via fanout techniques. The SOT23 parts are placed on a 0.5 mm grid system and all the vias snap to a 1 mm grid. This allows two 0.1 mm trace/space technology on all layers.

    FIGURE 21

    FIGURE 21

    Figure 22 illustrates 0.65 mm pitch SOT23 3, 5, 6 and 8-pin examples.

    FIGURE 22

    FIGURE 22

    0.65 mm pitch SOT23 fanout examples. Figure 23 illustrates 5 different 0.65mm pitch 3, 5, 6 and 8 pin SOT23 land pattern via fanout techniques. The SOT23 parts are placed on a 0.5 mm grid system and all the vias snap to a 1 mm grid. This allows two 0.1 mm trace/space technology on all layers with 0.5 mm via land.

    FIGURE 23

    FIGURE 23

    Figure 24 illustrates 0.95 mm pitch SOT23 3, 5, 6 and 8-pin examples.

    Figure 24

    Figure 24

    0.95 mm pitch SOT23 fanout examples. Figure 25 illustrates 5 different 0.95mm pitch 3, 5, 6 and 8 pin SOT23 land pattern via fanout techniques. The SOT23 parts are placed on a 0.5 mm grid system and all the vias snap to a 1 mm grid. This allows two 0.1 mm trace/space technology on all layers.

    Figure 25

    Figure 25

    The SOT223 is the next most popular component family. It has 4, 5 and 6 pin variations and 3 popular pin pitches.

    • 1.27 mm Pitch
    • 1.50 mm Pitch
    • 2.30 mm Pitch

    Figure 26 shows the 6-pin 1.27 mm pitch SOT223 land pattern.

    FIGURE 26

    FIGURE 26

    Figure 27 shows the 6-pin 1.27 mm pitch SOT223 land pattern via fanout using a power via with a 1 mm land and a 0.5 mm hole snapped to a 1 mm grid. The signal trace/space rules are 0.1 mm.

    FIGURE 27

    FIGURE 27

    Figure 28 shows the 5-pin 1.5 mm pitch SOT223 land pattern.

    FIGURE 28

    FIGURE 28

    Figure 29 shows the 5-pin 1.5 mm pitch SOT223 land pattern via fanout using a power via with a 1 mm land and a 0.5 mm hole snapped to a 1 mm grid. The trace/space rules are 0.1 mm.

    FIGURE 29

    FIGURE 29

    Figure 30 shows the 4-pin 2.3 mm pitch SOT223 land pattern.

    FIGURE 30

    FIGURE 30

    Figure 31 shows the 4-pin 1.5 mm pitch SOT223 land pattern via fanout using a power via with a 1 mm land and a 0.5 mm hole snapped to a 1 mm grid. The trace/space rules are 0.1 mm but the routing grid is 0.05 mm.

    FIGURE 31

    FIGURE 31

    The SOT143 is the next most popular component family. It has 4 pins with a larger Pin 1. The pin pitch is 1.9 mm. See Figure 32.

    FIGURE 32

    FIGURE 32

    Figure 33 shows the 4-pin 1.9 mm pitch SOT143 land pattern via fanout using a via with a 0.5 mm land and a 0.25 mm hole snapped to a 1 mm grid. The trace/space rules are 0.1 mm and the routing grid is 0.1 mm.

    FIGURE 33

    FIGURE 33

    The SOT343 is the next most popular component family. It has 4 pins with a larger Pin 1. See Figure 34.

    FIGURE 34

    FIGURE 34

     

    Figure 35 shows the 4-pin 1.3 mm pitch SOT343 land pattern via fanout using a via with a 0.5 mm land and a 0.25 mm hole snapped to a 1 mm grid. The trace/space rules are 0.1 mm and the routing grid is 0.1 mm. The via fanout direction depends on which layer you need more routing channels.

    FIGURE 35

    FIGURE 35

    The SOT component family uses a Gull Wing component lead. All Gull Wing leaded components have four different sets of land pattern rules. These examples are for the “Nominal Environment”.

    1.       Pin pitch less than 0.625mm (side goal is -0.02 mm) considered “fine pitch”

    2.       Pin pitch greater than 0.625 mm (side goal is 0.03 mm)

    3.       Outward Flat Ribbon with pin pitch less than 0.625mm (heel goal is 0.15 mm and side goal is -0.02 mm)

    4.       Outward Flat Ribbon with pin pitch greater than 0.625mm (heel goal is 0.15 mm and side goal is 0.03 mm)

    The formula that calculates the difference between Gull Wing and Outward Flat Ribbon (Mini Gull Wing) is shown in Figure 36.

    FIGURE 36

    FIGURE 36

    We already discussed Chip and Molded Body assembly outlines and Ref Des. It’s important to note that the Lands (Pads) do not get added to the assembly drawing layer for small parts. The 2 most important things on the assembly drawing are the Ref Des and Component Outline. If the part is too small and the Lands interfere with the Ref Des, then do not add the Top Assembly Lands to the padstack. However, if the Lands do not interfere with the Ref Des then we should add the Top Assembly Lands to the padstack.

    Here are some of the various assembly outlines for the 0.95 mm pitch SOT23 component family. See Figure 37 for the 3, 5 & 6 pin versions of the Assembly Outline, Ref Des, Polarity Marker for pin 1 location and Lands (Pads). Note that the polarity marker shape in a triangle in the corner because the component is too small for the standard circle polarity marker.

    FIGURE 37

    FIGURE 37

    Here are some of the various assembly outlines for the SOT223 component family. See Figure 38 for the 4, 5 & 6 pin versions of the Assembly Outline, Ref Des, Polarity Marker for pin 1 location and Lands (Pads).

    FIGURE 38

    FIGURE 38

    Here are some of the assembly outlines for the SOT143 component family. See Figure 39 for the standard and reverse pin versions of the Assembly Outline, Ref Des, Polarity Marker for pin 1 location and Lands (Pads). Note that the polarity marker shape in a triangle in the corner because the component is too small for the standard circle polarity marker.

    FIGURE 39

    FIGURE 39

    Here are some of the various silkscreen outlines for the SOT component families. See Figure 40 for the SOT23, SOT223 and SOT143 versions of the Silkscreen Outline, Polarity Marker and 0.5 mm Post Assembly Inspection Dot for pin 1 location and Lands (Pads). Note that the SOT23 and SOT143 do not have a polarity marker inside the silkscreen outline because the component is too small. The Post Assembly Inspection Dot will be the Polarity Marker.

    FIGURE 40

    FIGURE 40

  • 0.50 mm Pitch
  • 0.65 mm Pitch
  • 0.95 mm Pitch
  • , ,

    1 October, 2010

    Molded Body Components

    The next most popular component family on a PCB design layout is the Molded Body Tantalum Capacitor (CAPM). The CAPM components have an “L-Bend” component lead form. Most Molded Body Tantalum Capacitors are metric by default including their standard EIA names –

    • 3216 – 3.2 mm X 1.6 mm
    • 6032 – 6.0 mm X 3.2 mm
    • 7243 – 7.2 mm X 4.3 mm
    • 7343 – 7.3 mm X 4.3 mm

    The common component families that use the Molded Body package are -

    • Non-polarized Capacitors
    • Polarized Capacitors
    • Diodes
    • Resistors
    • Inductors
    • Fuses
    • LED’s

    See Figure 15 for the 6032 component and land pattern dimensions. I broke 1 rule to create this land pattern. Instead of a 1.0 mm Land Placement Round-off I used a 2.0 mm Land Placement Round-off to snap the land centers on a 0.5 mm grid from the center of the land pattern. When the land pattern is placed on a 0.5 mm grid, the land centers fall on a 0.5 mm grid. This improves the via fanout seen in Figure 17.

    FIGURE 15

    FIGURE 15

    Figure 16 illustrates the silkscreen and placement courtyard rules and sizes. The illustration shows the component leads on top of the land for graphic representation.

    FIGURE 16

    FIGURE 16

    Figure 17 illustrates the via fanout for a 6032 Tantalum Capacitor. If you are going to use the same size via to maintain trace/space compatibility with the rest of the PCB layout I recommend at least two vias. The placement of these vias is critical in accomplish reduced impedance and increased capacitance. It’s important that the vias be placed as close as possible to the capacitor terminal leads. In Figure 17, the 2 vias coming out the side are 0.15 mm away from the terminal lead. The vias coming out the ends on the land pattern are 0.75 mm away from the terminal leads. That’s 5 times farther away than the vias coming out the sides however some EE engineers will request all 4 vias. Since all the traces and vias are snapped to a 0.5 mm grid, this makes copy/paste much easier to manually fanout all of the 6032 Molded Body Capacitors. The dot grid display is 1 mm and the land pattern is placed on a 0.5 mm grid. All the vias in this illustration fall on a 1 mm snap grid.

    FIGURE 17

    FIGURE 17

    See Figure 18 for the 7343 Molded Body Tantalum Capacitor I recommend a larger via size with a 1 mm land size, 0.55 mm hole size and 1.3 mm plane anti-pad. This via can carry more current and you only need two (but the EE will ask for a 3rd one). The illustration in Figure 16 snaps all the vias to a 1 mm grid system. These vias are twice the size of the previous vias but all the same trace/space rules apply. The display grid is 1 mm.

    Because the land pattern, traces and the vias are on a 1 mm snap grid, this improves the copy/paste feature for manual fanout of all of the 7343 Molded Body components in your PCB layout.

    FIGURE 18

    FIGURE 18

     

    , ,

    22 September, 2010
    Chip Components Smaller Than 1608 (EIA 0603)

    Before you read this blog ‘Part 2″, read Part 1 White Paper of this series - “PCB Design Perfection Starts in the CAD Library” for the introduction information. Download it here – http://www.mentor.com/products/pcb-system-design/techpubs/download?id=60454

    Parts 3, 4, 5 etc. will be posted here over the next couple weeks. I’m really looking forward to your feedback on this subject. I believe that everyone who follows these basic rules will increase productivity levels in their PCB design layouts.

    See Figure 6 for the dimensions of a standard 1005 (EIA 0402) component superimposed with its related land pattern. In this case, I decided to break 2 rules –

    1.       Land size round-off 0.05 mm

    2.       Land snap grid round-off 1.0 mm

    The land center to land center spacing is 1.0 mm which is perfect for 1.0 mm space via fanout and the placement courtyard width is 1.0 mm which is perfect for placing parts 1.0 mm from center to center.

    When placing the 1005 in the PCB layout use a 0.1mm grid to optimize the part placement and via fanout.

    FIGURE 6

    FIGURE 6

    The 1005 (EIA 0402) was made for 1mm pitch BGA fanout. In Figure 7 you can see 2 different fanout options and one is superior to the other. The fanout coming out the top has all the key features. The vias are 0.25 mm closer to the capacitor component terminals than the typical right/left fanout which decreases impedance and increases capacitance. Also, the top fanout vias snap to a 1 mm grid because the 1005 land pattern was snapped to a 0.1 mm grid system. The 0.5 mm via land (pad) diameter with 0.25 mm hole size and 0.7 mm plane anti-pad is perfect for 0.1mm trace/space technology. See Figure 4. The trace width for the power fanout is 0.3 mm.

    FIGURE 7

    FIGURE 7

     
    See Figure 8 for the dimensions of a standard 0603 (EIA 0201) component superimposed with its related land pattern. In this case, I decided to break 2 rules –

    1.       Land size round-off 0.05 mm

    2.       Land snap grid round-off 1.0 mm

    3.       Use the “Least” environment due to component miniaturization

    For chip components smaller than 1 mm X 0.5 mm I use the IPC-7351B Least Environment to prevent tombstoning. When 2 pin micro-miniature parts have too much solder volume tombstoning can occur in the reflow oven. The land size for the 0603 should be slightly more than 2 times the terminal lead size.

    FIGURE 8

    FIGURE 8

    One of the techniques that can be used to prevent tombstoning for the 0603 (EIA 0201) is to thin the paste stencil from 0.15 mm to a smaller value for every occurrence of this component in the paste mask stencil. See Figure 9. The responsibility of the stencil thickness thinning process is placed on the assembly shop and the stencil manufacturer (not the PCB designer). Assembly shops use various solder alloys that require unique stencil creation.

    FIGURE 9

    FIGURE 9

    See Figure 10 for the dimensions of a standard 0603 (EIA 0201) component superimposed with its related land pattern. If you normally use the “Most” environment, my recommendation for the 0603 (EIA 0201) land pattern is to use the “Nominal” environment. The IPC nominal land size for the 0603 is about 3 times the size of the terminal lead. For this 0603 micro-miniature component, stay away from the “Most” environment as the solder volume is more than 4 times greater than the terminal lead footprint.

    FIGURE 10

    FIGURE 10

     The 1005 (EIA 0402) & 0603 (EIA 0201) chip components are very compatible with 1 mm pitch BGA. In Figure 11 there are 2 uses for the 1005 and one in-between the vias and one via-in-pad method. Because the 1005 land centers are on 1 mm pitch, the capacitor land (pad) falls directly centered on the via. Via-in-Pad technology will increase PCB cost because these vias need to be plated, filled and surface finish on the capacitor pad. The 0603 fall in-between the vias for the 0.1 mm trace/space technology DRC. This solution will not increase PCB fabrication cost. The dot grid display is 0.05 mm.

    FIGURE 11

    FIGURE 11

    IPC does not have a “standard” on drafting items such as silkscreen and assembly outlines and polarity markings yet.  There are several types of silkscreen outlines and polarity markings that are used for Non-polarized Chip parts, Polarized Capacitors, Diodes and LED’s.

    For a standard Non-polarized chip there are 2 options. See Figure 12 for both options. One is a line that separates the 2 lands. The default size is 0.2 mm and the default silkscreen the land gap is 0.25 mm. The CAD librarian can change both the line width and the gap to achieve placing a line between two lands that only have a 0.3 mm Gap by simply changing the line width and gap rules to 0.1 mm.

    FIGURE 12

    FIGURE 12

    See Figure 13 for the silkscreen outline for the Chip Diode. The Chip Diode also has a Post Assembly Inspection Dot so you can visually verify if the assembly inserted the Diode or LED in the correct rotation. The Polarized Chip Capacitor would have the same exact silkscreen outline but without the 0.6 mm bar.

    FIGURE 13

    FIGURE 13

    The Assembly Drawing Outlines and Polarity Markings are totally different than the Silkscreen Outlines and Polarity Markings. The first most obvious difference is that the outline shape is 1:1 scale of the component body. This outline can be either the “Nominal” or “Maximum” component body size. Another difference is the Reference Designator is centered inside the component outline and is never moved or relocated. The reference designator default size is 1.5 mm height with a 10% line width.

    The Reference Designator and Assembly Outline only change rules for micro-miniature parts. The Assembly Outline will grow as large as the placement courtyard in order to fit the Reference Designator inside the Assembly Outline. When the component gets smaller, the Reference Designator will decrease from the default 1.5 mm height to a sliding scale of values until it fits inside the assembly outline. The reference designator scaling width is always 10% of the height. The various reference designator heights for micro-miniature components are –

    ·         0.15 mm

    ·         0.125 mm

    ·         0.1 mm

    ·         0.075 mm

    ·         0.05 mm (this is the smallest human readable text height)

    See Figure 14 for the non-polarized and polarized capacitor, diode and resistor assembly outlines and Reference designators. Notice the absence of land pads. From all Chip and Molded Body components, the Land is removed from the SMT padstack to insure that the reference designators are unobstructed. Also, for CAD tools that have this feature, Right Reading Orthogonal is always recommended so when the component is rotated, the reference designator is always flipped to right reading orientation.

    FIGURE 14

    FIGURE 14

     
    Read Part 3 “Molded Body Components” coming up next.
     

    , ,

    8 July, 2010

    I’m curious as how do PCB designers route metric pitch BGA’s on a mil grid system or gridless (which consumes memory and CPU)? I can’t figure why anyone would use a mil grid system for any PCB CAD library construction or PCB design layout when all the SMT component manufacturers are only producing metric pin pitch packages. This is where we note that all chip resistors and capacitors are dimensioned using whole metric numbers. So by design all of them are considered metric based components. i.e.: 1206 = 0.125″ x 0.062″ or 3216 = 3.2mm x 1.6mm for the same component. Which is easier to understand? To me it’s interesting why some PCB designers still use the Imperial measurement system. I’d like to hear from designers and engineers who use the technology combination of metric pin pitch components and mil based part placement and trace sizes & routing grids. How do you do it?

    My big secret was to teach all the mechanical engineers and EE engineers the metric measurement system by providing equivalent charts. Even purchasing had to have a metric to Imperial chart for chip components because the BOM had all metric land pattern names but the buyers had to have the inch equivalent names to place an order.

    So we had to do for Chips. Notice that 0603 and 0402 appear in both columns -

    Metric = Inch

    3216 = 1206

    2012 = 0805

    1608 = 0603

    1005 = 0402

    0603 = 0201

    0402 = 01005

    Here is what I’m talking about. This is a table from a component manufacturer that lists the dimensions of a series of resistors in hard metric but all of the component names in the far left column are Imperial units (Type Inches). i.e. the first part is a metric 0402 (0.4mm x 0.2mm) but Panasonic calls it a 01005 (the inch equivalent 0.4mm = 0.0015748″ x 0.2mm = 0.007874). Why doesn’t Panasonic call it for what it really is, 0402?

    After successfully transitioned all the engineers then the PCB design process got really easy, faster and simpler. Then when I give the PCB manufacturer all my nice clean metric drawings and metric Gerber and Drill data the first thing they do is convert all units to Imperial to panelize and CAM the job with their mil based DRC rules. Wow, it took longer to CAM my job because of the translation.

    Inch Names but Metric Dimensions

    Inch Names but Metric Dimensions

    When I dig deeper to find out “Why do they do that”, I discover that all the materials like core, copper and prepreg all come in mil based thicknesses and shapes. So that’s where the buck stops! I mean that if overnight all the material providers only produced metric thickness and metric sizes that all of the PCB fabrication shops would be doing metric based manufacturing. The next thing you know they’d be recommending all their customers to produce metric based Gerber and drill data for their new machines made in Europe. (The reason why they’re made in Europe is because there’s no way in this lifetime that any USA manufacturer is going to create a metric based machine. Maybe in another lifetime…) and I digress.

    When the PCB fabrication shop starts recommending metric units preferred to their customers that’s when true electronic product development automation will really kick in and maybe we’ll start creating faster, better, more accurate, cheaper products or rather products that today cost $100,000 will only cost $1000. I hope to see the revelation in my lifetime where all design units are the same regardless if it’s Imperial or metric, just pick one and make life easy. 99 nations voted for metric. USA voted to gradually adopt with full conversion by 2015. At least that’s the 1985 Omnibus Act signed by Ronald Regan defines to extend Jimmy Carter’s 1975 Metric Conversion Act which was to convert USA in 10 years and adds another 30 years for the gradual metric conversion one industry at a time. Note that the EU Metric Directive went into effect January 1, 2010 for all weights & measures throughout Europe. The worldwide PCB design industry is 50% converted on the front end and we’re waiting on the back end. The PCB component manufacturers have semi successfully converted to metric units. At least they dimension everything in metric units but some still refer to the Imperial (Inch) name to order the component (like the Panasonic chart above). Very confusing!

    Come on PCB suppliers. The electronics industry needs all of you to transition to hard metric to complete the entire loop in the PCB design engineering and manufacturing industry. You are directly responsible for holding the electronics industry back from achieving the highest productivity levels obtainable and standardizing on a single unit system. I do not think the PCB material suppliers have a clue on how much of an impact they have on every electronic product being developed today. I beg you; please make our job easier and put an end to the dual measurement system chaos that EE engineers, mechanical engineers and PCB designers have to deal with every day until you transition. It’s time to stop using the Imperial unit system in the electronics industry and use one measurement system. Every Standards organization in the world has referred to the metric unit system as the ”vastly superior” alternative. So why isn’t everyone listening?


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