Posts Tagged ‘PCB Design’
Drafting elements in a CAD library part are not “Standardized” for specific values or sizes but there are recommendations that are coming out in the IPC-2610 series that include schematics, PCB assembly and fabrication. Documentation includes component outline and polarity markings for silkscreen and assembly. This article focuses on silkscreen and assembly Reference Designators.
Every reference designator (Ref Des) originates in the schematic diagram and is transferred to the PCB layout via the netlist. They also appear in the Bill of Material that is exported from the schematic and passed to the assembly shop. The rules for reference designator assignment are established by the IPC-2512 publication. However the Ref Des size, font, CAD layer and placement location are left up to the EE engineer and/or PCB designer.
Every CAD library part should have 2 distinct reference designators, one for the silkscreen and one for the assembly drawing. Both designators, in every CAD library part, are normally located in the center of the component body. The silkscreen reference designator is relocated outside the component body after the part placement is completed and approved by the design review panel. If via fanout and trace routing cause part placement nudging then it’s best to wait until that process is completed or duplication of effort will come into play. Also, if via hole sizes exceed 0.4 mm and they are not tented then it’s best to avoid placing the silkscreen reference designators over the via hole, as the ink will drop into the hole making the reference designator indistinguishable and eliminate the purpose of having the reference designator to begin with. If you are using large via hole sizes it’s best to wait until the PCB design passes the engineering routing review panel. Via sizes smaller than 0.4mm can be tented (covered) with solder mask and the placement of silkscreen designators can go directly on the via.
The silkscreen reference designator height sizes are –
- 1.0 mm – Minimum
- 1.5 mm – LP Calculator Default
- 2.0 mm – Nominal
- 2.5 mm – Maximum
The reference designator text line width is normally 10% of the height for good clarity and to prevent the characters from bleeding or blobbing together. The 0.15 mm height “Default” is what the LP Calculator uses but users can change the global setting values to any value or measurement system.
The assembly reference designators are different in the fact that they never get relocated outside the component body outline. Assembly reference designator height sizes are –
1.5 mm – Default
1.2 mm – 0.5 mm for miniature components
Here are some chip component assembly ref des height sizes that scale down according to the body size –
4520 (EIA 1808) = 1.5 mm
3216 (EIA 1206) = 1.2 mm
2013 (EIA 0805) = 1.0 mm
1608 (EIA 0603) = 0.7 mm
1005 (EIA 0402) = 0.5 mm
0603 (EIA 0201) – 0.5 mm
Note: All assembly body outlines are 1:1 scale of the physical component with the exception of all micro-miniature parts smaller than 1.6 mm length. Parts less than 1.6 mm length are EIA 0402 and 0201. These 2 parts assembly outline has to be enlarged so that the 0.5 mm assembly ref des fits cleanly inside it.
Also, most land patterns (CAD library parts) have the Lands (Pads) put on the assembly layer. This is true for all parts that are large enough to accommodate both the component leads and the assembly ref des without interfering with each other. When the component leads interfere with the assembly ref des, the component leads on the assembly layer are removed from the padstack. This includes all chip components, crystals, molded body parts and grid array parts with bottom only leads.
See Figure 1 for a sample of a typical silkscreen with the reference designators relocated outside the part.
See Figure 2 for a sample of a typical assembly drawing with the reference designators inside the part, exactly where they were put when the CAD library parts were built. While the silkscreen reference designators must be relocated to an optimized location after part placement is completed, the assembly reference designators do not require any movement or cleanup. Also notice in Figure 2 that the large parts have lands (pads) built into the padstack and the small chip components do not have lands (pads) on the assembly layer. The LP Calculator allows the user to turn on/off Land on Assembly because some people do not want any component leads on the assembly drawing; rather they only want closed polygons with reference designators inside.
Table 1 contains list of the standard reference designators from the IPC-2612 standard for schematic symbol generation.
*These class letters would not appear in a parts list as they are part of a PCB and not an active electronic component.
**Not a class letter, but commonly used to designate test points for maintenance purposes.
Note: The above list is not exhaustive. See the standard list of class designation letters in ANSI Y32.2/IEEE Std 315, Section 22 and the Index.
Here are some tips about Metric Speak that all PCB designers need to know. “Metric” is not a unit of measure. Metric is a term that describes a measurement system. You use either millimeters or microns for your PCB design units. The proper terminology to describe your working units when using the metric measurement system is millimeters or microns, not metric. Example: When doing PCB layout in Inches or Mils you never refer to working in “Imperial Units”.
Millimeters allow finer (and greater) granularity in the PCB design grid system to optimize board real-estate, part placement, via fanout and routing trace/space features and snap grids. This will be very important in the future of PCB RF Micro-technology. PCB impedance measurements are more accurate in Micron units than “Ounces of Copper” and Mil core/Prepreg dielectric. Use Micron Units to achieve the highest level of accuracy for impedance calculations.
Unfortunately, PCB manufacturers are directly responsible for holding back the progress of the transition to metrication of our industry. When the PCB fabrication companies transitions to the metric system, the entire electronics industry will achieve the peak of “electronic product development automation”. Until then, we’ll plod along using dual units in the land of chaos.
Here is an example of the chaos in the Chip Component family. All Chip names refer to their body length and width. When EIAJ introduced the standard Chip and Molded body component dimensions, only millimeter units were used. A 3216 was 3.2 mm long and 1.6 mm wide. It was very simple. When the data was passed on to EIA in America, they changed all the chip names from millimeters to Inches and a 3216 was renamed 1206 or 0.125” length and 0.062” width (just drop the 3rd place number). Today most component manufacturers dimension all there component packages in millimeters see Table 1 that illustrates Metric vs. Imperial names. You can easily see the confusion in the dual measurement system.
Let’s start the transition process. 99% of all PCB layouts use vias. See Table 2 for an Inch to Millimeter chart for common via sizes starting with a 0.15 mm hole and growing in 0.05 mm increments. I’ll provide the entire padstack conversion. I intentionally did not add thermal relief data because vias should have a direct plane connection (no thermal relief is necessary). When transitioning from Imperial units to Metric units, always round-off the millimeter values in 0.05mm increments for normal resolution. If you’re working on extremely dense hand held device technology, round-off to the nearest 0.01 mm. For PCB design, there is no reason to go more than 2 places to the right of the decimal point for the present. 0.01 mm = 0.0003937”
Table 3 illustrates 4 common inch based part placement grids and their millimeter equivalent. The common rule in placing parts in millimeters is to always stay one place to the right of the decimal or 0.1 mm increments.
Table 4 provides all the common trace/space technology and routing snap grids. The common rule when working in millimeters is to always use a 0.05 mm routing grid. Most component lead pin pitches are 0.05 mm increments and IPC-7351B land (pad) sizes and snap grids are in 0.05 mm increments. This totally optimizes trace routing and eliminates wasted PCB real-estate. Everything fits together tighter than Lego building blocks. Notice that in the inch units, a gridless shape-based option is used, but in millimeters all objects can easily snap to a grid and still achieve maximum density solutions. I provide 3 various route snap grid solutions for the various trace/space rules.
Note: Inch based routing grids are evenly divisible into 0.100” while millimeter based routing grids are evenly divisible into 1 mm.
Table 5 provides the PCB material equivalents. Note that the various columns are not related to each other. Each column describes a specific PCB feature. In the first column “Board Thickness” is common PCB finished material thicknesses and the metric equivalent rounded off to the nearest 0.1 mm. The second column is copper weight in ounces and their micron equivalent. Using microns to describe copper thickness is better than using weight. The third and forth columns go together. Column 3 defines the type of hole and column 4 provides the PCB fabrication tolerance for each different hole type in the chart.
Table 6 is common plated through-hole padstacks for component leads and their inch to millimeter conversion. All hole, pad and plane clearance values are in 0.05mm increments. The Solder Mask is the same value as the outer layer pads. This padstack information was taken from the proportional padstack table and you can download it here under “Appnote 10836: Proportional Through-hole Padstacks” – http://www.mentor.com/products/pcb-system-design/library-tools/lp-wizard/import-docs
Note: this downloadable chart only contains millimeter values and not the inch equivalents in Table 6.
Table 7 is common non-plated through-hole padstacks and their inch to millimeter conversion. All hole, pad and plane clearance values are in 0.05mm increments. The Solder Mask is the same value as the hole size to allow the PCB manufacturer to oversize it per their specific fabrication tolerances. Notice that the pad size for every padstack is 1.00 mm. Because the holes are not plated, the hole size is typically larger than the hole size. Also, there is no reason to have multiple pad sizes when the pad is eventually drilled away. The only reason for having a pad in a non-plated padstack is display a marker as a guide for the hole location. The PCB manufacturer does not need the pad in the padstack, but sometimes when there is no pad (but there is a drill hole) the manufacturer might question if the hole is valid. Of course there is no thermal relief required in non-plated hole padstacks.
I want to note that the LP Calculator automatically performs all of these through-hole padstack calculations for you and provides 5 different options –
IPC-7251 Most Environment
IPC-7251 Nominal Environment
IPC-7251 Least Environment
User Defined Environment Rules
You can get a free LP Calculator by signing up for a 10-day evaluation of LP Wizard here – http://www.mentor.com/products/pcb-system-design/library-tools/lp-wizard/lp-wizard-eval
After the LP Wizard 10-day evaluation is over, the LP Wizard program will run in “Demo Mode” as LP Calculator.
If the French would have won the French & Indian War against the British (the 7 Year War from 1754 to 1763) Imperial Units or the English measurement system would not exist in society today. Even the British transitioned to the metric measurement system 46 years ago. America is the last stronghold for the Imperial measurement system and how much longer will it take for the world to become united under a single measurement system. This is what world standards and space age technology acceleration will require to fully automate all PCB processes.
One of the greatest secrets to PCB design perfection today in 2011 is the use of the metric unit system. From 1974 – 1991 we used Inch units for PCB layout. From 1991 – 2001 we used Mil units. From 2001 – 2011 we used millimeter units. I have to say that when we made the transition from Mils to millimeters our productivity levels slipped a bit during the learning curve. But after 5 or 6 PCB layouts our productivity was back to normal. After about 15 PCB layouts our productivity levels surpassed all previous results. If I was forced to go back to the Mil measurement system, my productivity levels would reverse backwards. There is no way in the world that anyone in 2011 using Mil units can outperform the same talent using Millimeter units because most component pin pitches are on a millimeter grid system (like the 1 mm pitch BGA) and metric units are vastly superior to work within the PCB design space because all the numbers are evenly divisible by 10 and there is no use for calculators for mathematical calculations. There is no one that I know of that has successfully transitioned to the metric unit system for PCB layout that wants to go back to the Imperial unit system. That statement alone tells it all.
As a matter of fact, there would not be Imperial units in the world today if the United States government (congress) fulfilled the commitment that they signed at the Treaty of the Meter back in 1875. I hear it all the time from corporations who will not convert – “We’re American and we have our own measurement system. We are not part of the European Union or Russia or Japan. We’re proud to be Americans and we believe in our way of life and the system and values that we use”. Well, let me shine a little light on all those proud Americans who obviously do not know the historical facts. So before I go into PCB design details of why metric units are superior, I need to explain the historical background to set the stage.
Most Americans think that our involvement with metric measurement is relatively new. In fact, the United States has been increasing its use of metric units for many years, and the pace has accelerated in the past four decades. In the early 1800′s, under the presidency of Thomas Jefferson, the U.S. Coast and Geodetic Survey (the government’s surveying and map-making agency) used meter and kilogram standards brought from France. Abraham Lincoln was a strong proponent of the metric unit system and in 1866 (just 1 year after his assassination), Congress authorized the use of the metric system in America and supplied every state with a set of standard metric weights and measures.
In 1875, the United States solidified its commitment to the development of the internationally recognized metric system by becoming one of the original seventeen signatory nations to the Treaty of the Meter. The signing of this international agreement concluded five years of meetings in which the metric system was reformulated, refining the accuracy of its standards. The Treaty of the Meter, also known as the “Metric Convention” established the International Bureau of Weights and Measures (BIPM) in Sèvres, France, to provide standards of measurement for worldwide use.
In 1893, metric standards, developed through international cooperation under the auspices of BIPM, were adopted as the fundamental standards for length and mass in the United States. Our customary measurements — the foot, pound, quart, etc. — have been defined in relation to the meter and the kilogram ever since. The General Conference of Weights and Measures, the governing body that has overall responsibility for the metric system, and which is made up of the signatory nations to the Treaty of the Meter, approved an updated version of the metric system in 1960. This modern system is called Le Système International d’Unités or the International System of Units, abbreviated SI.
The United Kingdom began a transition to the metric system in 1965 to more fully mesh its business and trade practices with those of the European Common Market. The conversion of the United Kingdom and the Commonwealth nations to SI created a new sense of urgency regarding the use of metric units in the United States.
In 1968, Congress authorized a three-year study of systems of measurement in the U.S., with particular emphasis on the feasibility of adopting SI. The detailed U.S. Metric Study was conducted by the Department of Commerce. A 45-member advisory panel consulted with and took testimony from hundreds of consumers, business organizations, labor groups, manufacturers, and state and local officials.
The final report of the study, “A Metric America: A Decision Whose Time Has Come” concluded that the U.S. would eventually join the rest of the world in the use of the metric system of measurement. The study found that measurement in the United States was already based on metric units in many areas and that it was becoming more so every day. The majority of study participants believed that conversion to the metric system was in the best interests of the Nation, particularly in view of the importance of foreign trade and the increasing influence of technology in American life.
The study recommended that the United States implement a carefully planned transition to predominant use of the metric system over a ten-year period. Note: In 1975, the Australian continent also implemented its metric conversion act and successfully transitioned. The United States Congress passed the Metric Conversion Act of 1975 “to coordinate and plan the increasing use of the metric system in the United States.” The Act, however, did not require a ten-year conversion period. A process of voluntary conversion was initiated, and the U.S. Metric Board was established. The Board was charged with “devising and carrying out a broad program of planning, coordination, and public education, consistent with other national policy and interests, with the aim of implementing the policy set forth in this Act.” The efforts of the Metric Board were largely ignored by the American public, and, in 1981, the Board reported to Congress that it lacked the clear Congressional mandate necessary to bring about national conversion. Due to this apparent ineffectiveness, and in an effort to reduce Federal spending, the Metric Board was disestablished in the fall of 1982.
The Board’s demise increased doubts about the United States’ commitment to metrication. Public and private sector metric transition slowed at the same time that the very reasons for the United States to adopt the metric system — the increasing competitiveness of other nations and the demands of global marketplaces — made completing the conversion even more important.
Congress, recognizing the necessity of the United States’ conformance with international standards for trade, included new encouragement for U.S. industrial metrication in the Omnibus Trade and Competitiveness Act of 1988. This legislation amended the Metric Conversion Act of 1975 and designates the metric system as the preferred system of weights and measures for United States trade and commerce.” The legislation states that the Federal Government has a responsibility to assist industry, especially small business, as it voluntarily converts to the metric system of measurement.
Federal agencies were required by this legislation, with certain exceptions, to use the metric system in their procurement, grants and other business-related activities by the end of 1992. While not mandating metric use in the private sector, the Federal Government has sought to serve as a catalyst in the metric conversion of the country’s trade, industry, and commerce.
The current effort toward national metrication is based on the conclusion that industrial and commercial productivity, mathematics and science education, and the competitiveness of American products and services in world markets, will be enhanced by completing the change to the metric system of units. Failure to complete the change will increasingly handicap the Nation’s industry and economy.
There is one thing that I would like to clarify to the reader that I’m not proposing that the American “way of life” change in our sports (football, baseball, golf, etc.) or cooking units in our kitchens, but rather our “industry” must change to increase our competitiveness with the rest of the world. However, America has an impact on other counties weights and measurement systems. The EU Metric Directive (80/181/EEC), that was scheduled to go into effect on January 1, 2010, has been modified to allow the continuation of both supplemental (U.S. customary, inch-pound) and metric units for consumer goods sold in the EU. The rule was published on May 7, 2009 in the Official Journal of the European Union.
The modified Directive instructs the European Commission to produce a report to the Parliament and Council regarding the smooth functioning of the internal market and international acceptance of SI units by December 31, 2019, including proposals where appropriate. Demonstrated progress will be important to achieve long-term acceptance of supplemental units in the EU. Modifying the U.S. Fair Package and Labeling Act (FPLA) to permit metric labeling is an example where greater international marketplace acceptance of SI units can be achieved.
Next week I will present Imperial to Metric conversion charts as they apply to the PCB design industry. I will also post a short message on the proper terminology that I refer to as “Metric Etiquette”.
There is a reasonable solution for via fanout and a routing solution for the 0.5 mm pitch BGA but we need to think outside the box. The board thickness is an important factor because it affects the hole plating aspect ratio. If you use a 1 mm PCB thickness and want to achieve a 7:1 aspect ratio (this is common among all manufacturers) then the smallest hole size is 0.15 mm (6 mil). There are manufacturer’s that can hard drill a 0.15 mm (6 mil) hole through a 1 mm PCB. There are manufacturers that claim they can easily handle 10:1 aspect ratios. This means that they can drill 0.15 mm (6 mil) holes through 1.57 mm (0.062”) thick PCB material and plate the hole without problems. Drilling all the way through the PCB is important because sequential lamination is an expensive process.
For all via-in-land technology, a thermal relief on the voltage and ground plane connections must be used to prevent cold solder joints. A direct via-in-land connection to the plane will dissipate the heat required to melt the solder around the BGA ball and this will result in a cold or cracked solder joint. The exception to this rule is if the via only contacts a single plane with ½ OZ. copper or less.
If traces are routed between pins of the 0.5 pitch BGA land, the solder mask must be a 1:1 scale to create a “solder mask defined” BGA land. In this way, the traces between the lands will be protected from exposure and possible short circuiting.
The 0.5 mm pitch BGA via-in-land drill hole through the PCB is leading edge technology. When laser drills are capable of producing 0.125 hole sizes entirely through the board and PCB manufacturers can accurately fill the holes with conductive metal epoxy, this technology will become mainstream.
Micro-via technology is the mainstream solution for 0.5 pitch BGA components when a 0.1 – 0.15 laser hole is drilled one, two or three layers deep. This involves sequential lamination but before we get to that subject let’s discuss the via fanout process. Using via-in-land technology, we must offset the drill holes to create adequate routing channels. This is the only routing solution that I know of to maintain manufacturability. See Figure 1 for a via fanout solution for the outer layer. Notice that you will have to add additional copper land for via annular ring.
See Figure 2 for a via fanout solution for the inner layers. The most important feature here is the 0.1 mm (4 mil) trace width & 0.1 mm space between Trace to Via and Via to Via.
Depending on how many rows and columns in the BGA will determine the number of routing layers required.
Sequential lamination process requires the inner layers to be laminated, drilled and plated in Phase 1 and then add 2 additional outer layers and back through lamination, drill and plate in Phase 2. Then add 2 additional outer layers and back through lamination, drill and plate in Phase 3. See Figure 3 for the various phases of sequential lamination.
Let me try to explain why sequential lamination is so expensive and why most people avoid it unless they absolutely need it for high volume production. The PCB inner layer manufacturing goes through the entire fabrication process in Phase 1. Then the first HDI layers that are added to the PCB have to go through the entire fabrication process over again. This basically doubles the cost in Phase 2. Then the second HDI layers that are added to the PCB have to go through the entire fabrication process over again. This basically triples the cost in Phase 3 and the manufacturer’s say that they are basically building the same PC board 3 times.
There are 2 methods of via drilling for sequential lamination. Staggered vias and stacked vias. See Figure 4 for the staggered micro-via process.
Notice in the Staggered Micro-via picture that the via plugging color is green. This could be an epoxy fill because the vias are staggered and there is no manufacturing stress. Discuss staggered vs: stacked vias with your manufacturer to find out if one technique is less expensive than the other. See Figure 5 for the stacked micro-via process.
The Stacked Micro-vias must be filled with conductive metal to prevent the outer laser drill from damaging the inner layer hole. See Figure 6.
The latest generation technology developed by Dow Electronic Materials for advanced via fill plating, MICROFILL™ EVF Via Fill provides enhanced via filling, with simultaneous through-hole plating, at surface thicknesses unattainable. Formulated to operate in existing equipment over a broad range of operating conditions, MICROFILL™ EVF Copper Via Fill is suitable for HDI applications. It is proved by sufficient experience that MICROFILL™ EVF could help to reduce 20% plating thickness and helps to improve varied plating defects. See Figure 7 for stacked micro-via conductive fill techniques. To read more on this topic see: http://www.rohmhaas.com/wcm/information/em/interconnect/microfill/index.page
Notice the lower right image in Figure 7 that shows a 0.15 mm via hole going all the way through a 1 mm thick PCB with 20um (0.000787”) or ½ OZ. copper plating thickness. The normal hole plating thickness on an average PCB is 25um (0.001″) or 1 mil.
The land pattern standards clearly define all the properties necessary for standardization and acceptability of a “One World CAD Library”. The main objective in defining a one world CAD library is to achieve the highest level of “Electronic Product Development Automation”. This encompasses all the processes involved from engineering to PCB layout to fabrication, assembly and test. The data format standards need this type of consistency in order to meet the efficiency that electronic data transfer can bring to the industry.
Many large firms have spent millions of dollars creating and implementing their own unique standards for their own “Electronic Product Development Automation”. These standards are proprietary to each firm and are not openly shared with the rest of the industry. This has resulted in massive duplication of effort costing the industry millions of man hours in waste and creating industry chaos and global non-standardization.
The Land pattern standards (both IPC-7351 and IEC 61188-5-1) put an end to the “Proprietary Intellectual Property” and introduce a world standard so every electronics firm can benefit from Electronic Product Development Automation. The data format standards (IPC-2581 and IEC 61182-2) are an open database XML software code that is neutral to all the various CAD ASCII formats. For true machine automation to exist, the world desperately needs a neutral CAD database format that all PCB manufacturing machines can read.
One of the factors in global standardization is that of establishing a CAD component description and land pattern standard that adopts a fixed Zero Component Orientation so that all CAD images are built with the same rotation for the purpose of assembly machine automation. The IPC-7351 indicates that in the CAD library, all pin 1 locations are in the upper left corner for multiple pin components and pin 1 on left for 2-pin components. Figure 1 represents IPC-7351 default and IEC 61188-7 “Level A” zero component orientation.
In May 2009, IEC land pattern committee voted and approved a new Level B Zero Component Orientation and redefined the IPC-7351 Zero Orientation as Level A. The new IEC 61188-7 defines Zero Component Orientation pin 1 locations in the bottom left corner except 2-pin components Pin 1 is on the left side and labeled it “Level B”. Figure 2 represents IEC 61188-7 “Level B” zero component orientation.
Since the basic rules allow two variations of levels in the description of the CAD system library, it is a mandatory requirement to define which level was used (level A or Level B) for the component descriptions in the data file. This information is a mandatory requirement in the Header of any file that incorporates land patterns using these principles of zero-based orientation. See Figure 3 for the “Level A” zero orientation and machine rotation.
The industry association EIA (Electronics Industry Association) is responsible for component descriptions and tape and reel orientation in the EIA-481-D standard. EIA has tried valiantly to influence the industry by making good standards that describe the component outlines and how they should be positioned in the delivery system to the equipment on the manufacturing floor. Suppliers of parts have either not adhered to the recommendations or have misunderstood the intent and provided their products in different orientations.
Here are the EIA-481-D standard tape and reel pictures (Figures 4 & 5) that illustrate quadrant designations.
IPC and IEC use consistent rotations throughout their standard where EIA uses multiple rotation variations
IPC-7×51 “Level A” uses Quadrant 2 for Pin 1 Upper Left and Quadrants 2-4 for Upper Center
IEC 61188-7 “Level B” uses Quadrant 1 for Pin 1 Lower Left and Quadrants 1-2 for Left Center
EIA-481-D uses Quadrant 1 for Pin 1 Lower Left BGA, SOIC, SOP, QFN (rectangle), DIP
EIA-481-D uses Quadrant 2 for Pin 1 Upper Left TO-252, TO-263, QFN (square), TSOP
EIA-481-D uses Quadrant 3 for Pin 1 Lower Right for all SOT and miniature parts
EIA-481-D uses Quadrants 1-2 (Pin 1 Left Center) for PLCC, LCC
None of the 3 standards use Quadrant 4 for Pin 1 locations
The main purpose of creating the land pattern standards is to achieve reliable solder joint formation platforms; the reason for developing the data transfer structure is to improve the efficiency with which engineering intelligence is converted to manufacturing reality. Even if the neutral CAD format can drive all the manufacturing machines, it would be meaningless unless the component description standard for CAD land patterns was implemented with some consistency. Zero Component Orientation has a key role in machine automation.
The easiest way to illustrate the 3 world standards is to list every component family and their respective Zero Component Orientation for each standard. The big question is – Which standard will prevail?
Note: The EIA-481-D rotations marked in Red conflict with both IPC and IEC
Download the complete IPC-7351B Electronic Component Zero Orientation document here – http://www.mentor.com/resources/appnotes/upload/zero-orientation-cad-libaray.pdf
The BGA or Ball Grid Array has been around since the 1980′s but the pin pitch started out with 1.5 mm and then quickly went to 1.27 mm (50 mils) for about 15 years. Then in the late 1990′s, the 1 mm pitch BGA was introduced and every couple years a smaller pin pitch was introduced. Today 0.4 mm pitch BGA’s are in every cell phone and 0.3 mm pitch BGA’s are the next generation. Figure 1 displays the lead type for this component family.
There are 2 types of BGA Ball Leads –
Non-collapsing – this is normally 0.5 mm pitch and smaller, where the Land (pad) is larger than the ball to allow for via-in-pad technology and provide an adequate annular ring. The solder mask can be the same size as the Land. In some cases the Land for fine pitch BGA’s is solder mask defined where the solder mask encroaches slightly over the land. This provides protection for any trace routing between the lands but the most significant benefit is to help secure the Land to the PCB. During cell phone “drop testing”, the BGA solder joint normally holds better than the land to the Prepreg. i.e.: drop tests prove that the non-solder mask land will rip from the PCB before the solder joint breaks. So the solder mask defined land is secured better to the PCB for drop testing.
Collapsing - this is normally 0.65 mm pitch and higher, where the Land (pad) is smaller than the Ball size to allow the Ball to collapse around the sides of the Land. This requires a non-solder mask defined Land where the solder mask must be larger than the Land.
See Figure 2 for examples of non-collapsing and collapsing BGA balls.
The BGA Land (pad) size is determined by the ball size as seen below in Table 1 from IPC-7351B land pattern standard. Notice the correlation between the “reduction” and the “land pattern density level”. The 3 density levels change the land size reduction percentage, but they also determine the Placement Courtyard Excess. See Table 3.
Note: The IPC-7351B LP Calculator Uses this chart for calculations
It is very important to note that IPC prefers the Maximum Material Condition for all BGA Land sizes; they do not use the Nominal Land Diameter, but do use the Maximum Land Variation Diameter (notice the Bold numbers in the Chart “Land Variation” column). Notice that the standard ball sizes are in 0.05 mm increments until the pin pitch hits 0.5 mm and less. However, even though the world standards try to keep BGA balls sizes in 0.05 mm increments, component manufacturer’s sometimes do not adhere to the standard and create BGA ball sizes in 0.01 mm increments, but I have never seen a BGA ball size less than a 0.01 mm increment. Also, the BGA pin pitches are in 0.05 mm increments. As a result, the BGA land (pad) sizes are in 0.05 mm increments including the via fanout padstacks and hole sizes.
IPC-7351B has a 3-Tier BGA formula for Placement Courtyard Excess that uses the BGA ball size to calculate an adequate placement courtyard for BGA rework tools. If the BGA has a large ball size, larger rework equipment is necessary to unsolder the increased solder volume.
With a small ball size, the placement courtyard can be smaller as less heat is then required to unsolder the BGA component for rework. However, the end user may not plan to rework the BGA if it fails. In that case, there is no need to have a robust placement courtyard, but a recommended minimum placement courtyard excess is 0.5 mm.
“Non-collapsing” ball BGA components
Table 2 below is used for land size calculations for non-collapsing BGA balls.
It is very important to note that IPC prefers the Maximum Material Condition for all BGA Land Sizes, meaning that the Maximum Land Variation Diameter is used; not the “Nominal Land Diameter”.
Figure 3 is a 0.5 pitch non-collapsing BGA ball. Instead of shrinking, the non-collapsing land size gets larger to handle the solder volume that creates the solder joint. This technology is new to the electronics industry and was created as a solution for lead-free BGA balls and via-in-pad technology as a routing solution for fine pitch BGA components.
Via-in-Land Technology Trace/Space & Grid Data
BGA Ball Size: 0.15 Trace Width: 0.075
BGA Land Dia: 0.275 Trace/Trace Space: 0.075
Hole Size: 0.15 Trace/Via Space: 0.075
Thermal Relief Required Trace/BGA Land: 0.075
Plane Clearance: 0.425 Routing Grid: 0.05
Solder Mask: 1:1 scale Part Place Grid: 1
IPC-7351A has a 3-Tier BGA formula for Placement Courtyards that uses the BGA ball size to calculate an adequate placement courtyard for BGA rework tools.
If the BGA has a large ball size, larger rework equipment is necessary to unsolder the large solder volume. With a small ball size, the placement courtyard can be smaller as less heat is then required to unsolder the BGA component for rework. However, the end user may not plan to rework the BGA if it fails. In that case, there is no need to have a robust placement courtyard.
Table 3 below represents the 3-Tier scenario and the different placement courtyard excess size determination.
Padstack creation is something every CAD tool will eventually have to incorporate because it expedites and optimizes CAD library construction. You can download the IPC-7351B Padstack Naming Convention here – AppNote 10833: IPC-7251 & 7351 Padstack Naming Convention or http://www.mentor.com/products/pcb-system-design/library-tools/lp-wizard/import-docs
The SMT Padstack is easy -
- Top Land
- Top Solder Mask
- Top Paste Mask
- Top Assembly
Part 7 of this blog explains the Land Calculation for SMT land patterns, so let’s discuss Plated Through-hole calculations in this segment.
The Through-hole (PTH) Padstack is complex -
- Drill Hole
- Top Assembly
- Top Solder Mask
- Top Land
- Inner Land
- Plane Thermal Relief
- Plane Anti-pad (Clearance)
- Bottom Land
- Bottom Solder Mask
- Bottom Assembly
Here is a picture of a through-hole padstack.
Once you calculate the hole size, the minimum annular ring is 0.05 mm.
So the Minimum Annular Ring X 2 + Minimum Fabrication Allowance + Maximum Lead + Hole Over Lead = Pad Diameter
The IPC-7251 Through-hole land patterns have the capability of accommodating all three performance classiﬁcations.
Producibility Levels: When appropriate this standard will provide three design producibility levels of features, tolerances, measurements, assembly, testing of completion or veriﬁcation of the manufacturing process that reﬂect progressive increases in sophistication of tooling, materials or processing and, therefore progressive increases in fabrication cost. These levels are:
Level A General Design Producibility – Preferred [Maximum land\lead to hole relationship]
Level B Moderate Design Producibility – Standard [Nominal land\lead to hole relationship]
Level C High Design Producibility – Reduced [Least land\lead to hole relationship]
The producibility levels are not to be interpreted as a design requirement, but a method of communicating the degree of difficulty of a feature between design and fabrication/assembly facilities. The use of one level for a speciﬁc feature does not mean that other features must be of the same level. Selection should always be based on the minimum need, while recognizing that the precision, performance, conductive pattern density, equipment, assembly and testing requirements determine the design producibility level. The numbers listed within the tables of IPC-7251 are to be used as a guide in determining what the level of producibility will be for any feature. The speciﬁc requirement for any feature that must be controlled on the end item shall be speciﬁed on the master drawing of the printed board or the printed board assembly drawing.
Download the IPC-7251 padstack charts here – AppNote 10835: IPC-7251 Padstack Charts
Density Level A: Maximum Land/Lead to Hole Relationship – The ‘maximum’ land pattern conditions have been developed to accommodate the most robust producability of the solder application method. The geometry furnished may provide a wider process window for solder processing. The level A land patterns are usually associated with low component density product applications.
Density Level B: Nominal Land/Lead to Hole Relationship – Products with a moderate level of component density may consider adapting the ‘median’ land pattern geometry. The median land patterns furnished for all device families will provide a robust solder attachment condition for most soldering processes and should provide a condition suitable for wave, dip, drag or reﬂow soldering.
Density Level C: Least Land/Lead to Hole Relationship – High component density typical of portable and hand-held product applications may consider the ‘minimum’ land pattern geometry variation. Selection of the minimum land pattern geometry may not be suitable for all product use categories.
IPC Performance Classifications: Three general end-product classes have been established to reﬂect progressive increases in sophistication, functional performance requirements and testing/inspection frequency. It should be recognized that there may be an overlap of equipment between classes.
The end product user has the responsibility for determining the ‘‘Use Category’’ or ‘‘Class’’ to which the product belongs. The contract between user and supplier shall specify the ‘‘Class’’ required and indicate any exceptions or additional requirements to the parameters, where appropriate.
Class 1 General Electronic Products – Includes consumer products, some computer and computer peripherals, and hardware suitable for applications where the major requirement is function of the completed assembly.
Class 2 Dedicated Service Electronic – Products Includes communications equipment, sophisticated business machines, and instruments where high performance and extended life is required, and for which uninterrupted service is desired but not mandatory. Typically the end-use environment would not cause failures.
Class 3 High Reliability Electronic Products – Includes all equipment where continued performance or performance-on-demand is mandatory. Equipment downtime cannot be tolerated, end-use environment may be uncommonly harsh, and the equipment must function when required, such as life support systems and other critical systems.
IPC-7351 for SMT technology defines the rules for creating optimized land pattern CAD library parts using a 3-Tier system – Least (high density), Nominal (controlled environment) and Most (ruggedized & shock resistant). Many PCB designers and CAD Librarians have heard about the IPC-7351B standard, but few people know how they work. The IPC LP Calculator has made life easy for the PCB design industry by automatically generating accurate land pattern data derived from component dimensions. Part 7 of this series will describe the basic fundamental aspects of defining the optimized land (pad) size for a CAD library part and the mathematical model of the LP Calculator.
Land (Pad) Size and Location:
These 7 factors are used to calculate the optimum Land Size –
Component Body Tolerance
Component Terminal Tolerance
Land Size Round-off
Land Spacing Round-off
Solder Joint Goals for Toe, Heel and Side
The Fabrication (Manufacturing) Tolerance compensates for the fabrication allowance for etch back. By adding a fabrication tolerance, we calculate the land area that we need after the fabrication etching process. If your manufacturer over-sizes the land areas during the CAM process to compensate for their own etching tolerances, this is referred to as “double tolerance” because of double compensation for the same allowance. Ask your manufacturer if they over-size the land features. If they do, tell them that you already compensated for that in your CAD library. The IPC-7351 fabrication tolerance is 0.05mm.
The Placement (Assembly) Tolerance compensates for the pick and place machine accuracy. When parts are manually placed or machine placed, there is a small margin of placement accuracy that must be accounted for. The IPC-7351 assembly tolerance is 0.05mm.
Land Place (Spacing) Round-off relates to the land center to land center spacing. The goal in the IPC-7351 is to place all lands on a 0.05mm grid, so the space between the land span is rounded to 0.1mm increments so that the distance from the center of the land pattern to the center of the land is in 0.05mm increments. This plays a critical role in trace routing to achieve the highest packing density. In this picture example of a common Chip Component, the land snap grid is 0.05 mm from the center of the part to the center of the lands. The C1 & C2 dimensions.
Land Size Round-off is the value that the land size rounds up or down to. The IPC-7×51 standards round land sizes to 0.05mm increments with the exception of micro-miniature component packages that are typically less than 1.6mm in size. The micro-miniature part land size round-off is set to 0.01mm increments. In the picture above, the “X” & “Y” dimensions are rounded off in 0.05 mm increments. Even the land corner radius is rounded in 0.05 mm increments.
Solder Joint Goals for Toe are usually the outside the component lead with two exceptions, the J-Lead and the Molded Body components the Toe is under the component body. The Heel goals are normally on the inside of the component lead and the side goals are for both sides of the component lead. In Part 5 of this series I listed the component Lead Forms. Every lead form has it’s unique solder joint goal table. Here is a sample table for the Least, Nominal and Most “Toe, Heel and Side” goals and the Placement Courtyard Excess for the Gull Wing component family. Notice the Round-off factor is in 0.05 mm increments.
When all of the Tolerances, Round-offs and Solder Joint goals are applied the end result is a perfect land pattern.
If all the Tolerances and Solder Joint Goals were removed from the mathematical model, the component lead would be equal to the land size. This is the starting point for all land size calculations. The picture below illustrates a Chip Component (black) without Tolerances, Round-offs, or Solder Joint Goals and the land size (cyan).
The resulting solder joint for a chip component should look similar to this picture. Note that the component terminal never touches the land. There must be solder paste between the component lead and the land to form the best solder joint. Here’s a note from the IPC J-STD-001D “Requirements for Soldered Electrical and Electronic Assemblies”. Section 4.14 Solder Connection: All solder connections shall indicate evidence of wetting and adherence where the solder blends to the solder surface.
The IPC-7351B standard only focuses on 2 two major aspects of the CAD library:
- The land size and spacing
- Placement courtyard
All of the other aspects of the CAD library part such as silkscreen & assembly outlines, polarity markings, ref des, centroid marking, etc. are considered user definable drafting items. This includes all of the rules that pertain to these items such as line widths, silkscreen to land spacing, polarity sizes, ref des height, etc. are not part of the standard. But the Placement Courtyard Boundary is defined in the IPC-7351B standard, but the line width used to create the outline is user definable. The default solder mask and paste mask values are mentioned in the IPC-7351 as to be 1:1 scale of the land size, but this is only a recommendation.
See Courtyard Determination pictures below to see the 3 outlines defined by IPC-7351 as:
- Maximum Component Boundary
- Minimum Placement Courtyard
- Courtyard Manufacturing Zone
Here are the standard spacing rules from the Maximum Component Boundary to the Minimum Placement Courtyard:
- Least Environment = 0.1 mm
- Nominal Environment = 0.25 mm
- Most Environment = 0.5 mm
There are different Placement Courtyard spacing rules for Grid Array packages based on ball size:
- Ball size above 0.50 mm = 2 mm
- Ball size between 0.50 mm & 0.25 mm = 1 mm
- Ball size below 0.25 mm = 0.5 mm
One of the key aspects of the placement courtyard is that it allows room for rework. In the case of the BGA’s, the larger the Ball Size, the larger the heat nozzles and removal equipment is for getting around and under the component to unsolder the contacts. An important note to make here is that if you have no intentions of ever reworking (remove and replace) a BGA component then the 2 mm placement courtyard is not necessary and a 0.5 mm courtyard excess is OK. This also is relevant to the “Most Environment” where the minimum courtyard excess is 0.5 mm on all SMT land patterns. i.e.: the military and medical instrument industry might use the Most Environment and require “Class 3″ High Reliability Electronic Products where continued high performance is critical and product downtime cannot be tolerated. The “Class 3″ fabrication is very expensive and if a component on the PCB fails, rework becomes necessary to reduce cost. Rework requires additional land pattern placement courtyard excess to allow adequate space for rework equipment. Alternatively, the “Least Environment” for High Density PCB Layout, like handheld devices, has a courtyard excess of 0.1 mm with no room for rework equipment. So if a component fails in your Cellular Phone it will not be sent back to the shop for rework, but instead, it will be discarded.
The Placement Courtyards can be placed next to each other so the outline overlaps, however you need to discuss this with your assembly shop if they require an additional Manufacturing Zone for their process. The Placement Courtyard round-off snap grid is 0.5 mm. The question of “why don’t you place the silkscreen outline outside the land pattern boundary” is a FAQ and this is the answer - ”It is important that all silkscreen outline data be located inside the Placement Courtyard”.
This includes the Post Assembly Inspection Dot, which sometimes gets partially placed outside the placement courtyard. This is why in the upcoming IPC-2614 for Board Fabrication Documentation and drafting standards the “Post Assembly Inspection Dot” will become the “Post Assembly Inspection Line” and it will look like this to keep them inside the Placement Courtyard:
Most Enterprise CAD tools like Mentor Expedition have a different DRC checking feature that the user can define the component type to component type spacing rules. In this case, the placement courtyard excess should be turned off and the placement courtyard would be identical to the Maximum Component Boundary.
The Enterprise CAD tool placement courtyard is not defined in the IPC-7351 standard. This concept is based on the Enterprise CAD tools ability to determine various component body to body spacing that is user definable.
About Tom Hausherr's Blog
New component package technology and CAD library standards.
- PCB Design Perfection Starts in the CAD Library – Part 19
- PCB Design Perfection Starts in the CAD Library – Part 18
- PCB Design Perfection Starts in the CAD Library – Part 17
- PCB Design Perfection Starts in the CAD Library – Part 16
- PCB Design Perfection Starts in the CAD Library – Part 15 QFN
- Inch to Metric Conversion Tables for PCB design
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