Posts Tagged ‘library tools’
Before we go deeper into the various component families, we need to clarify the component lead forms of today’s component packaging technology and what is going to be eventually phased out and what is new and why.
The pin (component lead) pitch and the overall body height are continually shrinking. This is why the SSOP and TSOP land pattern names have to be dropped from the standard. S = Shrink for Fine Pitch and T = Thin for low profile height. If these 2 values are constantly changing then where is the line drawn? Whose part is Thin or Fine Pitch and by what measure? The Gull Wing lead has hit the wall at 0.4 mm pitch. Most assembly shops will try to convince you to swap that part out of your design for a larger pin pitch however, No-lead SON and QFN lead styles are being produced and manufactured at 0.4 mm pitch with no problems. The finer pitch parts have more I/O’s and a smaller footprint with a much lower profile than J-Lead or Gull Wing packages, so it’s obvious that the component industry is going to be no-lead or bottom only flat lead or side lead packages.
Let’s review the existing component lead forms in alphabetical order. The BGA or Ball Grid Array has been around since the 1980′s but the pin pitch started out with 1.5 mm and then quickly went to 1.27 mm (50 mils) for about 15 years. Then in the late 1990′s, the 1 mm pitch BGA was introduced and every couple years a smaller pin pitch was introduced. Today 0.4 mm pitch BGA’s are in every cell phone and 0.3 mm pitch BGA’s are the next generation.
There are 2 types of BGA Ball Leads -
- Collapsing – this is normally 0.65 mm pitch and higher, where the Land (pad) is smaller than the Ball size to allow the Ball to collapse around the sides of the Land. This requires a non-solder mask defined Land where the solder mask must be larger than the Land.
- Non-collapsing – this is normally 0.5 mm pitch and smaller, where the Land (pad) is larger than the ball to allow for via-in-pad technology and provide an adequate annular ring. The solder mask can be the same size as the Land. In some cases the Land for fine pitch BGA’s is solder mask defined where the solder mask encroaches slightly over the land. This provides protection for any trace routing between the lands but the most significant benefit is to help secure the Land to the PCB. During cell phone “drop testing”, the BGA solder joint normally holds better than the land to the Prepreg. i.e.: drop tests prove that the non-solder mask land will rip from the PCB before the solder joint breaks. So the solder mask defined land is secured better to the PCB for drop testing.
For more information about BGA’s, read my white paper “Metric Pitch BGA and Micro BGA Routing Solutions”.
While we’re on the subject of “Grid Array Lead Forms” let’s move on down the list of bottom only lead types. The next lead form in the “bottom only” category is the “Bump” lead. This is widely used in a package called “Land Grid Array” or LGA. The Land (pad) size can be the same as the Bump diameter and via-in-pad can be much more forgiving than BGA voids due to a dimple in the Land after the plug and plate process. This lead form is also highly lead-free compatible.
The next Grid Array lead form is the “Bottom Flat” and is also used in Land Grid Array (LGA) component packages. Linear Technologies is the leading provider of Bottom Flat Lead LGA packages. This lead form is also highly compatible with lead-free solder alloys as there is no reason for wetting (flow) properties in the solder.
We can also categorize the Pull-back Lead SON and QFN component packages with this solder joint goal as a slight periphery land is required to allow the solder to move from under the lead to the periphery to surround the protruding lead for a solid solder joint.
The next Grid Array component lead is the “Column”. Actel and Xilinx are the leading manufacturers for this lead style. You will not find any pin pitches smaller than 1 mm for the Column Lead. The Land must be slightly larger than the column to form a good solder joint.
Column Lead Solder Joint.
The last SMT Grid Array is the newest lead form in the industry is the “Pillar Column”. Recently introduced by Actel, this component lead has much promise for an improved solder joint. But time will tell how long this one will last.
Here is a solder joint for the Pillar Column Lead. Nice connection!
The “Corner Concave” lead form is primarily used for the Oscillator component family. It’s perfect for Oscillators because it only has 4 leads that are necessary for the standard Oscillator requirements.
“Flat Lead” components are coming on strong. These are the SODFL (Small Outline Diode Flat Lead) 2 leaded components and the SOTFL (Small Outline Transistor Flat Lead) packages that come in 3, 5, 6 and 8 lead components. Both of these component families are the direct replacement for the Gull Wing Lead SOD and SOT-23 packages.
“Flat No-lead” is used in the SON (Small Outline No-lead) with terminals on 2 sides and QFN (Quad Flat No-lead) with leads on 4 sides. The most common SON & QFN today is the “Edge” lead, where the component lead starts under the component and goes out to the component body edge. This solder joint goal requires a Toe, Heel and Side solder fillet where the toe joint is visible for inspection.
The other Flat No-lead is referred to as a “Pull-back” lead or “Bottom Only”. The solder joint goal is a periphery land around the terminal. Pull-back leads come in 2 lead shapes -
- D-Shape or Bullet in some CAD tools
This lead style has the same solder joint goals as the Bottom Only LGA lead.
The “Flat Thermal” lead comes in a DPAK where the signal pins and Gull Wing and the thermal lead is Flat. The ”Flat Thermal” lead is also used as the heat sink for SON, QFN, SOP and QFP packages. It is usually embedded in the plastic component body and therefore the solder joint goals are usually 1:1 scale for the maximum component lead size and Land size.
Every PCB designer is familiar with the Gull Wing lead, but it has 2 separate rule sets that are defined by the pin pitch -
- Less than 0.625 mm pitch
- Greater than 0.625 mm pitch
We need to note that 70% of the solder strength in the Gull Wing lead is in the “Heel” joint.
The “Inward Flat Ribbon L” is used for the Molded Body component family. This includes Polarized and Non-polarized Capacitors, Inductors, Resistors and LED’s. The most popular is the Tantalum Capacitor.
The “J-Lead” is one of the original SMT leads that became popular with the PLCC (Plastic Leaded Chip Carrier) and then the SOJ (Small Outline J-Lead). This lead form was very popular because the leads were stable and easy to manually solder. And the solder joint was easy to inspect. However, with the advent of High Speed technology, lead-free solder, low profile fine pitch component packages, this lead form will be one of the first SMT leads to become obsolete.
The “Outward Flat Ribbon L” lead is used to reduce the footprint size of SOT and SOP components. It’s similar to a Gull Wing lead, but the lead bends downward immediately coming out of the component body and then is bent flat. The flat lead is very compatible to lead-free solder alloys and takes up less PCB real-estate. Since there is no heel and these components are so “low profile”, the land is usually trimmed at the nominal component body. If the land (pad) protrudes under the component body, it will end up with solder on the bottom of the component during reflow.
The Outward L lead also has 2 separate rule sets that are defined by the pin pitch -
- Less than 0.625 mm pitch
- Greater than 0.625 mm pitch
The first component lead was the Plated Through-hole (PTH) and it’s still used today for almost every type of discrete component and connector. The through-hole components are mostly used for today’s power supply boards and proto-type boards that require hand soldering and rework.
The “Rectangular End Cap” is used for discrete resistors, capacitors and inductors. This lead type is by far the most popular due to the component count. An average PCB has 80 – 90% of the total part quantity using the Rectangular End Cap lead form. These components are easy to manually solder and easy to rework if necessary. However, the new DFN (Dual Flat No-lead) component with Bottom Only terminations is better for lead-free solder and part placement density.
Here is a rectangular end cap solder joint.
The “Side Lead” comes in 3 different lead styles -
The Side Lead is on the outside perimeter of the component body and normally runs from the bottom to the top of the component. It is used widely for Chip Array’s and LCC (Leadless Chip Carriers) and has 2 different sets of solder joint goals depending on the lead pitch -
- Pitch is less than or equal to 1 mm
- Pitch is greater than 1 mm
Here is the Concave “Side Lead” -
Here is the Flat “Side Lead” -
Here is the Convex “Side Lead” -
The last component lead form in the list is the “Under Body Outward L”. This lead form is used for Aluminum Electrolytic Capacitors and 2-pin SMT Crystals. This lead form has 2 different solder joint goals that are based on the component height. Once the component height exceeds 10 mm, the solder joint goals have to be more robust.
Now that we covered all the component lead forms, we can dive into the various component families and relate their lead forms back to this post. It’s going to be interesting to find out what new component lead will be invented by a component manufacturer in the years to come, but when they do, the IPC-7351 land pattern committee will be there to develop the optimized solder joint goal chart.
Next week I’m planning on posting “The Anatomy of a Land Pattern” and all the various elements that a quality land pattern must have in order to qualify for PCB design perfection. Here is a sample picture of the details we’ll cover -
The SOT23 is the most popular of this component family. It has 3, 5, 6 and 8 pin variations and 3 popular pin pitches.
Note: All pictures are shown in the “Nominal Environment” land pattern.
Figure 19 illustrates 0.5 mm pitch SOT23 3-pin and 8-pin examples.
0.5 mm pitch SOT23 fanout examples. Figure 20 illustrates 4 different 0.5mm pitch 3-pin SOT23 land pattern via fanout techniques. The SOT23 parts are placed on a 0.5 mm grid system and all the vias snap to a 1 mm grid.
There are two 0.1 mm trace/space technology on all layers.
Via land size is 0.5 mm, hole size is 0.25 mm and plane anti-pad is 0.7mm
0.5 mm pitch SOT23 fanout examples. Figure 21 illustrates 4 different 0.5mm pitch 8 pin SOT23 land pattern via fanout techniques. The SOT23 parts are placed on a 0.5 mm grid system and all the vias snap to a 1 mm grid. This allows two 0.1 mm trace/space technology on all layers.
Figure 22 illustrates 0.65 mm pitch SOT23 3, 5, 6 and 8-pin examples.
0.65 mm pitch SOT23 fanout examples. Figure 23 illustrates 5 different 0.65mm pitch 3, 5, 6 and 8 pin SOT23 land pattern via fanout techniques. The SOT23 parts are placed on a 0.5 mm grid system and all the vias snap to a 1 mm grid. This allows two 0.1 mm trace/space technology on all layers with 0.5 mm via land.
Figure 24 illustrates 0.95 mm pitch SOT23 3, 5, 6 and 8-pin examples.
0.95 mm pitch SOT23 fanout examples. Figure 25 illustrates 5 different 0.95mm pitch 3, 5, 6 and 8 pin SOT23 land pattern via fanout techniques. The SOT23 parts are placed on a 0.5 mm grid system and all the vias snap to a 1 mm grid. This allows two 0.1 mm trace/space technology on all layers.
The SOT223 is the next most popular component family. It has 4, 5 and 6 pin variations and 3 popular pin pitches.
1.27 mm Pitch
1.50 mm Pitch
2.30 mm Pitch
Figure 26 shows the 6-pin 1.27 mm pitch SOT223 land pattern.
Figure 27 shows the 6-pin 1.27 mm pitch SOT223 land pattern via fanout using a power via with a 1 mm land and a 0.5 mm hole snapped to a 1 mm grid. The signal trace/space rules are 0.1 mm.
Figure 28 shows the 5-pin 1.5 mm pitch SOT223 land pattern.
Figure 29 shows the 5-pin 1.5 mm pitch SOT223 land pattern via fanout using a power via with a 1 mm land and a 0.5 mm hole snapped to a 1 mm grid. The trace/space rules are 0.1 mm.
Figure 30 shows the 4-pin 2.3 mm pitch SOT223 land pattern.
Figure 31 shows the 4-pin 1.5 mm pitch SOT223 land pattern via fanout using a power via with a 1 mm land and a 0.5 mm hole snapped to a 1 mm grid. The trace/space rules are 0.1 mm but the routing grid is 0.05 mm.
The SOT143 is the next most popular component family. It has 4 pins with a larger Pin 1. The pin pitch is 1.9 mm. See Figure 32.
Figure 33 shows the 4-pin 1.9 mm pitch SOT143 land pattern via fanout using a via with a 0.5 mm land and a 0.25 mm hole snapped to a 1 mm grid. The trace/space rules are 0.1 mm and the routing grid is 0.1 mm.
The SOT343 is the next most popular component family. It has 4 pins with a larger Pin 1. See Figure 34.
Figure 35 shows the 4-pin 1.3 mm pitch SOT343 land pattern via fanout using a via with a 0.5 mm land and a 0.25 mm hole snapped to a 1 mm grid. The trace/space rules are 0.1 mm and the routing grid is 0.1 mm. The via fanout direction depends on which layer you need more routing channels.
The SOT component family uses a Gull Wing component lead. All Gull Wing leaded components have four different sets of land pattern rules. These examples are for the “Nominal Environment”.
1. Pin pitch less than 0.625mm (side goal is -0.02 mm) considered “fine pitch”
2. Pin pitch greater than 0.625 mm (side goal is 0.03 mm)
3. Outward Flat Ribbon with pin pitch less than 0.625mm (heel goal is 0.15 mm and side goal is -0.02 mm)
4. Outward Flat Ribbon with pin pitch greater than 0.625mm (heel goal is 0.15 mm and side goal is 0.03 mm)
The formula that calculates the difference between Gull Wing and Outward Flat Ribbon (Mini Gull Wing) is shown in Figure 36.
We already discussed Chip and Molded Body assembly outlines and Ref Des. It’s important to note that the Lands (Pads) do not get added to the assembly drawing layer for small parts. The 2 most important things on the assembly drawing are the Ref Des and Component Outline. If the part is too small and the Lands interfere with the Ref Des, then do not add the Top Assembly Lands to the padstack. However, if the Lands do not interfere with the Ref Des then we should add the Top Assembly Lands to the padstack.
Here are some of the various assembly outlines for the 0.95 mm pitch SOT23 component family. See Figure 37 for the 3, 5 & 6 pin versions of the Assembly Outline, Ref Des, Polarity Marker for pin 1 location and Lands (Pads). Note that the polarity marker shape in a triangle in the corner because the component is too small for the standard circle polarity marker.
Here are some of the various assembly outlines for the SOT223 component family. See Figure 38 for the 4, 5 & 6 pin versions of the Assembly Outline, Ref Des, Polarity Marker for pin 1 location and Lands (Pads).
Here are some of the assembly outlines for the SOT143 component family. See Figure 39 for the standard and reverse pin versions of the Assembly Outline, Ref Des, Polarity Marker for pin 1 location and Lands (Pads). Note that the polarity marker shape in a triangle in the corner because the component is too small for the standard circle polarity marker.
Here are some of the various silkscreen outlines for the SOT component families. See Figure 40 for the SOT23, SOT223 and SOT143 versions of the Silkscreen Outline, Polarity Marker and 0.5 mm Post Assembly Inspection Dot for pin 1 location and Lands (Pads). Note that the SOT23 and SOT143 do not have a polarity marker inside the silkscreen outline because the component is too small. The Post Assembly Inspection Dot will be the Polarity Marker.
The next most popular component family on a PCB design layout is the Molded Body Tantalum Capacitor (CAPM). The CAPM components have an “L-Bend” component lead form. Most Molded Body Tantalum Capacitors are metric by default including their standard EIA names –
3216 – 3.2 mm X 1.6 mm
6032 – 6.0 mm X 3.2 mm
7243 – 7.2 mm X 4.3 mm
7343 – 7.3 mm X 4.3 mm
The common component families that use the Molded Body package are -
See Figure 15 for the 6032 component and land pattern dimensions. I broke 1 rule to create this land pattern. Instead of a 1.0 mm Land Placement Round-off I used a 2.0 mm Land Placement Round-off to snap the land centers on a 0.5 mm grid from the center of the land pattern. When the land pattern is placed on a 0.5 mm grid, the land centers fall on a 0.5 mm grid. This improves the via fanout seen in Figure 17.
Figure 16 illustrates the silkscreen and placement courtyard rules and sizes. The illustration shows the component leads on top of the land for graphic representation.
Figure 17 illustrates the via fanout for a 6032 Tantalum Capacitor. If you are going to use the same size via to maintain trace/space compatibility with the rest of the PCB layout I recommend at least two vias. The placement of these vias is critical in accomplish reduced impedance and increased capacitance. It’s important that the vias be placed as close as possible to the capacitor terminal leads. In Figure 17, the 2 vias coming out the side are 0.15 mm away from the terminal lead. The vias coming out the ends on the land pattern are 0.75 mm away from the terminal leads. That’s 5 times farther away than the vias coming out the sides however some EE engineers will request all 4 vias. Since all the traces and vias are snapped to a 0.5 mm grid, this makes copy/paste much easier to manually fanout all of the 6032 Molded Body Capacitors. The dot grid display is 1 mm and the land pattern is placed on a 0.5 mm grid. All the vias in this illustration fall on a 1 mm snap grid.
See Figure 18 for the 7343 Molded Body Tantalum Capacitor I recommend a larger via size with a 1 mm land size, 0.55 mm hole size and 1.3 mm plane anti-pad. This via can carry more current and you only need two (but the EE will ask for a 3rd one). The illustration in Figure 16 snaps all the vias to a 1 mm grid system. These vias are twice the size of the previous vias but all the same trace/space rules apply. The display grid is 1 mm.
Because the land pattern, traces and the vias are on a 1 mm snap grid, this improves the copy/paste feature for manual fanout of all of the 7343 Molded Body components in your PCB layout.
Before you read this blog ‘Part 2″, read Part 1 White Paper of this series - “PCB Design Perfection Starts in the CAD Library” for the introduction information. Download it here – http://www.mentor.com/products/pcb-system-design/techpubs/download?id=60454
Parts 3, 4, 5 etc. will be posted here over the next couple weeks. I’m really looking forward to your feedback on this subject. I believe that everyone who follows these basic rules will increase productivity levels in their PCB design layouts.
See Figure 6 for the dimensions of a standard 1005 (EIA 0402) component superimposed with its related land pattern. In this case, I decided to break 2 rules –
1. Land size round-off 0.05 mm
2. Land snap grid round-off 1.0 mm
The land center to land center spacing is 1.0 mm which is perfect for 1.0 mm space via fanout and the placement courtyard width is 1.0 mm which is perfect for placing parts 1.0 mm from center to center.
When placing the 1005 in the PCB layout use a 0.1mm grid to optimize the part placement and via fanout.
The 1005 (EIA 0402) was made for 1mm pitch BGA fanout. In Figure 7 you can see 2 different fanout options and one is superior to the other. The fanout coming out the top has all the key features. The vias are 0.25 mm closer to the capacitor component terminals than the typical right/left fanout which decreases impedance and increases capacitance. Also, the top fanout vias snap to a 1 mm grid because the 1005 land pattern was snapped to a 0.1 mm grid system. The 0.5 mm via land (pad) diameter with 0.25 mm hole size and 0.7 mm plane anti-pad is perfect for 0.1mm trace/space technology. See Figure 4. The trace width for the power fanout is 0.3 mm.
1. Land size round-off 0.05 mm
2. Land snap grid round-off 1.0 mm
3. Use the “Least” environment due to component miniaturization
For chip components smaller than 1 mm X 0.5 mm I use the IPC-7351B Least Environment to prevent tombstoning. When 2 pin micro-miniature parts have too much solder volume tombstoning can occur in the reflow oven. The land size for the 0603 should be slightly more than 2 times the terminal lead size.
One of the techniques that can be used to prevent tombstoning for the 0603 (EIA 0201) is to thin the paste stencil from 0.15 mm to a smaller value for every occurrence of this component in the paste mask stencil. See Figure 9. The responsibility of the stencil thickness thinning process is placed on the assembly shop and the stencil manufacturer (not the PCB designer). Assembly shops use various solder alloys that require unique stencil creation.
See Figure 10 for the dimensions of a standard 0603 (EIA 0201) component superimposed with its related land pattern. If you normally use the “Most” environment, my recommendation for the 0603 (EIA 0201) land pattern is to use the “Nominal” environment. The IPC nominal land size for the 0603 is about 3 times the size of the terminal lead. For this 0603 micro-miniature component, stay away from the “Most” environment as the solder volume is more than 4 times greater than the terminal lead footprint.
The 1005 (EIA 0402) & 0603 (EIA 0201) chip components are very compatible with 1 mm pitch BGA. In Figure 11 there are 2 uses for the 1005 and one in-between the vias and one via-in-pad method. Because the 1005 land centers are on 1 mm pitch, the capacitor land (pad) falls directly centered on the via. Via-in-Pad technology will increase PCB cost because these vias need to be plated, filled and surface finish on the capacitor pad. The 0603 fall in-between the vias for the 0.1 mm trace/space technology DRC. This solution will not increase PCB fabrication cost. The dot grid display is 0.05 mm.
IPC does not have a “standard” on drafting items such as silkscreen and assembly outlines and polarity markings yet. There are several types of silkscreen outlines and polarity markings that are used for Non-polarized Chip parts, Polarized Capacitors, Diodes and LED’s.
For a standard Non-polarized chip there are 2 options. See Figure 12 for both options. One is a line that separates the 2 lands. The default size is 0.2 mm and the default silkscreen the land gap is 0.25 mm. The CAD librarian can change both the line width and the gap to achieve placing a line between two lands that only have a 0.3 mm Gap by simply changing the line width and gap rules to 0.1 mm.
See Figure 13 for the silkscreen outline for the Chip Diode. The Chip Diode also has a Post Assembly Inspection Dot so you can visually verify if the assembly inserted the Diode or LED in the correct rotation. The Polarized Chip Capacitor would have the same exact silkscreen outline but without the 0.6 mm bar.
The Assembly Drawing Outlines and Polarity Markings are totally different than the Silkscreen Outlines and Polarity Markings. The first most obvious difference is that the outline shape is 1:1 scale of the component body. This outline can be either the “Nominal” or “Maximum” component body size. Another difference is the Reference Designator is centered inside the component outline and is never moved or relocated. The reference designator default size is 1.5 mm height with a 10% line width.
The Reference Designator and Assembly Outline only change rules for micro-miniature parts. The Assembly Outline will grow as large as the placement courtyard in order to fit the Reference Designator inside the Assembly Outline. When the component gets smaller, the Reference Designator will decrease from the default 1.5 mm height to a sliding scale of values until it fits inside the assembly outline. The reference designator scaling width is always 10% of the height. The various reference designator heights for micro-miniature components are –
· 0.15 mm
· 0.125 mm
· 0.1 mm
· 0.075 mm
· 0.05 mm (this is the smallest human readable text height)
See Figure 14 for the non-polarized and polarized capacitor, diode and resistor assembly outlines and Reference designators. Notice the absence of land pads. From all Chip and Molded Body components, the Land is removed from the SMT padstack to insure that the reference designators are unobstructed. Also, for CAD tools that have this feature, Right Reading Orthogonal is always recommended so when the component is rotated, the reference designator is always flipped to right reading orientation.
I’m curious as how do PCB designers route metric pitch BGA’s on a mil grid system or gridless (which consumes memory and CPU)? I can’t figure why anyone would use a mil grid system for any PCB CAD library construction or PCB design layout when all the SMT component manufacturers are only producing metric pin pitch packages. This is where we note that all chip resistors and capacitors are dimensioned using whole metric numbers. So by design all of them are considered metric based components. i.e.: 1206 = 0.125″ x 0.062″ or 3216 = 3.2mm x 1.6mm for the same component. Which is easier to understand? To me it’s interesting why some PCB designers still use the Imperial measurement system. I’d like to hear from designers and engineers who use the technology combination of metric pin pitch components and mil based part placement and trace sizes & routing grids. How do you do it?
My big secret was to teach all the mechanical engineers and EE engineers the metric measurement system by providing equivalent charts. Even purchasing had to have a metric to Imperial chart for chip components because the BOM had all metric land pattern names but the buyers had to have the inch equivalent names to place an order.
So we had to do for Chips. Notice that 0603 and 0402 appear in both columns -
Metric = Inch
3216 = 1206
2012 = 0805
1608 = 0603
1005 = 0402
0603 = 0201
0402 = 01005
Here is what I’m talking about. This is a table from a component manufacturer that lists the dimensions of a series of resistors in hard metric but all of the component names in the far left column are Imperial units (Type Inches). i.e. the first part is a metric 0402 (0.4mm x 0.2mm) but Panasonic calls it a 01005 (the inch equivalent 0.4mm = 0.0015748″ x 0.2mm = 0.007874). Why doesn’t Panasonic call it for what it really is, 0402?
After successfully transitioned all the engineers then the PCB design process got really easy, faster and simpler. Then when I give the PCB manufacturer all my nice clean metric drawings and metric Gerber and Drill data the first thing they do is convert all units to Imperial to panelize and CAM the job with their mil based DRC rules. Wow, it took longer to CAM my job because of the translation.
When I dig deeper to find out “Why do they do that”, I discover that all the materials like core, copper and prepreg all come in mil based thicknesses and shapes. So that’s where the buck stops! I mean that if overnight all the material providers only produced metric thickness and metric sizes that all of the PCB fabrication shops would be doing metric based manufacturing. The next thing you know they’d be recommending all their customers to produce metric based Gerber and drill data for their new machines made in Europe. (The reason why they’re made in Europe is because there’s no way in this lifetime that any USA manufacturer is going to create a metric based machine. Maybe in another lifetime…) and I digress.
When the PCB fabrication shop starts recommending metric units preferred to their customers that’s when true electronic product development automation will really kick in and maybe we’ll start creating faster, better, more accurate, cheaper products or rather products that today cost $100,000 will only cost $1000. I hope to see the revelation in my lifetime where all design units are the same regardless if it’s Imperial or metric, just pick one and make life easy. 99 nations voted for metric. USA voted to gradually adopt with full conversion by 2015. At least that’s the 1985 Omnibus Act signed by Ronald Regan defines to extend Jimmy Carter’s 1975 Metric Conversion Act which was to convert USA in 10 years and adds another 30 years for the gradual metric conversion one industry at a time. Note that the EU Metric Directive went into effect January 1, 2010 for all weights & measures throughout Europe. The worldwide PCB design industry is 50% converted on the front end and we’re waiting on the back end. The PCB component manufacturers have semi successfully converted to metric units. At least they dimension everything in metric units but some still refer to the Imperial (Inch) name to order the component (like the Panasonic chart above). Very confusing!
Come on PCB suppliers. The electronics industry needs all of you to transition to hard metric to complete the entire loop in the PCB design engineering and manufacturing industry. You are directly responsible for holding the electronics industry back from achieving the highest productivity levels obtainable and standardizing on a single unit system. I do not think the PCB material suppliers have a clue on how much of an impact they have on every electronic product being developed today. I beg you; please make our job easier and put an end to the dual measurement system chaos that EE engineers, mechanical engineers and PCB designers have to deal with every day until you transition. It’s time to stop using the Imperial unit system in the electronics industry and use one measurement system. Every Standards organization in the world has referred to the metric unit system as the ”vastly superior” alternative. So why isn’t everyone listening?
Tags: library tools
About Tom Hausherr's Blog
New component package technology and CAD library standards.
- PCB Design Perfection Starts in the CAD Library – Part 19
- PCB Design Perfection Starts in the CAD Library – Part 18
- PCB Design Perfection Starts in the CAD Library – Part 17
- PCB Design Perfection Starts in the CAD Library – Part 16
- PCB Design Perfection Starts in the CAD Library – Part 15 QFN
- Inch to Metric Conversion Tables for PCB design
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