Posts Tagged ‘CAD Library’

31 March, 2011

Here are some tips about Metric Speak that all PCB designers need to know. “Metric” is not a unit of measure. Metric is a term that describes a measurement system. You use either millimeters or microns for your PCB design units. The proper terminology to describe your working units when using the metric measurement system is millimeters or microns, not metric. Example: When doing PCB layout in Inches or Mils you never refer to working in “Imperial Units”.

Millimeters allow finer (and greater) granularity in the PCB design grid system to optimize board real-estate, part placement, via fanout and routing trace/space features and snap grids. This will be very important in the future of PCB RF Micro-technology. PCB impedance measurements are more accurate in Micron units than “Ounces of Copper” and Mil core/Prepreg dielectric. Use Micron Units to achieve the highest level of accuracy for impedance calculations.

Unfortunately, PCB manufacturers are directly responsible for holding back the progress of the transition to metrication of our industry. When the PCB fabrication companies transitions to the metric system, the entire electronics industry will achieve the peak of “electronic product development automation”. Until then, we’ll plod along using dual units in the land of chaos.

Here is an example of the chaos in the Chip Component family. All Chip names refer to their body length and width. When EIAJ introduced the standard Chip and Molded body component dimensions, only millimeter units were used. A 3216 was 3.2 mm long and 1.6 mm wide. It was very simple. When the data was passed on to EIA in America, they changed all the chip names from millimeters to Inches and a 3216 was renamed 1206 or 0.125” length and 0.062” width (just drop the 3rd place number). Today most component manufacturers dimension all there component packages in millimeters see Table 1 that illustrates Metric vs. Imperial names. You can easily see the confusion in the dual measurement system.

Table 1 - Chip Component Names

Table 1 - Chip Component Names

Let’s start the transition process. 99% of all PCB layouts use vias. See Table 2 for an Inch to Millimeter chart for common via sizes starting with a 0.15 mm hole and growing in 0.05 mm increments. I’ll provide the entire padstack conversion. I intentionally did not add thermal relief data because vias should have a direct plane connection (no thermal relief is necessary). When transitioning from Imperial units to Metric units, always round-off the millimeter values in 0.05mm increments for normal resolution. If you’re working on extremely dense hand held device technology, round-off to the nearest 0.01 mm. For PCB design, there is no reason to go more than 2 places to the right of the decimal point for the present. 0.01 mm = 0.0003937”

Table 2 - Via Padstack Technology

Table 2 - Via Padstack Technology

 Table 3 illustrates 4 common inch based part placement grids and their millimeter equivalent.  The common rule in placing parts in millimeters is to always stay one place to the right of the decimal or 0.1 mm increments.

Table 3 - Component Placement

Table 3 - Component Placement

 Table 4 provides all the common trace/space technology and routing snap grids. The common rule when working in millimeters is to always use a 0.05 mm routing grid. Most component lead pin pitches are 0.05 mm increments and IPC-7351B land (pad) sizes and snap grids are in 0.05 mm increments. This totally optimizes trace routing and eliminates wasted PCB real-estate. Everything fits together tighter than Lego building blocks.  Notice that in the inch units, a gridless shape-based option is used, but in millimeters all objects can easily snap to a grid and still achieve maximum density solutions. I provide 3 various route snap grid solutions for the various trace/space rules.

Note: Inch based routing grids are evenly divisible into 0.100” while millimeter based routing grids are evenly divisible into 1 mm.

Table 4 - Trace Widths & Optimum Routing Grids

Table 4 - Trace Widths & Optimum Routing Grids

 Table 5 provides the PCB material equivalents. Note that the various columns are not related to each other. Each column describes a specific PCB feature. In the first column “Board Thickness” is common PCB finished material thicknesses and the metric equivalent rounded off to the nearest 0.1 mm. The second column is copper weight in ounces and their micron equivalent. Using microns to describe copper thickness is better than using weight. The third and forth columns go together. Column 3 defines the type of hole and column 4 provides the PCB fabrication tolerance for each different hole type in the chart.

Table 5 - PC Board Criteria

Table 5 - PC Board Criteria

 Table 6 is common plated through-hole padstacks for component leads and their inch to millimeter conversion. All hole, pad and plane clearance values are in 0.05mm increments. The Solder Mask is the same value as the outer layer pads. This padstack information was taken from the proportional padstack table and you can download it here under “Appnote 10836: Proportional Through-hole Padstacks” – http://www.mentor.com/products/pcb-system-design/library-tools/lp-wizard/import-docs

Note: this downloadable chart only contains millimeter values and not the inch equivalents in Table 6.

Table 6 - Common Plated Through-hole Padstacks

Table 6 - Common Plated Through-hole Padstacks

 Table 7 is common non-plated through-hole padstacks and their inch to millimeter conversion. All hole, pad and plane clearance values are in 0.05mm increments. The Solder Mask is the same value as the hole size to allow the PCB manufacturer to oversize it per their specific fabrication tolerances. Notice that the pad size for every padstack is 1.00 mm. Because the holes are not plated, the hole size is typically larger than the hole size. Also, there is no reason to have multiple pad sizes when the pad is eventually drilled away. The only reason for having a pad in a non-plated padstack is display a marker as a guide for the hole location. The PCB manufacturer does not need the pad in the padstack, but sometimes when there is no pad (but there is a drill hole) the manufacturer might question if the hole is valid. Of course there is no thermal relief required in non-plated hole padstacks.

Table 7 - Common Non-Plated Through-hole Padstacks

Table 7 - Common Non-Plated Through-hole Padstacks

I want to note that the LP Calculator automatically performs all of these through-hole padstack calculations for you and provides 5 different options –

  1. Proportional Environment
  2. IPC-7251 Most Environment
  3. IPC-7251 Nominal Environment
  4. IPC-7251 Least Environment
  5. User Defined Environment Rules 

You can get a free LP Calculator by signing up for a 10-day evaluation of LP Wizard here – http://www.mentor.com/products/pcb-system-design/library-tools/lp-wizard/lp-wizard-eval

After the LP Wizard 10-day evaluation is over, the LP Wizard program will run in “Demo Mode” as LP Calculator.

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21 January, 2011
0.5 mm Pitch BGA Routing Solution

There is a reasonable solution for via fanout and a routing solution for the 0.5 mm pitch BGA but we need to think outside the box. The board thickness is an important factor because it affects the hole plating aspect ratio. If you use a 1 mm PCB thickness and want to achieve a 7:1 aspect ratio (this is common among all manufacturers) then the smallest hole size is 0.15 mm (6 mil). There are manufacturer’s that can hard drill a 0.15 mm (6 mil) hole through a 1 mm PCB. There are manufacturers that claim they can easily handle 10:1 aspect ratios. This means that they can drill 0.15 mm (6 mil) holes through 1.57 mm (0.062”) thick PCB material and plate the hole without problems. Drilling all the way through the PCB is important because sequential lamination is an expensive process.

For all via-in-land technology, a thermal relief on the voltage and ground plane connections must be used to prevent cold solder joints. A direct via-in-land connection to the plane will dissipate the heat required to melt the solder around the BGA ball and this will result in a cold or cracked solder joint. The exception to this rule is if the via only contacts a single plane with ½ OZ. copper or less.

If traces are routed between pins of the 0.5 pitch BGA land, the solder mask must be a 1:1 scale to create a “solder mask defined” BGA land. In this way, the traces between the lands will be protected from exposure and possible short circuiting.

The 0.5 mm pitch BGA via-in-land drill hole through the PCB is leading edge technology. When laser drills are capable of producing 0.125 hole sizes entirely through the board and PCB manufacturers can accurately fill the holes with conductive metal epoxy, this technology will become mainstream.

Micro-via technology is the mainstream solution for 0.5 pitch BGA components when a 0.1 – 0.15 laser hole is drilled one, two or three layers deep. This involves sequential lamination but before we get to that subject let’s discuss the via fanout process. Using via-in-land technology, we must offset the drill holes to create adequate routing channels. This is the only routing solution that I know of to maintain manufacturability. See Figure 1 for a via fanout solution for the outer layer. Notice that you will have to add additional copper land for via annular ring.

Figure 1 – 0.5 mm Pitch BGA Via-in-Land

Figure 1 – 0.5 mm Pitch BGA Offset Via-in-Land

The vias are 0.05 mm offset from the land center and grouped together.

See Figure 2 for a via fanout solution for the inner layers. The most important feature here is the 0.1 mm (4 mil) trace width & 0.1 mm space between Trace to Via and Via to Via.

Figure 2 – 0.5 mm Pitch BGA fanout Inner Layers

Figure 2 – 0.5 mm Pitch BGA fanout Inner Layers

 

 

 

Depending on how many rows and columns in the BGA will determine the number of routing layers required.  

Sequential lamination process requires the inner layers to be laminated, drilled and plated in Phase 1 and then add 2 additional outer layers and back through lamination, drill and plate in Phase 2. Then add 2 additional outer layers and back through lamination, drill and plate in Phase 3. See Figure 3 for the various phases of sequential lamination.

Figure 3 - Sequential Lamination

Figure 3 - Sequential Lamination

Let me try to explain why sequential lamination is so expensive and why most people avoid it unless they absolutely need it for high volume production. The PCB inner layer manufacturing goes through the entire fabrication process in Phase 1. Then the first HDI layers that are added to the PCB have to go through the entire fabrication process over again. This basically doubles the cost in Phase 2. Then the second HDI layers that are added to the PCB have to go through the entire fabrication process over again. This basically triples the cost in Phase 3 and the manufacturer’s say that they are basically building the same PC board 3 times.

There are 2 methods of via drilling for sequential lamination. Staggered vias and stacked vias. See Figure 4 for the staggered micro-via process.

Figure 4 – Staggered Micro-vias

Figure 4 – Staggered Micro-vias

Notice in the Staggered Micro-via picture that the via plugging color is green. This could be an epoxy fill because the vias are staggered and there is no manufacturing stress. Discuss staggered vs: stacked vias with your manufacturer to find out if one technique is less expensive than the other. See Figure 5 for the stacked micro-via process.

Figure 5 – Stacked Micro-vias

Figure 5 – Stacked Micro-vias

The Stacked Micro-vias must be filled with conductive metal to prevent the outer laser drill from damaging the inner layer hole. See Figure 6.

Figure 6 – Stacked Micro-via Conductive Fill

Figure 6 – Stacked Micro-via Conductive Fill

The latest generation technology developed by Dow Electronic Materials for advanced via fill plating, MICROFILL™ EVF Via Fill provides enhanced via filling, with simultaneous through-hole plating, at surface thicknesses unattainable. Formulated to operate in existing equipment over a broad range of operating conditions, MICROFILL™ EVF Copper Via Fill is suitable for HDI applications. It is proved by sufficient experience that MICROFILL™ EVF could help to reduce 20% plating thickness and helps to improve varied plating defects. See Figure 7 for stacked micro-via conductive fill techniques. To read more on this topic see:  http://www.rohmhaas.com/wcm/information/em/interconnect/microfill/index.page

Figure 7 – Stacked Micro-via Conductive Fill

Figure 7 – Stacked Micro-via Conductive Fill

Notice the lower right image in Figure 7 that shows a 0.15 mm via hole going all the way through a 1 mm thick PCB with 20um (0.000787”) or ½ OZ. copper plating thickness. The normal hole plating thickness on an average PCB is 25um (0.001″) or 1 mil.

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14 January, 2011
CAD Library Zero Component Orientations
 
In 2005 IPC and IEC (International Electrotechnical Commission) established a joint standard for land pattern geometries (IPC-7351/IEC 61188-5-1). In order to maintain a consistent method where these two important standards describe the component mechanical outlines, and their respective mounting platforms, a single concept must be developed that takes into account various factors within the global community.

The land pattern standards clearly define all the properties necessary for standardization and acceptability of a “One World CAD Library”. The main objective in defining a one world CAD library is to achieve the highest level of “Electronic Product Development Automation”. This encompasses all the processes involved from engineering to PCB layout to fabrication, assembly and test. The data format standards need this type of consistency in order to meet the efficiency that electronic data transfer can bring to the industry.

Many large firms have spent millions of dollars creating and implementing their own unique standards for their own “Electronic Product Development Automation”. These standards are proprietary to each firm and are not openly shared with the rest of the industry. This has resulted in massive duplication of effort costing the industry millions of man hours in waste and creating industry chaos and global non-standardization.

The Land pattern standards (both IPC-7351 and IEC 61188-5-1) put an end to the “Proprietary Intellectual Property” and introduce a world standard so every electronics firm can benefit from Electronic Product Development Automation. The data format standards (IPC-2581 and IEC 61182-2) are an open database XML software code that is neutral to all the various CAD ASCII formats. For true machine automation to exist, the world desperately needs a neutral CAD database format that all PCB manufacturing machines can read.

One of the factors in global standardization is that of establishing a CAD component description and land pattern standard that adopts a fixed Zero Component Orientation so that all CAD images are built with the same rotation for the purpose of assembly machine automation. The IPC-7351 indicates that in the CAD library, all pin 1 locations are in the upper left corner for multiple pin components and pin 1 on left for 2-pin components. Figure 1 represents IPC-7351 default and IEC 61188-7 “Level A” zero component orientation.

Figure 1 - IPC-7351 Pin 1 Upper Left (IEC 61188-7 Level A)

Figure 1 - IPC-7351 Zero Orientation with Pin 1 Upper Left (IEC 61188-7 Level A)

 In May 2009, IEC land pattern committee voted and approved a new Level B Zero Component Orientation and redefined the IPC-7351 Zero Orientation as Level A. The new IEC 61188-7 defines Zero Component Orientation pin 1 locations in the bottom left corner except 2-pin components Pin 1 is on the left side and labeled it “Level B”. Figure 2 represents IEC 61188-7 “Level B” zero component orientation.

Figure 2 – IEC 61188-7 “Level B” Zero Orientation with Pin 1 in Lower Left Corner

Figure 2 – IEC 61188-7 “Level B” Zero Orientation with Pin 1 in Lower Left Corner

  Since the basic rules allow two variations of levels in the description of the CAD system library, it is a mandatory requirement to define which level was used (level A or Level B) for the component descriptions in the data file. This information is a mandatory requirement in the Header of any file that incorporates land patterns using these principles of zero-based orientation. See Figure 3 for the “Level A” zero orientation and machine rotation.

Figure 3 – Example of “Level A” Orientation Concepts

Figure 3 – Example of “Level A” Orientation Concepts

The industry association EIA (Electronics Industry Association) is responsible for component descriptions and tape and reel orientation in the EIA-481-D standard. EIA has tried valiantly to influence the industry by making good standards that describe the component outlines and how they should be positioned in the delivery system to the equipment on the manufacturing floor. Suppliers of parts have either not adhered to the recommendations or have misunderstood the intent and provided their products in different orientations.

Here are the EIA-481-D standard tape and reel pictures (Figures 4 & 5) that illustrate quadrant designations.

Figure 4 – EIA-481-D Quadrant Designations

Figure 4 – EIA-481-D Quadrant Designations

 

Figure 5 – CAD Library Zero Orientation Quadrants

Figure 5 – CAD Library Zero Orientation Quadrants

IPC and IEC use consistent rotations throughout their standard where EIA uses multiple rotation variations

  • IPC-7×51 “Level A” uses Quadrant 2 for Pin 1 Upper Left and Quadrants 2-4 for Upper Center
  • IEC 61188-7 “Level B” uses Quadrant 1 for Pin 1 Lower Left and Quadrants 1-2 for Left Center
  • EIA-481-D uses Quadrant 1 for Pin 1 Lower Left BGA, SOIC, SOP, QFN (rectangle), DIP
  • EIA-481-D uses Quadrant 2 for Pin 1 Upper Left TO-252, TO-263, QFN (square), TSOP
  • EIA-481-D uses Quadrant 3 for Pin 1 Lower Right for all SOT and miniature parts
  • EIA-481-D uses Quadrants 1-2 (Pin 1 Left Center) for PLCC, LCC
  • None of the 3 standards use Quadrant 4 for Pin 1 locations

The main purpose of creating the land pattern standards is to achieve reliable solder joint formation platforms; the reason for developing the data transfer structure is to improve the efficiency with which engineering intelligence is converted to manufacturing reality. Even if the neutral CAD format can drive all the manufacturing machines, it would be meaningless unless the component description standard for CAD land patterns was implemented with some consistency. Zero Component Orientation has a key role in machine automation.

The easiest way to illustrate the 3 world standards is to list every component family and their respective Zero Component Orientation for each standard. The big question is – Which standard will prevail?  

Figure-6 IPC, IEC & EIA Zero Component Orientations

Figure-6 IPC, IEC & EIA Zero Component Orientations

Note: The EIA-481-D rotations marked in Red conflict with both IPC and IEC

Download the complete IPC-7351B Electronic Component Zero Orientation document here – http://www.mentor.com/resources/appnotes/upload/zero-orientation-cad-libaray.pdf

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8 January, 2011

The BGA or Ball Grid Array has been around since the 1980′s but the pin pitch started out with 1.5 mm and then quickly went to 1.27 mm (50 mils) for about 15 years. Then in the late 1990′s, the 1 mm pitch BGA was introduced and every couple years a smaller pin pitch was introduced. Today 0.4 mm pitch BGA’s are in every cell phone and 0.3 mm pitch BGA’s are the next generation. Figure 1 displays the lead type for this component family.

Figure 1

Figure 1

There are 2 types of BGA Ball Leads –

  1. Non-collapsing – this is normally 0.5 mm pitch and smaller, where the Land (pad) is larger than the ball to allow for via-in-pad technology and provide an adequate annular ring. The solder mask can be the same size as the Land. In some cases the Land for fine pitch BGA’s is solder mask defined where the solder mask encroaches slightly over the land. This provides protection for any trace routing between the lands but the most significant benefit is to help secure the Land to the PCB. During cell phone “drop testing”, the BGA solder joint normally holds better than the land to the Prepreg. i.e.: drop tests prove that the non-solder mask land will rip from the PCB before the solder joint breaks. So the solder mask defined land is secured better to the PCB for drop testing.
  2. Collapsing - this is normally 0.65 mm pitch and higher, where the Land (pad) is smaller than the Ball size to allow the Ball to collapse around the sides of the Land. This requires a non-solder mask defined Land where the solder mask must be larger than the Land.

 See Figure 2 for examples of non-collapsing and collapsing BGA balls.

Non-collapsing and Collapsing BGA Balls

Figure 2: Non-collapsing and Collapsing BGA Balls

The BGA Land (pad) size is determined by the ball size as seen below in Table 1 from IPC-7351B land pattern standard. Notice the correlation between the “reduction” and the “land pattern density level”. The 3 density levels change the land size reduction percentage, but they also determine the Placement Courtyard Excess. See Table 3.

Table 1: Land Approximation for Collapsible Solder Balls

Table 1: Land Approximation for Collapsible Solder Balls

Note:  The IPC-7351B LP Calculator Uses this chart for calculations

It is very important to note that IPC prefers the Maximum Material Condition for all BGA Land sizes; they do not use the Nominal Land Diameter, but do use the Maximum Land Variation Diameter (notice the Bold numbers in the Chart “Land Variation” column). Notice that the standard ball sizes are in 0.05 mm increments until the pin pitch hits 0.5 mm and less. However, even though the world standards try to keep BGA balls sizes in 0.05 mm increments, component manufacturer’s sometimes do not adhere to the standard and create BGA ball sizes in 0.01 mm increments, but I have never seen a BGA ball size less than a 0.01 mm increment. Also, the BGA pin pitches are in 0.05 mm increments. As a result, the BGA land (pad) sizes are in 0.05 mm increments including the via fanout padstacks and hole sizes.

IPC-7351B has a 3-Tier BGA formula for Placement Courtyard Excess that uses the BGA ball size to calculate an adequate placement courtyard for BGA rework tools. If the BGA has a large ball size, larger rework equipment is necessary to unsolder the increased solder volume.

With a small ball size, the placement courtyard can be smaller as less heat is then required to unsolder the BGA component for rework.  However, the end user may not plan to rework the BGA if it fails.  In that case, there is no need to have a robust placement courtyard, but a recommended minimum placement courtyard excess is 0.5 mm.

Non-collapsing” ball BGA components

Table 2 below is used for land size calculations for non-collapsing BGA balls.

Table 2: Non-Collapsing BGA Ball Land Calculations

Table 2: Non-Collapsing BGA Ball Land Calculations

It is very important to note that IPC prefers the Maximum Material Condition for all BGA Land Sizes, meaning that the Maximum Land Variation Diameter is used; not the “Nominal Land Diameter”.

Figure 3 is a 0.5 pitch non-collapsing BGA ball. Instead of shrinking, the non-collapsing land size gets larger to handle the solder volume that creates the solder joint. This technology is new to the electronics industry and was created as a solution for lead-free BGA balls and via-in-pad technology as a routing solution for fine pitch BGA components.

Figure 3: Non-Collapsing 0.5 mm pitch BGA

Figure 3: Non-Collapsing 0.5 mm pitch BGA

  • Via-in-Land Technology          Trace/Space & Grid Data
  • BGA Ball Size: 0.15                               Trace Width: 0.075
  • BGA Land Dia: 0.275                          Trace/Trace Space: 0.075
  • Hole Size: 0.15                                       Trace/Via Space: 0.075
  • Thermal Relief Required                   Trace/BGA Land: 0.075
  • Plane Clearance: 0.425                     Routing Grid: 0.05
  • Solder Mask: 1:1 scale                        Part Place Grid: 1

IPC-7351A has a 3-Tier BGA formula for Placement Courtyards that uses the BGA ball size to calculate an adequate placement courtyard for BGA rework tools.

If the BGA has a large ball size, larger rework equipment is necessary to unsolder the large solder volume. With a small ball size, the placement courtyard can be smaller as less heat is then required to unsolder the BGA component for rework.  However, the end user may not plan to rework the BGA if it fails.  In that case, there is no need to have a robust placement courtyard.

Table 3 below represents the 3-Tier scenario and the different placement courtyard excess size determination.

Table 3: BGA Density Levels for Placement Courtyard Size Determination

Table 3: BGA Density Levels for Placement Courtyard Size Determination

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18 November, 2010
Placement Courtyards
I promised to post “The Anatomy of a Land Pattern” in Part 6 of my blog, but the subject must be broken down into mini-blogs as the topic covers too many issues. So let’s start with the IPC-7351B “Placement Courtyard”.

The IPC-7351B standard only focuses on 2 two major aspects of the CAD library:

  1. The land size and spacing
  2. Placement courtyard

All of the other aspects of the CAD library part such as silkscreen & assembly outlines, polarity markings, ref des, centroid marking, etc. are considered user definable drafting items. This includes all of the rules that pertain to these items such as line widths, silkscreen to land spacing, polarity sizes, ref des height, etc. are not part of the standard. But the Placement Courtyard Boundary is defined in the IPC-7351B standard, but the line width used to create the outline is user definable. The default solder mask and paste mask values are mentioned in the IPC-7351 as to be 1:1 scale of the land size, but this is only a recommendation.

See Courtyard Determination pictures below to see the 3 outlines defined by IPC-7351 as:

  1. Maximum Component Boundary
  2. Minimum Placement Courtyard
  3. Courtyard Manufacturing Zone
Surface Mount Courtyard Determination

Surface Mount Courtyard Determination

Plated Through-hole Courtyard Determination

Plated Through-hole Courtyard Determination

Here are the standard spacing rules from the Maximum Component Boundary to the Minimum Placement Courtyard:

  1. Least Environment = 0.1 mm
  2. Nominal Environment = 0.25 mm
  3. Most Environment = 0.5 mm

There are different Placement Courtyard spacing rules for Grid Array packages based on ball size:

  1. Ball size above 0.50 mm = 2 mm
  2. Ball size between 0.50 mm & 0.25 mm = 1 mm
  3. Ball size below 0.25 mm = 0.5 mm

One of the key aspects of the placement courtyard is that it allows room for rework. In the case of the BGA’s, the larger the Ball Size, the larger the heat nozzles and removal equipment is for getting around and under the component to unsolder the contacts. An important note to make here is that if you have no intentions of ever reworking (remove and replace) a BGA component then the 2 mm placement courtyard is not necessary and a 0.5 mm courtyard excess is OK. This also is relevant to the “Most Environment” where the minimum courtyard excess is 0.5 mm on all SMT land patterns. i.e.: the military and medical instrument industry might use the Most Environment and require “Class 3″ High Reliability Electronic Products where continued high performance is critical and product downtime cannot be tolerated. The “Class 3″ fabrication is very expensive and if a component on the PCB fails, rework becomes necessary to reduce cost. Rework requires additional land pattern placement courtyard excess to allow adequate space for rework equipment. Alternatively, the “Least Environment” for High Density PCB Layout, like handheld devices, has a courtyard excess of 0.1 mm with no room for rework equipment. So if a component fails in your Cellular Phone it will not be sent back to the shop for rework, but instead, it will be discarded.

The Placement Courtyards can be placed next to each other so the outline overlaps, however you need to discuss this with your assembly shop if they require an additional Manufacturing Zone for their process. The Placement Courtyard round-off snap grid is 0.5 mm. The question of “why don’t you place the silkscreen outline outside the land pattern boundary” is a FAQ and this is the answer - “It is important that all silkscreen outline data be located inside the Placement Courtyard”.

This includes the Post Assembly Inspection Dot, which sometimes gets partially placed outside the placement courtyard. This is why in the upcoming IPC-2614 for Board Fabrication Documentation and drafting standards the “Post Assembly Inspection Dot” will become the “Post Assembly Inspection Line” and it will look like this to keep them inside the Placement Courtyard:

Dip & SOP Post Assembly Inspection Line

DIP & SOP Post Assembly Inspection Line

The Placement Courtyard or Courtyard Excess is the smallest area that provides a minimum electrical and mechanical clearance of the maximum extremities of the land pattern and/or the component body. However it is the responsibility of the user to verify the land patterns used for achieving an undisturbed mounting process including testing and an ensured reliability for the product stress conditions in use.
For many through-hole parts and connectors, the placement courtyard will follow the contour of the component body outline and land pattern.
Axial Lead Courtyard

Axial Lead Courtyard

Most Enterprise CAD tools like Mentor Expedition have a different DRC checking feature that the user can define the component type to component type spacing rules. In this case, the placement courtyard excess should be turned off and the placement courtyard would be identical to the Maximum Component Boundary.

Enterprise CAD Tool Courtyard

Enterprise CAD Tool Courtyard

The Enterprise CAD tool placement courtyard is not defined in the IPC-7351 standard. This concept is based on the Enterprise CAD tools ability to determine various component body to body spacing that is user definable.

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