2 December, 2010

# PCB Design Perfection Starts in the CAD Library – Part 8

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Padstack creation is something every CAD tool will eventually have to incorporate because it expedites and optimizes CAD library construction. You can download the IPC-7351B Padstack Naming Convention here – AppNote 10833: IPC-7251 & 7351 Padstack Naming Convention or http://www.mentor.com/products/pcb-system-design/library-tools/lp-wizard/import-docs

The SMT Padstack is easy –

• Top Land
• Top Assembly

Part 7 of this blog explains the Land Calculation for SMT land patterns, so let’s discuss Plated Through-hole calculations in this segment.

The Through-hole (PTH) Padstack is complex –

• Drill Hole
• Top Assembly
• Top Land
• Inner Land
• Plane Thermal Relief
• Bottom Land
• Bottom Assembly

Here is a picture of a through-hole padstack.

The PTH padstack creation can be fully automated via the maximum lead diameter.

In the IPC-2222 standard there is a hole size calculation chart –

IPC-2222 Table 9-3

Once you calculate the hole size, the minimum annular ring is 0.05 mm.

IPC-2221 Minimum Annular Ring

Next we need to add the IPC-2221 Minimum Fabrication Allowance to the pad size.

IPC-2221 Table 9-1

So the Minimum Annular Ring X 2 + Minimum Fabrication Allowance + Maximum Lead + Hole Over Lead = Pad Diameter

Next we need to calculate the Plane Thermal Relief ID, OD and Spoke Width sizes.

Thermal Relief Calculations

The Plane Anti-pad or Plane Clearance is the same size as the Thermal Relief OD (Outside Diameter).

In both the SMT and PTH padstack, the IPC recommended Solder Mask and Paste Mask size is 1:1 scale of the Top and Bottom land size. The PCB fabrication shop can automatically oversize (swell) the solder mask to any size they need to insure high yield production per their specific manufacturing capabilities. This is where automation of padstack generation comes in. The entire concept is to generate a padstack that meets the environment class of your design specification.

The IPC-7251 Through-hole land patterns have the capability of accommodating all three performance classiﬁcations.

Producibility Levels: When appropriate this standard will provide three design producibility levels of features, tolerances, measurements, assembly, testing of completion or veriﬁcation of the manufacturing process that reﬂect progressive increases in sophistication of tooling, materials or processing and, therefore progressive increases in fabrication cost. These levels are:

• Level A General Design Producibility – Preferred [Maximum land\lead to hole relationship]
• Level B Moderate Design Producibility – Standard [Nominal land\lead to hole relationship]
• Level C High Design Producibility – Reduced [Least land\lead to hole relationship]

The producibility levels are not to be interpreted as a design requirement, but a method of communicating the degree of difficulty of a feature between design and fabrication/assembly facilities. The use of one level for a speciﬁc feature does not mean that other features must be of the same level. Selection should always be based on the minimum need, while recognizing that the precision, performance, conductive pattern density, equipment, assembly and testing requirements determine the design producibility level. The numbers listed within the tables of IPC-7251 are to be used as a guide in determining what the level of producibility will be for any feature. The speciﬁc requirement for any feature that must be controlled on the end item shall be speciﬁed on the master drawing of the printed board or the printed board assembly drawing.

Density Level A: Maximum Land/Lead to Hole Relationship The ‘maximum’ land pattern conditions have been developed to accommodate the most robust producability of the solder application method. The geometry furnished may provide a wider process window for solder processing. The level A land patterns are usually associated with low component density product applications.

Density Level B: Nominal Land/Lead to Hole RelationshipProducts with a moderate level of component density may consider adapting the ‘median’ land pattern geometry. The median land patterns furnished for all device families will provide a robust solder attachment condition for most soldering processes and should provide a condition suitable for wave, dip, drag or reﬂow soldering.

Density Level C: Least Land/Lead to Hole RelationshipHigh component density typical of portable and hand-held product applications may consider the ‘minimum’ land pattern geometry variation. Selection of the minimum land pattern geometry may not be suitable for all product use categories.

The “Proportional” PTH Padstacks are a mixture combination of all the IPC Levels. Small holes use Level C and medium hole sizes use Level B and large hole sizes use Level A. When a hole size exceeds 2 mm, the Proportional padstack annular ring will incrementally grow with every hole size.  I have used the proportional padstacks for the past 20 years and it is proven technology that works. Its flexible flow is more compliant with the PTH components and their pin pitch density. The main point is that Proportional padstacks meet or exceed the IPC-7251 standard.

Note: the “Producibility Levels” are not necessarily related to the IPC Preformance Classifications. i.e.: The IPC-7251 land patterns have the capability of accommodating all three performance classiﬁcations.

IPC Performance Classifications: Three general end-product classes have been established to reﬂect progressive increases in sophistication, functional performance requirements and testing/inspection frequency. It should be recognized that there may be an overlap of equipment between classes.

The end product user has the responsibility for determining the ‘‘Use Category’’ or ‘‘Class’’ to which the product belongs. The contract between user and supplier shall specify the ‘‘Class’’ required and indicate any exceptions or additional requirements to the parameters, where appropriate.

Class 1 General Electronic Products – Includes consumer products, some computer and computer peripherals, and hardware suitable for applications where the major requirement is function of the completed assembly.

Class 2 Dedicated Service Electronic – Products Includes communications equipment, sophisticated business machines, and instruments where high performance and extended life is required, and for which uninterrupted service is desired but not mandatory. Typically the end-use environment would not cause failures.

Class 3 High Reliability Electronic Products – Includes all equipment where continued performance or performance-on-demand is mandatory. Equipment downtime cannot be tolerated, end-use environment may be uncommonly harsh, and the equipment must function when required, such as life support systems and other critical systems.

24 November, 2010

# PCB Design Perfection Starts in the CAD Library – Part 7

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Land Calculations

IPC-7351 for SMT technology defines the rules for creating optimized land pattern CAD library parts using a 3-Tier system – Least (high density), Nominal (controlled environment) and Most (ruggedized & shock resistant). Many PCB designers and CAD Librarians have heard about the IPC-7351B standard, but few people know how they work. The IPC LP Calculator has made life easy for the PCB design industry by automatically generating accurate land pattern data derived from component dimensions. Part 7 of this series will describe the basic fundamental aspects of defining the optimized land (pad) size for a CAD library part and the mathematical model of the LP Calculator.

These 7 factors are used to calculate the optimum Land Size –

1. Component Body Tolerance
2. Component Terminal Tolerance
3. Fabrication Tolerance
4. Placement Tolerance
5. Land Size Round-off
6. Land Spacing Round-off
7. Solder Joint Goals for Toe, Heel and Side
IPC-7351 identifies two component body dimensions “A” (body width) & “B” (body length).  The one SMT Component Body Tolerance that affects the land pattern is the minimum and maximum sizes of the component “Lead Span” (the dimension from lead tip to lead tip) dimension “L”. This varies for different component packages. For Gull Wing or J-Lead it’s the distance from outside lead tip to tip. For Chip Resistors or Capacitors it’s the full tolerance of the overall body. The picture below represents the “L” dimension of a Gull Wing lead component.

The Component Terminal Tolerance is the size of the metalized area that actually touches the land area. IPC refers to this as the component footprint. The footprint must compensate for the minimum and maximum lead tolerance for the calculation of an optimized Land Size. The component lead footprint is then synchronized with the appropriate land pattern.

Component Terminal Tolerance

The Fabrication (Manufacturing) Tolerance compensates for the fabrication allowance for etch back. By adding a fabrication tolerance, we calculate the land area that we need after the fabrication etching process. If your manufacturer over-sizes the land areas during the CAM process to compensate for their own etching tolerances, this is referred to as “double tolerance” because of double compensation for the same allowance. Ask your manufacturer if they over-size the land features. If they do, tell them that you already compensated for that in your CAD library. The IPC-7351 fabrication tolerance is 0.05mm.

Fabrication Tolerance

The Placement (Assembly) Tolerance compensates for the pick and place machine accuracy. When parts are manually placed or machine placed, there is a small margin of placement accuracy that must be accounted for. The IPC-7351 assembly tolerance is 0.05mm.

Land Place (Spacing) Round-off relates to the land center to land center spacing. The goal in the IPC-7351 is to place all lands on a 0.05mm grid, so the space between the land span is rounded to 0.1mm increments so that the distance from the center of the land pattern to the center of the land is in 0.05mm increments. This plays a critical role in trace routing to achieve the highest packing density. In this picture example of a common Chip Component, the land snap grid is 0.05 mm from the center of the part to the center of the lands. The C1 & C2 dimensions.

Land Place and Size Round-off

Land Size Round-off is the value that the land size rounds up or down to. The IPC-7×51 standards round  land sizes to 0.05mm increments with the exception of micro-miniature component packages that are typically less than 1.6mm in size. The micro-miniature part land size round-off is set to 0.01mm increments. In the picture above, the “X” & “Y” dimensions are rounded off in 0.05 mm increments. Even the land corner radius is rounded in 0.05 mm increments.

Solder Joint Goals for Toe are usually the outside the component lead with two exceptions, the J-Lead and the Molded Body components the Toe is under the component body. The Heel goals are normally on the inside of the component lead and the side goals are for both sides of the component lead.  In Part 5 of this series I listed the component Lead Forms. Every lead form has it’s unique solder joint goal table. Here is a sample table for the Least, Nominal and Most “Toe, Heel and Side” goals and the Placement Courtyard Excess for the Gull Wing component family. Notice the Round-off factor is in 0.05 mm increments.

Gull Wing Solder Joint Goal Table

When all of the Tolerances, Round-offs and Solder Joint goals are applied the end result is a perfect land pattern.

Land Pattern & Component with Tolerances

If all the Tolerances and Solder Joint Goals were removed from the mathematical model, the component lead would be equal to the land size. This is the starting point for all land size calculations. The picture below illustrates a Chip Component (black) without Tolerances, Round-offs, or Solder Joint Goals and the land size (cyan).

Land Pattern & Component with no Tolerances

The resulting solder joint for a chip component should look similar to this picture. Note that the component terminal never touches the land. There must be solder paste between the component lead and the land to form the best solder joint. Here’s a note from the IPC J-STD-001D “Requirements for Soldered Electrical and Electronic Assemblies”. Section 4.14 Solder Connection: All solder connections shall indicate evidence of wetting and adherence where the solder blends to the solder surface.

Chip Solder Joint