Posts Tagged ‘BGA’
There is a reasonable solution for via fanout and a routing solution for the 0.5 mm pitch BGA but we need to think outside the box. The board thickness is an important factor because it affects the hole plating aspect ratio. If you use a 1 mm PCB thickness and want to achieve a 7:1 aspect ratio (this is common among all manufacturers) then the smallest hole size is 0.15 mm (6 mil). There are manufacturer’s that can hard drill a 0.15 mm (6 mil) hole through a 1 mm PCB. There are manufacturers that claim they can easily handle 10:1 aspect ratios. This means that they can drill 0.15 mm (6 mil) holes through 1.57 mm (0.062”) thick PCB material and plate the hole without problems. Drilling all the way through the PCB is important because sequential lamination is an expensive process.
For all via-in-land technology, a thermal relief on the voltage and ground plane connections must be used to prevent cold solder joints. A direct via-in-land connection to the plane will dissipate the heat required to melt the solder around the BGA ball and this will result in a cold or cracked solder joint. The exception to this rule is if the via only contacts a single plane with ½ OZ. copper or less.
If traces are routed between pins of the 0.5 pitch BGA land, the solder mask must be a 1:1 scale to create a “solder mask defined” BGA land. In this way, the traces between the lands will be protected from exposure and possible short circuiting.
The 0.5 mm pitch BGA via-in-land drill hole through the PCB is leading edge technology. When laser drills are capable of producing 0.125 hole sizes entirely through the board and PCB manufacturers can accurately fill the holes with conductive metal epoxy, this technology will become mainstream.
Micro-via technology is the mainstream solution for 0.5 pitch BGA components when a 0.1 – 0.15 laser hole is drilled one, two or three layers deep. This involves sequential lamination but before we get to that subject let’s discuss the via fanout process. Using via-in-land technology, we must offset the drill holes to create adequate routing channels. This is the only routing solution that I know of to maintain manufacturability. See Figure 1 for a via fanout solution for the outer layer. Notice that you will have to add additional copper land for via annular ring.
See Figure 2 for a via fanout solution for the inner layers. The most important feature here is the 0.1 mm (4 mil) trace width & 0.1 mm space between Trace to Via and Via to Via.
Depending on how many rows and columns in the BGA will determine the number of routing layers required.
Sequential lamination process requires the inner layers to be laminated, drilled and plated in Phase 1 and then add 2 additional outer layers and back through lamination, drill and plate in Phase 2. Then add 2 additional outer layers and back through lamination, drill and plate in Phase 3. See Figure 3 for the various phases of sequential lamination.
Let me try to explain why sequential lamination is so expensive and why most people avoid it unless they absolutely need it for high volume production. The PCB inner layer manufacturing goes through the entire fabrication process in Phase 1. Then the first HDI layers that are added to the PCB have to go through the entire fabrication process over again. This basically doubles the cost in Phase 2. Then the second HDI layers that are added to the PCB have to go through the entire fabrication process over again. This basically triples the cost in Phase 3 and the manufacturer’s say that they are basically building the same PC board 3 times.
There are 2 methods of via drilling for sequential lamination. Staggered vias and stacked vias. See Figure 4 for the staggered micro-via process.
Notice in the Staggered Micro-via picture that the via plugging color is green. This could be an epoxy fill because the vias are staggered and there is no manufacturing stress. Discuss staggered vs: stacked vias with your manufacturer to find out if one technique is less expensive than the other. See Figure 5 for the stacked micro-via process.
The Stacked Micro-vias must be filled with conductive metal to prevent the outer laser drill from damaging the inner layer hole. See Figure 6.
The latest generation technology developed by Dow Electronic Materials for advanced via fill plating, MICROFILL™ EVF Via Fill provides enhanced via filling, with simultaneous through-hole plating, at surface thicknesses unattainable. Formulated to operate in existing equipment over a broad range of operating conditions, MICROFILL™ EVF Copper Via Fill is suitable for HDI applications. It is proved by sufficient experience that MICROFILL™ EVF could help to reduce 20% plating thickness and helps to improve varied plating defects. See Figure 7 for stacked micro-via conductive fill techniques. To read more on this topic see: http://www.rohmhaas.com/wcm/information/em/interconnect/microfill/index.page
Notice the lower right image in Figure 7 that shows a 0.15 mm via hole going all the way through a 1 mm thick PCB with 20um (0.000787”) or ½ OZ. copper plating thickness. The normal hole plating thickness on an average PCB is 25um (0.001″) or 1 mil.
The BGA or Ball Grid Array has been around since the 1980′s but the pin pitch started out with 1.5 mm and then quickly went to 1.27 mm (50 mils) for about 15 years. Then in the late 1990′s, the 1 mm pitch BGA was introduced and every couple years a smaller pin pitch was introduced. Today 0.4 mm pitch BGA’s are in every cell phone and 0.3 mm pitch BGA’s are the next generation. Figure 1 displays the lead type for this component family.
There are 2 types of BGA Ball Leads –
Non-collapsing – this is normally 0.5 mm pitch and smaller, where the Land (pad) is larger than the ball to allow for via-in-pad technology and provide an adequate annular ring. The solder mask can be the same size as the Land. In some cases the Land for fine pitch BGA’s is solder mask defined where the solder mask encroaches slightly over the land. This provides protection for any trace routing between the lands but the most significant benefit is to help secure the Land to the PCB. During cell phone “drop testing”, the BGA solder joint normally holds better than the land to the Prepreg. i.e.: drop tests prove that the non-solder mask land will rip from the PCB before the solder joint breaks. So the solder mask defined land is secured better to the PCB for drop testing.
Collapsing - this is normally 0.65 mm pitch and higher, where the Land (pad) is smaller than the Ball size to allow the Ball to collapse around the sides of the Land. This requires a non-solder mask defined Land where the solder mask must be larger than the Land.
See Figure 2 for examples of non-collapsing and collapsing BGA balls.
The BGA Land (pad) size is determined by the ball size as seen below in Table 1 from IPC-7351B land pattern standard. Notice the correlation between the “reduction” and the “land pattern density level”. The 3 density levels change the land size reduction percentage, but they also determine the Placement Courtyard Excess. See Table 3.
Note: The IPC-7351B LP Calculator Uses this chart for calculations
It is very important to note that IPC prefers the Maximum Material Condition for all BGA Land sizes; they do not use the Nominal Land Diameter, but do use the Maximum Land Variation Diameter (notice the Bold numbers in the Chart “Land Variation” column). Notice that the standard ball sizes are in 0.05 mm increments until the pin pitch hits 0.5 mm and less. However, even though the world standards try to keep BGA balls sizes in 0.05 mm increments, component manufacturer’s sometimes do not adhere to the standard and create BGA ball sizes in 0.01 mm increments, but I have never seen a BGA ball size less than a 0.01 mm increment. Also, the BGA pin pitches are in 0.05 mm increments. As a result, the BGA land (pad) sizes are in 0.05 mm increments including the via fanout padstacks and hole sizes.
IPC-7351B has a 3-Tier BGA formula for Placement Courtyard Excess that uses the BGA ball size to calculate an adequate placement courtyard for BGA rework tools. If the BGA has a large ball size, larger rework equipment is necessary to unsolder the increased solder volume.
With a small ball size, the placement courtyard can be smaller as less heat is then required to unsolder the BGA component for rework. However, the end user may not plan to rework the BGA if it fails. In that case, there is no need to have a robust placement courtyard, but a recommended minimum placement courtyard excess is 0.5 mm.
“Non-collapsing” ball BGA components
Table 2 below is used for land size calculations for non-collapsing BGA balls.
It is very important to note that IPC prefers the Maximum Material Condition for all BGA Land Sizes, meaning that the Maximum Land Variation Diameter is used; not the “Nominal Land Diameter”.
Figure 3 is a 0.5 pitch non-collapsing BGA ball. Instead of shrinking, the non-collapsing land size gets larger to handle the solder volume that creates the solder joint. This technology is new to the electronics industry and was created as a solution for lead-free BGA balls and via-in-pad technology as a routing solution for fine pitch BGA components.
Via-in-Land Technology Trace/Space & Grid Data
BGA Ball Size: 0.15 Trace Width: 0.075
BGA Land Dia: 0.275 Trace/Trace Space: 0.075
Hole Size: 0.15 Trace/Via Space: 0.075
Thermal Relief Required Trace/BGA Land: 0.075
Plane Clearance: 0.425 Routing Grid: 0.05
Solder Mask: 1:1 scale Part Place Grid: 1
IPC-7351A has a 3-Tier BGA formula for Placement Courtyards that uses the BGA ball size to calculate an adequate placement courtyard for BGA rework tools.
If the BGA has a large ball size, larger rework equipment is necessary to unsolder the large solder volume. With a small ball size, the placement courtyard can be smaller as less heat is then required to unsolder the BGA component for rework. However, the end user may not plan to rework the BGA if it fails. In that case, there is no need to have a robust placement courtyard.
Table 3 below represents the 3-Tier scenario and the different placement courtyard excess size determination.
About Tom Hausherr's Blog
New component package technology and CAD library standards.
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