Archive for June, 2011

23 June, 2011

PCB Breakaway Panels

 As PCB part placements get denser, it’s necessary to add breakaway panels that add additional board material (edge rails) to accommodate the assembly process. Two parallel edges are required for a PCB to be processed in the SMT line. This is to prevent skewing through the conveyor system. Also, all odd shaped PCB’s must have edge rails incorporated to meet this requirement. Custom reflow fixtures will be made, at an additional cost to you, if this requirement is not met. The breakaway tabs remain intact all the way through the assembly process and are removed at the final stage.

V-Grove Score and Tab Routing are two common methods used for creating breakaway tabs. Tab Routing uses perforated breakaway tabs (sometimes referred to as “Mouse Bites”). The breakaway tab closest to the PCB corner should be located between 10 mm and 12 mm from the edge to reduce sagging during reflow or wave soldering. It is also preferred to have at least one tab per side. If the PCB placement is too dense for a Tooling Hole, then it should be placed on the breakaway tab. See Figure 1 for the optimized breakaway tab solution.

Note: all dimensions in this paper are in millimeter units.

Figure 1 - Example of Breakaway Panel

 One important aspect is to have a clean edge after the breakaway tab is removed. Slight inset of perforation is preferred because it provides an edge which requires little to no additional labor to clean up. Figure 2 illustrates the perforation location preferences.

Figure 2 - Breakaway Perforation Locations

 The spacing between breakaway tabs can range from 60 mm to 90 mm, but I recommend 77 mm from center to center as shown in Figure 3. Try not to exceed 100 mm between tabs and try to evenly space them apart.

Figure 3 - Breakaway Tab Spacing

 The plane pull-back should be at least 1 mm from all slots and perforation holes. All trace routing needs to be over a plane for clean return path so keep all routing 1 mm from all slots and perforation holes. Keep components 2 mm – 3mm away from the routed slots. These rules help prevent components or trace damage during the de-paneling process. See Figure 4 to define the keep-out areas in the PCB layout.

Figure 4 - Plane & Component Spacing

 Tab routing is more precise than V-groove scoring and edge surfaces are smooth. The breakaway tab points require consideration for additional smoothing if necessary to comply with the fabrication drawing note regarding smooth edges. The dilled perforation provides a low stress break point on the tab and if the hole pattern is recessed within the printed board edge, secondary sanding or grinding can be avoided.

 It is not recommended to substitute perforation holes with a V-groove score as it does not provide a durable tab that will withstand handling. V-groove scoring can however be used in place of routing, but requires board edge grinding to smooth the surface. The V-groove feature is generally provided on both sides of the PCB and only in a straight line. A V-Groove depth that will provide a sturdy work-piece and still separate with light to moderate pressure after assembly is an important element in manufacturing. Many PCB fabrication shops recommend a V-grove depth that is 1/3 of the PCB thickness from both sides using Computer Numerical Control (CNC) equipment. The alignment or positional accuracy of the two grooves is critical for clean separation and minimizes post separation board edge smoothing. According to IPC-2222 Section 5.3.1, the alignment tolerance for the V-groove is ±80 µm. Figure 5 illustrates the 90° scoring option. It is important that all conductors be routed within a minimum distance of 1 mm from the top of the scoring edge to prevent damage during de-paneling. The inner layer planes should be pulled back 1 mm from the V-groove. The PCB designer should collaborate with the PCB fabrication shop on the V-groove angle option that they use.

Figure 5 - 90 Degree V-Groove Scoring

 Figure 6 illustrates the 30° scoring option and uses the same rules.

Figure 6 - 30 Degree V-Groove Scoring

 It is important to note that the 1/3 depth rule only applies to “Breakaway Panels”. V-Groove scoring inner web material can range from 0.15 mm to 0.4 mm for panel separation depending on the length of the score. If the score length is less than 25 mm, it can have a web thickness of 0.15 mm and scores that are 100 mm long can have a web thickness of 0.25 mm and scores that are longer than 100 mm can have a web thickness of 0.4 mm. These values are just guidelines and should be discussed with your assembly shop to confirm the web thickness for your printed circuit board design.

 

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13 June, 2011

Periphery Solder Joint Goals

When it comes to solder joint goals, we are familiar with the terms Toe, Heel and Side solder joint fillets, but IPC introduced the Periphery solder joint in the latest release of the IPC-7351B. Due to the indoctrination of several new component families like Dual Flat No-lead (DFN), Land Grid Array (LGA), Pull-back Quad Flat No-lead (PQFN), Pull-back Small Outline No-lead (PSON) and Column Grid Array (CGA), IPC created the Periphery solder joint goal to accommodate these “Bottom only terminal” lead forms as seen in Figure 1.

Figure 1 - Components with Bottom Only Terminal Leads

Figure 1 - Components with Bottom Only Terminal Leads

The flat leads of these component families are very compatible with lead-free solder, due to the fact that some lead-free solder alloys have low-flow wetting properties. The flat lead with a Periphery land area also improves assembly accuracy as the components have minimal “wander” movement during the reflow process. This is unlike the typical chip resistor & capacitor has a wrap-around component lead. Great caution must be taken into consideration because the J-STD-001D assembly standard allows for chip component overhang of up to 50% of the component width for Class 1 and Class 2 and 25% for Class 3 (the “A” dimension) as seen in Figure 2.

Figure 2 - Acceptable Wrap-around Lead Solder Joint

Figure 2 - Acceptable Wrap-around Lead Solder Joint

The new DFN component family has 2, 3 and 4 lead package styles and the body sizes range from 16 mm to 1 mm in size. The 2-pin DFN package is intended to replace wrap-around leaded chip resistors, diodes and capacitors. The component terminal leads for pin 1 and 2 can be different sizes. The DFN component package data is derived from the JEDEC MO-236A standard. The 3-pin DFN package is intended to replace gull wing leaded SOT23 and DPAK transistors and voltage regulators. The 4-pin DFN package is intended to replace a variety of different component families including oscillators, bridge rectifiers, LED’s, sensors, etc. The Periphery solder joint goals as seen in Table 1 are used for the DFN, PSON and PQFN component families.

Table 1 - DFN, PSON and PQFN Solder Joint Goals

Table 1 - DFN, PSON and PQFN Solder Joint Goals

The LGA component family usage is rapidly growing. The LGA component lead style can be a bump which is typically a round shape. The LGA component lead style can also be flat which can be round, square or irregular shape. The pin assignments typically follow the same JEDEC convention as BGA’s. The LGA component package data is derived from the JEDEC MO-270B standard. See Figure 3 for the LGA lead styles.

Figure 3 - LGA Lead Styles

Figure 3 - LGA Lead Styles

See Figure 4 for the LGA lead shapes.

Figure 4 - LGA Lead Shapes

Figure 4 - LGA Lead Shapes

The LGA land pattern only has one tier environment similar to the BGA however; the LGA land size is 1:1 scale of the lead size. See Table 2 for the LGA solder joint goals.

Table 2 - LGA Solder Joint Goals

Table 2 - LGA Solder Joint Goals

Multi-row & column LGA’s will require via-in-pad routing solutions for the inner rows of contacts because there is no room for the traditional “dog bone” via fanout. Figure 5 represents a 1.0 mm pitch LGA with 0.7 X 0.7 mm square lands with a flat lead. You can place 0.5 mm pad & 0.25 mm hole vias in the center of the lands and be able to route two 0.1 mm traces between the vias.

Figure 5 - LGA Via Fanout

Figure 5 - LGA Via Fanout

Unlike Pin Grid Arrays (PGA) that have been common to microprocessors, LGA’s do not utilize any pins but rather an array of bare gold plated copper pads that permit a direct electrical connection between the component substrate and the PCB. Compared to the PGA component family, LGA pad density can be significantly higher due to tighter spacing that is not hindered by the need to attach pins to the substrate.

Linear Technology is the world’s leading producer of LGA component packages. Linear uses unpopulated component leads in many of its component packages as seen in Figure 6.

Figure 6 - Linear LGA Packages with Unpopulated Leads

Figure 6 - Linear LGA Packages with Unpopulated Leads

The BGA land is considered the first “periphery” land introduced to the electronics industry. However, the collapsing BGA ball is the only land calculation that creates a smaller land than the component lead. Non-collapsing BGA balls require a larger land size than the ball size. Via-in Pad in a flat lead LGA produces better solder joint results than BGA technology because there are no “Voids” in the flat LGA component lead after reflow. Figure 7 is a BGA ball cross-section that illustrates trapped air hole using via-in-pad BGA void issues.

Figure 7 - BGA Void

Figure 7 - BGA Void

However, voids created by trapped air in blind or through-hole vias can be eliminated by plugging or filling the hole prior to the land plating process. Figure 8 illustrates various types of vias that contribute to trapped air and that causes voids in BGA balls.

Figure 8 - BGA Voids From Trapped Air

Figure 8 - BGA Voids From Trapped Air

The Pull-Back Small Outline No-lead package (PSON) is a rectangular semiconductor package with metal terminals along two sides of the bottom of the package. The Pull-back leads are typically 0.1 mm to 0.2 mm away from the component body edge. The body of the component is generally molded plastic and the plastic mold compound is present on all 4 sides of the terminal lead contact. The SON and PSON component families are intended to replace the leaded SOIC and takes up about 50% less PC board area footprint. The PSON is considered a leadless package design with a bottom paddle to conduct heat away from the package used stitch vias that attach to the GND plane.

The Pull-back component lead terminal shown in Figure 9 represents the Pull-back Small Outline No-lead (PSON) and Pull-back Quad Flat No-lead (PQFN) which have two different lead shapes, D-shape and rectangular. These illustrations are 0.8 mm pitch 5 mm X 5 mm body outline.

Figure 9 - PSON & PQFN Lead Shapes

Figure 9 - PSON & PQFN Lead Shapes

Note: the latest LP Wizard and LP Calculator 10.3.1 release introduces the D-shape land calculation and CAD export to tools that support D-shape lands.

See Table 1 for the IPC-7351B 3-Tier land pattern environments for PSON and PQFN component lead form with the Periphery solder joint goals.

Ceramic and Plastic Column Grid Arrays (CGA) solder column contacts are used for larger ceramic-based packages (32.0 mm to 45.0 mm). The package resembles the earlier plated through-hole pin-grid-array but with closer contact pin pitch. The column contact diameter is typically 0.5 mm for 1.0 mm pin pitch and 1.2 mm to 2.0 mm lead length. The columns are attached to the package either by eutectic (Pb37Sn63) solder or they are cast in place using 90% Pb and 10% Sn. Via-in-pad technology is popular with the 1.0 mm pitch CGA component family due to the lack of room for a typical bog-bone via fanout.

The longer columns typically increase solder joint reliability by absorbing the stresses created by the CTE mismatch between the ceramic package and the PC board. On the other-hand, longer columns may reduce electrical performance and will increase the overall package profile on the PCB. Also, the columns are not as rugged as a BGA solder joint and are susceptible to handling damage.

The Column Grid Array was grouped with the LGA component family solder joint goals in the IPC-7351B at 1:1 scale lead to land size, but the CGA solder goals were recently been updated so that the land size is 0.1 mm larger than the maximum lead diameter. Figure 10 illustrates the CGA solder joint goal with a periphery land to form a solder fillet and Table 3 has the solder joint goal data.

Figure 10 - CGA Solder Joint

Figure 10 - CGA Solder Joint

Table 3 - CGA Solder Joint Goals

Table 3 - CGA Solder Joint Goals

The DFN, PSON, PQFN, LGA, CGA and BGA have a different concept for developing a land pattern. Effectively, there are no toe, side or heel fillets; rather the land periphery is similar about the entire termination. Whether the component terminal shape is round, square, rectangle or D-shape, once the tolerance is assigned it applies to the periphery of the lands for that particular part. Thus the term “Periphery” is used to signify that the principles occur all around the component package termination contact.

Did you know that the LP Wizard fully supports all the component families listed in this article? You can download the free 10-day trial license for the newly released LP Wizard 10.3.1 that now produces D-shape land style for PQFN and PSON component families here – http://www.mentor.com/go/lpwizard

After the 10-day trial license ends, there is no need to uninstall the program as the LP Wizard will run in “Demo Mode” (without a license) as an IPC-7351B LP Calculator.

3 June, 2011
IPC introduced a new padstack naming convention in the IPC-7351B standard publication and it is used exclusively in the Mentor Graphics LP calculator. This article explains the breakdown of the new standard and its benefits.

The padstack consists of combinations of letters and numbers that represent shape, or dimensions of lands on different layers of printed boards or documentation. The name of the padstack needs to represent all the various combinations. These are used in combination with the land pattern conventions defined herein according to the rules established in the IPC-2220 Design standards.

The first part of the padstack convention consists of a land (pad) shape. There are six basic land shape identifiers. Note: All alphabetical characters are “lower case”. This helps discriminate numeric values.

Basic Land Shape Letters –

  • c = Circular
  • s = Square
  • r = Rectangle
  • b = Oblong
  • d = D-shape (Square on one end and full radius on the other end)
  • u = User defined contour (Irregular shape)

 The “b” was used for Oblong because the letter “o” can easily be confused with the character zero “0”.

 The next section of the naming convention addresses assumed defaults. This is to keep the default padstack name short and simple. Any deviations from these padstack defaults require the use of special modifiers.

  • Solder Mask is 1:1 scale of the land size
  • Paste Mask is 1:1 scale of the land size
  • The Assembly Layer land is 1:1 scale of the land size

  • Inner Layer Land is the same shape as the outer layer land

  • The Primary and Secondary lands are the same size

  • The inner layer land shapes are Circular

  • Vias are Circular

  • Thermal ID, OD and Spoke Width sizes follow the IPC Level A, B or C

  • Thermal Reliefs have 4 spokes

  • Plane Clearance Anti-pad size follows the IPC Level A, B or C

  • Mounting Holes are Circular

 Every board fabricator’s ability to register solder mask is different. The 1:1 scale solder mask default compensates for the variation, and so long as manufacturers are building to standard specifications such as the IPC-6012 that states you can’t have miss-registration of the solder mask. It’s important that when you are creating a CAD library that will be used for various trace/space combinations, that you leave the responsibility of the solder mask swell up to the fabrication CAM operator when they are panelizing your Gerber or ODB++ data. By having all of the solder mask sizes 1:1 scale of the land (pad) size, you are providing the manufacturer with a known starting point for them to work with.

I need to explain an exception to this rule for creating solder mask defined lands for BGA’s. IPC does not recommend solder mask defined BGA CAD library parts but some companies use this technique for very fine pitch parts that require a small diameter land size. In this case, the solder mask acts as an adhesive to secure the land to the PCB Prepreg to withstand drop testing for hand held electronic products. It has been proven in drop tests for hand held electronic devices that a fine pitch BGA solder joint is more secure than the land attachment to the Prepreg. i.e.: during drop testing, a fine pitch BGA pad will rip away from the PCB Prepreg material before the BGA solder joint fails. See the picture on the right side in Figure 1 as an example of a solder mask defined BGA land.   

Figure 1 - Solder Mask Defined BGA Land

Figure 1 - Solder Mask Defined BGA Land

 

 Solder mask defined lands are also used for Flexible circuit boards for the same reason, to hold the land (pad) to the PCB surface to prevent the land from ripping away from the PCB material. When you use solder mask defined lands you must indicate which parts deviate from the 1:1 scale solder mask rule in the fabrication drawing notes to notify the CAM operator not to swell these solder mask features.

 In the padstack naming convention there are illegal characters that should never be used. These include “ ” , ; : / \ [ ] ( ) . { } * & % # $ ! @ ^ =

 Examples utilizing the “Basic Land Shape Letters” (all padstack values are in metric units)

 Note: Every number goes two places to the right and as many places as needed to the left of the decimal

 Examples: 1150 = 11.50 mm or 11500 μm, 150 = 1.50 mm or 1500 μm, 15 = 0.15 mm or 150 μm

c150h90 - where “c” denotes a Circular land with a 1.50 diameter and H denotes a hole size of 0.90

v50h25 – where a “v” denotes a via with a 0.50 land (default Circular land) and H denotes a 0.25 hole

s150h90 – where “s” denotes a 1.50 Square land and H denotes a hole size of 0.90

s350 – where ‘s” denotes a square SMT land size of 3.50

r200_100 – where “r” denotes a Rectangular SMT land 2.00 land length X 1.00 land width

b300_150 – where “b” denotes a SMT Oblong land size of 3.00 X 1.50

b400_200h100 – where “b” denotes an Oblong land size of 4.00 length X 2.00 width and 1.00 hole

d300_150 – where “d” denotes land with one circular end and one square end (looks like a D) 3.00 X 1.50

v30h15l1-3 – where “v” denotes a 0.30 blind via with 0.15 Hole; 1 is the starting layer, 3 is the end layer

r200_100r5 – Rounded Rectangular 2mm X 1mm X 0.05mm radius corners

r200_100c10 – Chamfered Rectangular 2mm X 1mm X 0.1mm chamfered corners

v30h15l3-6 – where “v” denotes a 0.30 buried via with 0.15 Hole; 3 is the starting layer, 6 is the end layer

  Special modifiers are used when padstack features are different than the defaults. These are the “Variants” or “Modifiers” that go after the basic padstack naming convention.

 These are used when the User needs to change the padstack default values either by a different dimension or a different shape. In instances where shapes are different this becomes a two letter code with the modifier first followed by the land shape letter.

 

These are single letter modifiers –

n = Non-plated Hole

z = Inner Layer land dimension if different than the land on primary layer

x = Special modifier used alone or following other modifiers for lands on opposite side to primary layer land dimension

t­ = Thermal Relief; if different than IPC standard padstack – tid_od_sw for 4 spoke default      

m = Solder Mask if different than default 1:1 scale of land

p = Solder Paste if different than default 1:1 scale of land

a = Assembly surface land if different than default 1:1 scale of land

y = Plane Clearance (Anti-pad) if the value is different than the Thermal OD

o = Offset Land Origin

k = Keep-out

r = Radius for Rounded Rectangular Land Shape

c = Chamfer for Chamfered Rectangular Land Shape

 

These are double letter modifiers –  

ts = Thermal Square; if different than the top side land shape and dimensions

sw = Thermal spoke width

zs = Inner Layer Land Shape is Square (Note: The default is circular)

m0 = No Solder Mask

mxc = Solder Mask Opposite Side Circular

mx0 = Solder Mask Opposite Side No Solder Mask

xc = Opposite Side Circular

vs = Via with Square land

hn = Non-plated Hole

 

 Land shape change is the last letter in the string prior to the dimension.

 Examples of single letter modifiers with a Circular Plated Through-hole land –

c150h90 = Default padstack with a 1.50 circular land with a 0.90 hole (no modifiers used)

c150hn90 = Default padstack with a 1.50 circular land with a 0.90 non-plated hole (no modifiers used)

c150h90z140 = Inner layer land is smaller than external lands 1.40 or 0.10 smaller

c150h90z140x170 = Opposite side land is larger than top side land 1.70 or 0.20 larger

c150h90z140x170m165mx185 = Solder mask opening for top and bottom lands 0.15 larger for each

c150h90z140x170m165mX185a200 = Assembly drawing land in 0.50 larger than 1.50 primary land

c150h90z140x170m165mx185a200y300 = Plane clearance anti-pad diameter is 3.00

c150h90z140x170m165mx85 = Solder mask encroachment on opposite land by 0.65 smaller

c150h90m165 = adding a solder mask opening of 1.65 diameter or 0.15 larger than land

c150h90t150_180_40 = Thermal ID 1.50, OD 1.80, Spoke Width 0.40, Anti-pad 1.80

c150h90t150_180_40y200 = Anti-pad 2.00 (because the size is different than the Thermal OD)

c150h90t150_180_80_2 = Spoke Width 0.80 with 2 Spokes

c150h90m165t150_180_40 = Solder Mask 1.65

c150h90zc150 = where “c” is Circular 1.50 land with 0.90 Hole with 1.50 inner (Z) Layer Circular land

 

 Examples of single letter modifiers for an Oblong Surface Mount land –

b300_150 = Default padstack with a 3.00 length and 1.50 width land (no modifiers used)

b300_150m330_180 = Solder Mask is 0.30 larger than the land

b300_150m330_180p240_140 = Solder Paste is smaller by 0.10 width and 0.60 length

b300_150b-50 = Oblong Land 3.0mm X 1.5mm w/Offset Origin negative 0.5mm

r400_200po430_230 = Rectangle SMT land 4.00 X 2.00 with a Oblong Solder Paste size of 4.30 X 2.30

 

 Examples of a padstack with Oblong land with Slotted Hole –

Sample – b = Oblong Land Shape then “X” dimension (length) then Underscore _Y” dimension (width)

b400_200h300_100 = Oblong land 4mm length X 2mm width with slotted hole size 3mm X 1mm

b400_200hn300_100 = Oblong land 4mm X 2mm with non-plated slotted hole size 3mm X 1mm

 

 Chamfered & Rounded corner modifiers are used to indicate which corner(s) are modified.

 See figure 2 for the “order of precedence” that has been given to the first 4 modifiers.

Figure 2 - Chamfered Land Variations

Figure 2 - Chamfered Land Variations

 

 Modifiers:

  • bl = bottom left
  • br = bottom right
  • ul = upper left
  • ur = upper right
  • ulr = upper left & right
  • blr = bottom left & right
  • ubl = upper and bottom left
  • ubr = upper and bottom right

 Rounded and Chamfered lands in “one corner” Modifier Examples:

r100_200rbl50 = rectangular land 1.00 x 2.00 with 0.50 radius for rounded corner in bottom left corner

r100_200rbr50 = rectangular land 1.00 x 2.00 with 0.50 radius for rounded corner in bottom right corner

r100_200rul50 = rectangular land 1.00 x 2.00 with 0.50 radius for rounded corner in upper left corner

r100_200rur50 = rectangular land 1.00 x 2.00 with 0.50 radius for rounded corner in upper right corner

r100_200cbl50 = rectangular land 1.00 x 2.00 with 0.50 chamfer for chamfer corner in bottom left corner

r100_200cbr50 = rectangular land 1.00 x 2.00 with 0.50 chamfer for chamfer corner in bottom right corner

r100_200cul50 = rectangular land 1.00 x 2.00 with 0.50 chamfer for chamfer corner in upper left corner

r100_200cur50 = rectangular land 1.00 x 2.00 with 0.50 chamfer for chamfer corner in upper right corner

 

Chamfered and Rounded Rectangular with all four corners chamfered does not need a corner modifier.

Modifier Examples with Rounded Rectangle Land Shape: 

Rounded Rectangular Land Shape

Rounded Rectangular Land Shape

r200_100culr50 = rectangular land 2.00 x 1.00 with 0.50 chamfer for chamfered corners in 2 corners

r200_100c50 = rectangular land 2.00 x 1.00 with 0.50 chamfer for chamfered corners in all 4 corner

 

Modifier Examples with Chamfered Rectangle Land Shape: 

Chamfered Rectangular Land Shape

Chamfered Rectangular Land Shape

r100_200r50 = rectangular land 1.00 x 2.00 with 0.50 radius for rounded corners in all 4 corners

r200_100r50 = rectangular land 2.00 x 1.00 with 0.50 radius for rounded corners in all 4 corners

 

 Thermal pads can have a combination of chamfered and rounded corners however the typical application is 2 variations. The most prominent is a chamfered corner located near pin 1 and the second is a chamfered corner located near pin 1 with the other 3 corners rounded. These two variations are the default.

Square Configurations

Thermal Pad with 4 Square Corners

Thermal Pad with 4 Square Corners

s480p4s152 = 4.80mm Square Land with 4 Paste Mask Squares 1.52mm each

Thermal Pad with Chamfered Corner

Thermal Pad with Chamfered Corner

u480p4s152cul50 = 4.80mm Square Land with 4 Paste Mask Squares 1.52mm each with 0.50mm Chamfer in Upper Left corner

Thermal Pad With Chamfered Corner Rounded Corners

Thermal Pad With Chamfered Corner Rounded Corners

u480p4s152cul50r25 = 4.80mm Square Land with 4 Paste Mask Squares 1.52mm each with 0.50mm Chamfer in Upper Left corner with 0.25mm corner Radius

 

 Example of a Local Fiducial for Fine Pitch SMT Components:

c100m200k200 = Circular Land 1.00 with Solder Mask 2.00 with Keep-out 2.00

s100m200k200 = Square Land 1.00 with Solder Mask 2.00 with Keep-out 2.00

See Figure 3 for Local Fiducial application used for fine pitch components.  

Figure 3 - Local Fiducials

Figure 3 - Local Fiducials

 

 Did you know that you can download a free 10-day trial license for LP Wizard here – http://www.mentor.com/go/lpwizard

 After the 10-day trial license ends, the LP Wizard will run in “Demo Mode” as an IPC-7351B LP Calculator. The LP Calculator auto-generates padstack names using the convention mentioned in this article.  

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