Archive for January, 2011

28 January, 2011

The 3-Tier PCB library concept was originally created by IEC (International Electromechanical Commission) in 1999 and introduced to IPC in 2000. The concept had to be created as a solution for high density packaging for hand held devices to ruggedized military applications and everything in-between. The IPC-7351 and the IEC 61188-5-1 SMT land pattern standards for were specifically created to introduce this new concept in 2005. Before 2005, the IPC-SM-782 was a 1-Tier land pattern standard developed in 1985 and released in March 1987. The pad size of the IPC-SM-782 land pattern, compared to the new IPC-7351, fell in-between the Most and the Nominal environments.

The IPC-7251 land pattern standard for through-hole components is currently being developed. It also has a 3-Tier environment concept that apply to the hole sizes and annular rings.

Three land pattern geometry variations are supplied for each of the device families; Maximum Land Protrusion (Density Level A), Nominal Land Protrusion (Density Level B) and Least Land Protrusion (Density Level C). Here are the definitions for the 3-Tier (or 3 Level) PCB library system for both through-hole and SMD technology.

Density Level A: Maximum Land/Lead to Hole Relationship – The ‘maximum’ land pattern conditions have been developed to accommodate the most robust producability of the solder application method. The “Level A” land patterns are usually associated with low component density product applications. “Level A” land patterns accommodate wave or flow solder of leadless chip devices and leaded gull wing devices. The geometry furnished for these devices, as well as inward and “J”-formed lead contact device families, may provide a wider process window for reflow solder processes as well. “Level A” is used for ruggedized military applications and medical devices.

Density Level B: Nominal Land/Lead to Hole Relationship – Products with a moderate level of component density may consider adapting the ‘median’ land pattern geometry. The median land patterns furnished for all device families will provide a robust solder attachment condition for most soldering processes and should provide a condition suitable for wave, dip, drag or reflow soldering. “Level B” is primarily used for desktop applications, controlled environment devices and many consumer electronic products.

Density Level C: Least Land/Lead to Hole Relationship – High component density typical of portable and hand-held product applications may consider the ‘minimum’ land pattern geometry variation. Selection of the minimum land pattern geometry may not be suitable for all product use categories.
The use of classes of performance 1, 2, and 3 is combined with that of component density levels A, B, and C in explaining the condition of an electronic assembly. As an example, combining the description as Levels 1A or 3B or 2C, would indicate the different combinations of performance and component density to aid in understanding the environment and the manufacturing requirements of a particular assembly.

See Figure 1 for an example of the 3 different land pattern levels for chip components.

Figure 1 - 3-Tier for Chip Components

Figure 1 - 3-Tier for Chip Components

Let’s take a look at the IPC-7351B tables for the Chip Component family. Table 1 applies to all chip components equal to or larger than a 1608 (EIA 0603). The chip component family is referred to as “Rectangular or Square-End components for resistors, capacitors and inductors.

Table 1 - Chip Components Equal or Greater Than 1608 (EIA 0603)

Table 1 - Chip Components Equal or Greater Than 1608 (EIA 0603)

Notice in Table 1 that the Side Goal value for the Least Environment is -0.05 mm. This does not mean that the land will be smaller than the component lead. There are several other factors that go into the land size calculation like Fabrication and Assembly tolerances and Component Lead tolerance. So whenever you see a negative value in a solder joint goal table, it is only adjusting the land size to neutralize the fabrication tolerance.

Table 2 is for “Rectangular or Square-End components for resistors, capacitors and inductors smaller than a 1608 (EIA 0603). Notice that the “Toe” goal and placement courtyard excess are affected the most. Also, the round-off factor is in 0.02 mm increments.

Table 2 - Chip Components Less Than 1608 (EIA 0603)

Table 2 - Chip Components Less Than 1608 (EIA 0603)

See Figure 2 for an example of the 3 different land pattern levels for small outline package (SOP) components.

Figure 2 - 3-Tier for SOP Components

Figure 2 - 3-Tier for SOP Components

Let’s take a look at the IPC-7351B tables for the Gull Wing and Flat Ribbon L lead Component family. This component family includes Small Outline Diodes (SOD), Small Outline Packages (SOP) Small Outline Transistors (SOT) and Quad Flat Packages (QFP). Table 3 applies to all gull wing components with a pin pitch greater than 0.625 mm.

Table 3 - Gull Wing with Pin Pitch Greater than 0.625 mm

Table 3 - Gull Wing with Pin Pitch Greater than 0.625 mm

Table 4 is for Gull Wing and Flat Ribbon L lead Component family with a pin pitch less than 0.625 mm.

Table 4 - Gull Wing with Pin Pitch Less than 0.625 mm

Table 4 - Gull Wing with Pin Pitch Less than 0.625 mm

Notice in Table 4 that the only difference is in the “Side” solder joint goal. Also, Table 4 only represents the Small Outline Package (SOP) and the Quad Flat Package (QFP) component families.

There is a different IPC-7351B table for every component family lead type. The only component family group that only has one tier for the land size is the “Grid Array” components. Ball Grid Array (BGA), Land Grid Array (LGA), Column Grid Array (CGA and Pillar Column Grid Array (PCGA). This component family group has various placement courtyard excess sizes that are dependent on the lead size for the sole purpose of rework equipment access.

The “Bottom Only” leaded component families do not have a Toe, Heel or Side solder joint goal. Their solder joint goal is referred to as a “Periphery” and the land area is the same value on all sides. This includes “D-Shaped” leads for Pull-back lead QFN, Square and Rectangular leads for LGA’s and Round leads for BGA, CGA and LGA.

The SMT Land Pattern Naming convention has an M, N or L at the end of the name and the PTH Land Pattern Naming convention has an A, B or C at the end of the name to identify the Density Level with the exception of the Grid Array component families. The main reason why SMD land pattern names use L, N & M is because they can be used in all “Producibility Levels” –

  • Level A – General Design Producibility (Preferred)
  • Level B – General Design Producibility (Standard)
  • Level C – General Design Producibility (Reduced)

However, the PTH land pattern names use A, B & C because they are closely linked to the Producibility Levels for manufacturability due to drill hole tolerances and annular ring allowance for both outer and inner layers. Note: The IPC-7251 standard for through-hole technology is still in development and should be released later this year (2011).

There is also a “Proportional” environment for PTH libraries that uses a combination of IPC Level A, B and C depending on the hole size. Small holes use Level C, medium hole sizes use Level B and larger hole sizes use Level C or greater annular ring. Proportional meets IPC levels for smaller hole sizes and beats IPC levels for larger hole sizes.

21 January, 2011
0.5 mm Pitch BGA Routing Solution

There is a reasonable solution for via fanout and a routing solution for the 0.5 mm pitch BGA but we need to think outside the box. The board thickness is an important factor because it affects the hole plating aspect ratio. If you use a 1 mm PCB thickness and want to achieve a 7:1 aspect ratio (this is common among all manufacturers) then the smallest hole size is 0.15 mm (6 mil). There are manufacturer’s that can hard drill a 0.15 mm (6 mil) hole through a 1 mm PCB. There are manufacturers that claim they can easily handle 10:1 aspect ratios. This means that they can drill 0.15 mm (6 mil) holes through 1.57 mm (0.062”) thick PCB material and plate the hole without problems. Drilling all the way through the PCB is important because sequential lamination is an expensive process.

For all via-in-land technology, a thermal relief on the voltage and ground plane connections must be used to prevent cold solder joints. A direct via-in-land connection to the plane will dissipate the heat required to melt the solder around the BGA ball and this will result in a cold or cracked solder joint. The exception to this rule is if the via only contacts a single plane with ½ OZ. copper or less.

If traces are routed between pins of the 0.5 pitch BGA land, the solder mask must be a 1:1 scale to create a “solder mask defined” BGA land. In this way, the traces between the lands will be protected from exposure and possible short circuiting.

The 0.5 mm pitch BGA via-in-land drill hole through the PCB is leading edge technology. When laser drills are capable of producing 0.125 hole sizes entirely through the board and PCB manufacturers can accurately fill the holes with conductive metal epoxy, this technology will become mainstream.

Micro-via technology is the mainstream solution for 0.5 pitch BGA components when a 0.1 – 0.15 laser hole is drilled one, two or three layers deep. This involves sequential lamination but before we get to that subject let’s discuss the via fanout process. Using via-in-land technology, we must offset the drill holes to create adequate routing channels. This is the only routing solution that I know of to maintain manufacturability. See Figure 1 for a via fanout solution for the outer layer. Notice that you will have to add additional copper land for via annular ring.

Figure 1 – 0.5 mm Pitch BGA Via-in-Land

Figure 1 – 0.5 mm Pitch BGA Offset Via-in-Land

The vias are 0.05 mm offset from the land center and grouped together.

See Figure 2 for a via fanout solution for the inner layers. The most important feature here is the 0.1 mm (4 mil) trace width & 0.1 mm space between Trace to Via and Via to Via.

Figure 2 – 0.5 mm Pitch BGA fanout Inner Layers

Figure 2 – 0.5 mm Pitch BGA fanout Inner Layers

 

 

 

Depending on how many rows and columns in the BGA will determine the number of routing layers required.  

Sequential lamination process requires the inner layers to be laminated, drilled and plated in Phase 1 and then add 2 additional outer layers and back through lamination, drill and plate in Phase 2. Then add 2 additional outer layers and back through lamination, drill and plate in Phase 3. See Figure 3 for the various phases of sequential lamination.

Figure 3 - Sequential Lamination

Figure 3 - Sequential Lamination

Let me try to explain why sequential lamination is so expensive and why most people avoid it unless they absolutely need it for high volume production. The PCB inner layer manufacturing goes through the entire fabrication process in Phase 1. Then the first HDI layers that are added to the PCB have to go through the entire fabrication process over again. This basically doubles the cost in Phase 2. Then the second HDI layers that are added to the PCB have to go through the entire fabrication process over again. This basically triples the cost in Phase 3 and the manufacturer’s say that they are basically building the same PC board 3 times.

There are 2 methods of via drilling for sequential lamination. Staggered vias and stacked vias. See Figure 4 for the staggered micro-via process.

Figure 4 – Staggered Micro-vias

Figure 4 – Staggered Micro-vias

Notice in the Staggered Micro-via picture that the via plugging color is green. This could be an epoxy fill because the vias are staggered and there is no manufacturing stress. Discuss staggered vs: stacked vias with your manufacturer to find out if one technique is less expensive than the other. See Figure 5 for the stacked micro-via process.

Figure 5 – Stacked Micro-vias

Figure 5 – Stacked Micro-vias

The Stacked Micro-vias must be filled with conductive metal to prevent the outer laser drill from damaging the inner layer hole. See Figure 6.

Figure 6 – Stacked Micro-via Conductive Fill

Figure 6 – Stacked Micro-via Conductive Fill

The latest generation technology developed by Dow Electronic Materials for advanced via fill plating, MICROFILL™ EVF Via Fill provides enhanced via filling, with simultaneous through-hole plating, at surface thicknesses unattainable. Formulated to operate in existing equipment over a broad range of operating conditions, MICROFILL™ EVF Copper Via Fill is suitable for HDI applications. It is proved by sufficient experience that MICROFILL™ EVF could help to reduce 20% plating thickness and helps to improve varied plating defects. See Figure 7 for stacked micro-via conductive fill techniques. To read more on this topic see:  http://www.rohmhaas.com/wcm/information/em/interconnect/microfill/index.page

Figure 7 – Stacked Micro-via Conductive Fill

Figure 7 – Stacked Micro-via Conductive Fill

Notice the lower right image in Figure 7 that shows a 0.15 mm via hole going all the way through a 1 mm thick PCB with 20um (0.000787”) or ½ OZ. copper plating thickness. The normal hole plating thickness on an average PCB is 25um (0.001″) or 1 mil.

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14 January, 2011
CAD Library Zero Component Orientations
 
In 2005 IPC and IEC (International Electrotechnical Commission) established a joint standard for land pattern geometries (IPC-7351/IEC 61188-5-1). In order to maintain a consistent method where these two important standards describe the component mechanical outlines, and their respective mounting platforms, a single concept must be developed that takes into account various factors within the global community.

The land pattern standards clearly define all the properties necessary for standardization and acceptability of a “One World CAD Library”. The main objective in defining a one world CAD library is to achieve the highest level of “Electronic Product Development Automation”. This encompasses all the processes involved from engineering to PCB layout to fabrication, assembly and test. The data format standards need this type of consistency in order to meet the efficiency that electronic data transfer can bring to the industry.

Many large firms have spent millions of dollars creating and implementing their own unique standards for their own “Electronic Product Development Automation”. These standards are proprietary to each firm and are not openly shared with the rest of the industry. This has resulted in massive duplication of effort costing the industry millions of man hours in waste and creating industry chaos and global non-standardization.

The Land pattern standards (both IPC-7351 and IEC 61188-5-1) put an end to the “Proprietary Intellectual Property” and introduce a world standard so every electronics firm can benefit from Electronic Product Development Automation. The data format standards (IPC-2581 and IEC 61182-2) are an open database XML software code that is neutral to all the various CAD ASCII formats. For true machine automation to exist, the world desperately needs a neutral CAD database format that all PCB manufacturing machines can read.

One of the factors in global standardization is that of establishing a CAD component description and land pattern standard that adopts a fixed Zero Component Orientation so that all CAD images are built with the same rotation for the purpose of assembly machine automation. The IPC-7351 indicates that in the CAD library, all pin 1 locations are in the upper left corner for multiple pin components and pin 1 on left for 2-pin components. Figure 1 represents IPC-7351 default and IEC 61188-7 “Level A” zero component orientation.

Figure 1 - IPC-7351 Pin 1 Upper Left (IEC 61188-7 Level A)

Figure 1 - IPC-7351 Zero Orientation with Pin 1 Upper Left (IEC 61188-7 Level A)

 In May 2009, IEC land pattern committee voted and approved a new Level B Zero Component Orientation and redefined the IPC-7351 Zero Orientation as Level A. The new IEC 61188-7 defines Zero Component Orientation pin 1 locations in the bottom left corner except 2-pin components Pin 1 is on the left side and labeled it “Level B”. Figure 2 represents IEC 61188-7 “Level B” zero component orientation.

Figure 2 – IEC 61188-7 “Level B” Zero Orientation with Pin 1 in Lower Left Corner

Figure 2 – IEC 61188-7 “Level B” Zero Orientation with Pin 1 in Lower Left Corner

  Since the basic rules allow two variations of levels in the description of the CAD system library, it is a mandatory requirement to define which level was used (level A or Level B) for the component descriptions in the data file. This information is a mandatory requirement in the Header of any file that incorporates land patterns using these principles of zero-based orientation. See Figure 3 for the “Level A” zero orientation and machine rotation.

Figure 3 – Example of “Level A” Orientation Concepts

Figure 3 – Example of “Level A” Orientation Concepts

The industry association EIA (Electronics Industry Association) is responsible for component descriptions and tape and reel orientation in the EIA-481-D standard. EIA has tried valiantly to influence the industry by making good standards that describe the component outlines and how they should be positioned in the delivery system to the equipment on the manufacturing floor. Suppliers of parts have either not adhered to the recommendations or have misunderstood the intent and provided their products in different orientations.

Here are the EIA-481-D standard tape and reel pictures (Figures 4 & 5) that illustrate quadrant designations.

Figure 4 – EIA-481-D Quadrant Designations

Figure 4 – EIA-481-D Quadrant Designations

 

Figure 5 – CAD Library Zero Orientation Quadrants

Figure 5 – CAD Library Zero Orientation Quadrants

IPC and IEC use consistent rotations throughout their standard where EIA uses multiple rotation variations

  • IPC-7×51 “Level A” uses Quadrant 2 for Pin 1 Upper Left and Quadrants 2-4 for Upper Center
  • IEC 61188-7 “Level B” uses Quadrant 1 for Pin 1 Lower Left and Quadrants 1-2 for Left Center
  • EIA-481-D uses Quadrant 1 for Pin 1 Lower Left BGA, SOIC, SOP, QFN (rectangle), DIP
  • EIA-481-D uses Quadrant 2 for Pin 1 Upper Left TO-252, TO-263, QFN (square), TSOP
  • EIA-481-D uses Quadrant 3 for Pin 1 Lower Right for all SOT and miniature parts
  • EIA-481-D uses Quadrants 1-2 (Pin 1 Left Center) for PLCC, LCC
  • None of the 3 standards use Quadrant 4 for Pin 1 locations

The main purpose of creating the land pattern standards is to achieve reliable solder joint formation platforms; the reason for developing the data transfer structure is to improve the efficiency with which engineering intelligence is converted to manufacturing reality. Even if the neutral CAD format can drive all the manufacturing machines, it would be meaningless unless the component description standard for CAD land patterns was implemented with some consistency. Zero Component Orientation has a key role in machine automation.

The easiest way to illustrate the 3 world standards is to list every component family and their respective Zero Component Orientation for each standard. The big question is – Which standard will prevail?  

Figure-6 IPC, IEC & EIA Zero Component Orientations

Figure-6 IPC, IEC & EIA Zero Component Orientations

Note: The EIA-481-D rotations marked in Red conflict with both IPC and IEC

Download the complete IPC-7351B Electronic Component Zero Orientation document here – http://www.mentor.com/resources/appnotes/upload/zero-orientation-cad-libaray.pdf

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8 January, 2011

The BGA or Ball Grid Array has been around since the 1980’s but the pin pitch started out with 1.5 mm and then quickly went to 1.27 mm (50 mils) for about 15 years. Then in the late 1990’s, the 1 mm pitch BGA was introduced and every couple years a smaller pin pitch was introduced. Today 0.4 mm pitch BGA’s are in every cell phone and 0.3 mm pitch BGA’s are the next generation. Figure 1 displays the lead type for this component family.

Figure 1

Figure 1

There are 2 types of BGA Ball Leads –

  1. Non-collapsing – this is normally 0.5 mm pitch and smaller, where the Land (pad) is larger than the ball to allow for via-in-pad technology and provide an adequate annular ring. The solder mask can be the same size as the Land. In some cases the Land for fine pitch BGA’s is solder mask defined where the solder mask encroaches slightly over the land. This provides protection for any trace routing between the lands but the most significant benefit is to help secure the Land to the PCB. During cell phone “drop testing”, the BGA solder joint normally holds better than the land to the Prepreg. i.e.: drop tests prove that the non-solder mask land will rip from the PCB before the solder joint breaks. So the solder mask defined land is secured better to the PCB for drop testing.
  2. Collapsing - this is normally 0.65 mm pitch and higher, where the Land (pad) is smaller than the Ball size to allow the Ball to collapse around the sides of the Land. This requires a non-solder mask defined Land where the solder mask must be larger than the Land.

 See Figure 2 for examples of non-collapsing and collapsing BGA balls.

Non-collapsing and Collapsing BGA Balls

Figure 2: Non-collapsing and Collapsing BGA Balls

The BGA Land (pad) size is determined by the ball size as seen below in Table 1 from IPC-7351B land pattern standard. Notice the correlation between the “reduction” and the “land pattern density level”. The 3 density levels change the land size reduction percentage, but they also determine the Placement Courtyard Excess. See Table 3.

Table 1: Land Approximation for Collapsible Solder Balls

Table 1: Land Approximation for Collapsible Solder Balls

Note:  The IPC-7351B LP Calculator Uses this chart for calculations

It is very important to note that IPC prefers the Maximum Material Condition for all BGA Land sizes; they do not use the Nominal Land Diameter, but do use the Maximum Land Variation Diameter (notice the Bold numbers in the Chart “Land Variation” column). Notice that the standard ball sizes are in 0.05 mm increments until the pin pitch hits 0.5 mm and less. However, even though the world standards try to keep BGA balls sizes in 0.05 mm increments, component manufacturer’s sometimes do not adhere to the standard and create BGA ball sizes in 0.01 mm increments, but I have never seen a BGA ball size less than a 0.01 mm increment. Also, the BGA pin pitches are in 0.05 mm increments. As a result, the BGA land (pad) sizes are in 0.05 mm increments including the via fanout padstacks and hole sizes.

IPC-7351B has a 3-Tier BGA formula for Placement Courtyard Excess that uses the BGA ball size to calculate an adequate placement courtyard for BGA rework tools. If the BGA has a large ball size, larger rework equipment is necessary to unsolder the increased solder volume.

With a small ball size, the placement courtyard can be smaller as less heat is then required to unsolder the BGA component for rework.  However, the end user may not plan to rework the BGA if it fails.  In that case, there is no need to have a robust placement courtyard, but a recommended minimum placement courtyard excess is 0.5 mm.

Non-collapsing” ball BGA components

Table 2 below is used for land size calculations for non-collapsing BGA balls.

Table 2: Non-Collapsing BGA Ball Land Calculations

Table 2: Non-Collapsing BGA Ball Land Calculations

It is very important to note that IPC prefers the Maximum Material Condition for all BGA Land Sizes, meaning that the Maximum Land Variation Diameter is used; not the “Nominal Land Diameter”.

Figure 3 is a 0.5 pitch non-collapsing BGA ball. Instead of shrinking, the non-collapsing land size gets larger to handle the solder volume that creates the solder joint. This technology is new to the electronics industry and was created as a solution for lead-free BGA balls and via-in-pad technology as a routing solution for fine pitch BGA components.

Figure 3: Non-Collapsing 0.5 mm pitch BGA

Figure 3: Non-Collapsing 0.5 mm pitch BGA

  • Via-in-Land Technology          Trace/Space & Grid Data
  • BGA Ball Size: 0.15                               Trace Width: 0.075
  • BGA Land Dia: 0.275                          Trace/Trace Space: 0.075
  • Hole Size: 0.15                                       Trace/Via Space: 0.075
  • Thermal Relief Required                   Trace/BGA Land: 0.075
  • Plane Clearance: 0.425                     Routing Grid: 0.05
  • Solder Mask: 1:1 scale                        Part Place Grid: 1

IPC-7351A has a 3-Tier BGA formula for Placement Courtyards that uses the BGA ball size to calculate an adequate placement courtyard for BGA rework tools.

If the BGA has a large ball size, larger rework equipment is necessary to unsolder the large solder volume. With a small ball size, the placement courtyard can be smaller as less heat is then required to unsolder the BGA component for rework.  However, the end user may not plan to rework the BGA if it fails.  In that case, there is no need to have a robust placement courtyard.

Table 3 below represents the 3-Tier scenario and the different placement courtyard excess size determination.

Table 3: BGA Density Levels for Placement Courtyard Size Determination

Table 3: BGA Density Levels for Placement Courtyard Size Determination

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