Mentor.com Blogs Tom Hausherr's Blog PCB Design Perfection Starts in the CAD Library – Part 8

PCB Design Perfection Starts in the CAD Library – Part 8

Tom Hausherr's Blog: Electronic Component Packages and PCB Libraries

December 2nd, 2010, by Tom Hausherr | Permalink

Tags: CAD Libraries, Padstacks, PCB Design

Padstacks

Padstack creation is something every CAD tool will eventually have to incorporate because it expedites and optimizes CAD library construction. You can download the IPC-7351B Padstack Naming Convention here – AppNote 10833: IPC-7251 & 7351 Padstack Naming Convention or http://www.mentor.com/products/pcb-system-design/library-tools/lp-wizard/import-docs

The SMT Padstack is easy -

Top Land
Top Solder Mask
Top Paste Mask
Top Assembly

Part 7 of this blog explains the Land Calculation for SMT land patterns, so let’s discuss Plated Through-hole calculations in this segment.

The Through-hole (PTH) Padstack is complex -

Drill Hole
Top Assembly
Top Solder Mask
Top Land
Inner Land
Plane Thermal Relief
Plane Anti-pad (Clearance)
Bottom Land
Bottom Solder Mask
Bottom Assembly

Here is a picture of a through-hole padstack.

PTH Padstack

The PTH padstack creation can be fully automated via the maximum lead diameter.

Round PTH Lead Rectangle PTH Lead

Rectangle PTH Lead

Square PTH Lead

In the IPC-2222 standard there is a hole size calculation chart -

IPC-2222 Table 9-3

Once you calculate the hole size, the minimum annular ring is 0.05 mm.

IPC-2221 Minimum Annular Ring

Next we need to add the IPC-2221 Minimum Fabrication Allowance to the pad size.

IPC-2221 Table 9-1

So the Minimum Annular Ring X 2 + Minimum Fabrication Allowance + Maximum Lead + Hole Over Lead = Pad Diameter

Next we need to calculate the Plane Thermal Relief ID, OD and Spoke Width sizes.

Thermal Relief Calculations

The Plane Anti-pad or Plane Clearance is the same size as the Thermal Relief OD (Outside Diameter).

In both the SMT and PTH padstack, the IPC recommended Solder Mask and Paste Mask size is 1:1 scale of the Top and Bottom land size. The PCB fabrication shop can automatically oversize (swell) the solder mask to any size they need to insure high yield production per their specific manufacturing capabilities. This is where automation of padstack generation comes in. The entire concept is to generate a padstack that meets the environment class of your design specification.

The IPC-7251 Through-hole land patterns have the capability of accommodating all three performance classiﬁcations.

Producibility Levels: When appropriate this standard will provide three design producibility levels of features, tolerances, measurements, assembly, testing of completion or veriﬁcation of the manufacturing process that reﬂect progressive increases in sophistication of tooling, materials or processing and, therefore progressive increases in fabrication cost. These levels are:

Level A General Design Producibility – Preferred [Maximum land\lead to hole relationship]
Level B Moderate Design Producibility – Standard [Nominal land\lead to hole relationship]
Level C High Design Producibility – Reduced [Least land\lead to hole relationship]

The producibility levels are not to be interpreted as a design requirement, but a method of communicating the degree of difficulty of a feature between design and fabrication/assembly facilities. The use of one level for a speciﬁc feature does not mean that other features must be of the same level. Selection should always be based on the minimum need, while recognizing that the precision, performance, conductive pattern density, equipment, assembly and testing requirements determine the design producibility level. The numbers listed within the tables of IPC-7251 are to be used as a guide in determining what the level of producibility will be for any feature. The speciﬁc requirement for any feature that must be controlled on the end item shall be speciﬁed on the master drawing of the printed board or the printed board assembly drawing.

Download the IPC-7251 padstack charts here – AppNote 10835: IPC-7251 Padstack Charts

Density Level A: Maximum Land/Lead to Hole Relationship – The ‘maximum’ land pattern conditions have been developed to accommodate the most robust producability of the solder application method. The geometry furnished may provide a wider process window for solder processing. The level A land patterns are usually associated with low component density product applications.

Density Level B: Nominal Land/Lead to Hole Relationship – Products with a moderate level of component density may consider adapting the ‘median’ land pattern geometry. The median land patterns furnished for all device families will provide a robust solder attachment condition for most soldering processes and should provide a condition suitable for wave, dip, drag or reﬂow soldering.

Density Level C: Least Land/Lead to Hole Relationship – High component density typical of portable and hand-held product applications may consider the ‘minimum’ land pattern geometry variation. Selection of the minimum land pattern geometry may not be suitable for all product use categories.

The “Proportional” PTH Padstacks are a mixture combination of all the IPC Levels. Small holes use Level C and medium hole sizes use Level B and large hole sizes use Level A. When a hole size exceeds 2 mm, the Proportional padstack annular ring will incrementally grow with every hole size. I have used the proportional padstacks for the past 20 years and it is proven technology that works. Its flexible flow is more compliant with the PTH components and their pin pitch density. The main point is that Proportional padstacks meet or exceed the IPC-7251 standard.

Download the Proportional padstack chart here – Appnote 10836: Proportional Through-hole Padstacks

Note: the “Producibility Levels” are not necessarily related to the IPC Preformance Classifications. i.e.: The IPC-7251 land patterns have the capability of accommodating all three performance classiﬁcations.

IPC Performance Classifications: Three general end-product classes have been established to reﬂect progressive increases in sophistication, functional performance requirements and testing/inspection frequency. It should be recognized that there may be an overlap of equipment between classes.

The end product user has the responsibility for determining the ‘‘Use Category’’ or ‘‘Class’’ to which the product belongs. The contract between user and supplier shall specify the ‘‘Class’’ required and indicate any exceptions or additional requirements to the parameters, where appropriate.

Class 1 General Electronic Products – Includes consumer products, some computer and computer peripherals, and hardware suitable for applications where the major requirement is function of the completed assembly.

Class 2 Dedicated Service Electronic – Products Includes communications equipment, sophisticated business machines, and instruments where high performance and extended life is required, and for which uninterrupted service is desired but not mandatory. Typically the end-use environment would not cause failures.

Class 3 High Reliability Electronic Products – Includes all equipment where continued performance or performance-on-demand is mandatory. Equipment downtime cannot be tolerated, end-use environment may be uncommonly harsh, and the equipment must function when required, such as life support systems and other critical systems.

Comments (↓ Add Your Own)

13 comments on this post

Commented on December 4, 2010 at 3:56 pm
By me

Brocken Link.
You can download the IPC-7351B Padstack Naming Convention here – AppNote 10833: IPC-7251 & 7351 Padstack Naming Convention. – Oops! This page appears broken. HTTP 404 – File not found.

Commented on December 4, 2010 at 4:59 pm
By Tom Hausherr

Try this – http://www.mentor.com/products/pcb-system-design/library-tools/lp-wizard/import-docs

Commented on December 7, 2010 at 12:54 am
By gmdelcampo

Maybe IPC should consider adopting the “Proportional” level.

Commented on December 7, 2010 at 8:19 am
By Tom Hausherr

I asked IPC about it and they told me that they cannot adopt it because it meets or exceeds the current standard. They consider that duplication.

Commented on December 26, 2010 at 1:45 pm
By Tran

Hi Tom,

Is it possible to permanently add more layer as a default along with the Mounted side, Opposite and the inner layers into the padstack?

Commented on December 26, 2010 at 7:01 pm
By Tom Hausherr

What layers would you need to add?

I am interested to know.

Tom

Commented on December 27, 2010 at 12:49 pm
By Tran

Follow up my last question regarding adding more layer into the default layer group.
I would like to add the 2 soldermask top [mounted]and bottom [opposite]layers.

Rgds,

Tran

Commented on December 27, 2010 at 12:56 pm
By Tom Hausherr

Tran,

So you want to add 2 different solder mask top and bottom layers so that you can call out those layers when you post process your solder mask Gerber data.

This is the very reason why IPC recommends that you simply size your solder mask 1:1 scale of the Land (pad) Size and tell the manufacturer to oversize your solder mask.

But I completely understand if you want to be in complete control of your solder mask sizes.

Tom

Commented on January 12, 2011 at 1:58 pm
By BenG

Tom -

Can you comment on how Via Technology pad sizes were calculated in AppNote 10830? I often use an 8mil hole / 18mil pad via in my designs. Based on what I find in IPC-2221, section 9.1.1 (Land Requirements), this via would violate the minimum annular ring requirements.

Ben

Commented on January 12, 2011 at 2:20 pm
By Tom Hausherr

Try this master URL that points to all the app notes – http://www.mentor.com/products/pcb-system-design/library-tools/lp-wizard/import-docs

Tom

Commented on January 12, 2011 at 2:23 pm
By Tom Hausherr

Ben,

The term “Land” refers to a PCB feature for soldering a component lead.
Via’s are different and your 10 mil (0.025 mm) annular ring is OK for vias.

Tom

Commented on March 2, 2011 at 9:24 pm
By David

Tom,
Great article, but I have some questions.
You show values for IPC-2221 Table 9-1 that are much different than those I see in the spec. Similarly, I do not understand how the values you provide for “Thermal ID over Hole Size”, “Thermal OD over Hole Size” and “Thermal OD over ID” are derived.

Thanks,
David

Commented on March 3, 2011 at 9:29 am
By Tom Hausherr

David,

In the IPC-2221 standard Table 9-1 illustrates the “Minimum Fabrication Allowance”.

We are working on the new IPC-7251 for through-hole land patterns for a 3-Tier CAD library standard and that is where I got my numbers for Table 9-1. I made a typo. “Min Fabrication Allowance” really should be “Nom Fabrication Allowance” and I should have mentioned the IPC-7251 standard that will be released later this year.

The entire through-hole padstack construction is clearly defined in the IPC-7251. I am on the executive committee for that standard and the values in the IPC LP Calculator reflect all the new values. The IPC-2221 focuses on manufacturing “Minimum” requirements while the IPC-7251 focuses on “Nominal” manufacturing requirements. So the text “Min” in Table 9-1 in the blog should read “Nom” and probably refer to the IPC-7251.

Thanks for catching this typo. I really appreciate when people challenge the standard for the purpose of perfecting it.