PCB Design Perfection Starts in the CAD Library – Part 2

Chip Components Smaller Than 1608 (EIA 0603)

Before you read this blog ‘Part 2″, read Part 1 White Paper of this series – “PCB Design Perfection Starts in the CAD Library” for the introduction information. Download it here – http://www.mentor.com/products/pcb-system-design/techpubs/download?id=60454

Parts 3, 4, 5 etc. will be posted here over the next couple weeks. I’m really looking forward to your feedback on this subject. I believe that everyone who follows these basic rules will increase productivity levels in their PCB design layouts.

See Figure 6 for the dimensions of a standard 1005 (EIA 0402) component superimposed with its related land pattern. In this case, I decided to break 2 rules –

1.       Land size round-off 0.05 mm

2.       Land snap grid round-off 1.0 mm

The land center to land center spacing is 1.0 mm which is perfect for 1.0 mm space via fanout and the placement courtyard width is 1.0 mm which is perfect for placing parts 1.0 mm from center to center.

When placing the 1005 in the PCB layout use a 0.1mm grid to optimize the part placement and via fanout.



The 1005 (EIA 0402) was made for 1mm pitch BGA fanout. In Figure 7 you can see 2 different fanout options and one is superior to the other. The fanout coming out the top has all the key features. The vias are 0.25 mm closer to the capacitor component terminals than the typical right/left fanout which decreases impedance and increases capacitance. Also, the top fanout vias snap to a 1 mm grid because the 1005 land pattern was snapped to a 0.1 mm grid system. The 0.5 mm via land (pad) diameter with 0.25 mm hole size and 0.7 mm plane anti-pad is perfect for 0.1mm trace/space technology. See Figure 4. The trace width for the power fanout is 0.3 mm.



See Figure 8 for the dimensions of a standard 0603 (EIA 0201) component superimposed with its related land pattern. In this case, I decided to break 2 rules –

1.       Land size round-off 0.05 mm

2.       Land snap grid round-off 1.0 mm

3.       Use the “Least” environment due to component miniaturization

For chip components smaller than 1 mm X 0.5 mm I use the IPC-7351B Least Environment to prevent tombstoning. When 2 pin micro-miniature parts have too much solder volume tombstoning can occur in the reflow oven. The land size for the 0603 should be slightly more than 2 times the terminal lead size.



One of the techniques that can be used to prevent tombstoning for the 0603 (EIA 0201) is to thin the paste stencil from 0.15 mm to a smaller value for every occurrence of this component in the paste mask stencil. See Figure 9. The responsibility of the stencil thickness thinning process is placed on the assembly shop and the stencil manufacturer (not the PCB designer). Assembly shops use various solder alloys that require unique stencil creation.



See Figure 10 for the dimensions of a standard 0603 (EIA 0201) component superimposed with its related land pattern. If you normally use the “Most” environment, my recommendation for the 0603 (EIA 0201) land pattern is to use the “Nominal” environment. The IPC nominal land size for the 0603 is about 3 times the size of the terminal lead. For this 0603 micro-miniature component, stay away from the “Most” environment as the solder volume is more than 4 times greater than the terminal lead footprint.



 The 1005 (EIA 0402) & 0603 (EIA 0201) chip components are very compatible with 1 mm pitch BGA. In Figure 11 there are 2 uses for the 1005 and one in-between the vias and one via-in-pad method. Because the 1005 land centers are on 1 mm pitch, the capacitor land (pad) falls directly centered on the via. Via-in-Pad technology will increase PCB cost because these vias need to be plated, filled and surface finish on the capacitor pad. The 0603 fall in-between the vias for the 0.1 mm trace/space technology DRC. This solution will not increase PCB fabrication cost. The dot grid display is 0.05 mm.



IPC does not have a “standard” on drafting items such as silkscreen and assembly outlines and polarity markings yet.  There are several types of silkscreen outlines and polarity markings that are used for Non-polarized Chip parts, Polarized Capacitors, Diodes and LED’s.

For a standard Non-polarized chip there are 2 options. See Figure 12 for both options. One is a line that separates the 2 lands. The default size is 0.2 mm and the default silkscreen the land gap is 0.25 mm. The CAD librarian can change both the line width and the gap to achieve placing a line between two lands that only have a 0.3 mm Gap by simply changing the line width and gap rules to 0.1 mm.



See Figure 13 for the silkscreen outline for the Chip Diode. The Chip Diode also has a Post Assembly Inspection Dot so you can visually verify if the assembly inserted the Diode or LED in the correct rotation. The Polarized Chip Capacitor would have the same exact silkscreen outline but without the 0.6 mm bar.



The Assembly Drawing Outlines and Polarity Markings are totally different than the Silkscreen Outlines and Polarity Markings. The first most obvious difference is that the outline shape is 1:1 scale of the component body. This outline can be either the “Nominal” or “Maximum” component body size. Another difference is the Reference Designator is centered inside the component outline and is never moved or relocated. The reference designator default size is 1.5 mm height with a 10% line width.

The Reference Designator and Assembly Outline only change rules for micro-miniature parts. The Assembly Outline will grow as large as the placement courtyard in order to fit the Reference Designator inside the Assembly Outline. When the component gets smaller, the Reference Designator will decrease from the default 1.5 mm height to a sliding scale of values until it fits inside the assembly outline. The reference designator scaling width is always 10% of the height. The various reference designator heights for micro-miniature components are –

·         0.15 mm

·         0.125 mm

·         0.1 mm

·         0.075 mm

·         0.05 mm (this is the smallest human readable text height)

See Figure 14 for the non-polarized and polarized capacitor, diode and resistor assembly outlines and Reference designators. Notice the absence of land pads. From all Chip and Molded Body components, the Land is removed from the SMT padstack to insure that the reference designators are unobstructed. Also, for CAD tools that have this feature, Right Reading Orthogonal is always recommended so when the component is rotated, the reference designator is always flipped to right reading orientation.



Read Part 3 “Molded Body Components” coming up next.

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9 comments on this post | ↓ Add Your Own

Commented on June 23, 2011 at 9:10 am
By Alex Wong

Hi Tom, find your post recently. Sound nice and going to be useful, as gonna create CAE and PCB decals for project design. Going to read all the parts, so I shall do with right design practices from start.

Btw, couldn’t receive the direct download link for part 1 even I submitted via the link. Any advise? Will you consider compiling the parts into a good reference pdf.

Thank you again for your great effort.

Commented on June 23, 2011 at 9:41 am
By Tom Hausherr

Part 1 is a PDF file that you can download. Register here for it –

Part 19 – “Breakaway Tabs” is being released later today (or tomorrow morning).

Commented on June 24, 2011 at 3:14 am
By Alex Wong

Thanks Tom.
Notice that the chip land pattern is rounded rather than typical rectangular pad. Can you share what is advantages to use rounded one?

Commented on June 24, 2011 at 7:43 am
By Tom Hausherr


The lands (pads) for all SMT land patterns (except BGA, LGA and CGA) should have rounded rectangular corners. They are easier to manufacture in fabrication. The Paste Mask Stencil aperture opening all have rounded corners (they are created by laser. If you look at all the solder joints in Chip or Molded Body capacitors, diodes and resistors, after the PCB assembly comes out of the reflow oven, all solder in the corners is gone. The heat pulls the solder toward the component lead leaving no solder in the corner areas. There are graphic pictures in the J-STD-001 assembly guideline that clearly illustrate this. “Rounded Rectangle Pad Shape” is also better for Lead-Free solder process. You can also add aditional routing and via channels in your PCB layout. I’ll discuss this in a future article.

Commented on June 30, 2011 at 4:46 am
By Alex Wong


I just wonder, if rounded rectangular corners are better to use, why not just standardize it to all SMT components?

In my building of CAD library, I also refer to some included patterns from PADS9.3, e.g. SMM7531B and they are have sharp rectangular corner.

Look forward your article on this subject.

Commented on August 19, 2012 at 5:34 pm
By Roderick Mann

Tom, thanks a lot for this excellent series. Although I’m mainly a hobby designer, I try to do it right. I also use OS X, which means my choice in tools is very limited. Playing around with the LPC viewer, I was having trouble understanding the courtyard line width.

in the starter PLB file, component CAPC0603X33N, it seems that the standard calls for a 0.2 mm courtyard line thickness. But what the viewer is displaying is much thinner. Can you explain what’s going on there? Thanks!

Commented on August 6, 2013 at 10:25 am
By Sam Reaves


Is it possible to download all of the PCB Design Perfection series as a PDF for off line reading?



Commented on November 15, 2013 at 6:07 am
By Patrick Vignal

Hi Tom,
your link to Part 1above doesn’t work anymore…
Here the updated one: http://www.mentor.com/pcb/techpubs/request/pcb-design-perfection-starts-in-the-cad-library-part-1-the-1608-eia-0603-chip-component-60454
It works at least today… =)

Commented on June 17, 2014 at 12:48 am
By Vic Main

Thanks very much for this series, it’s been very helpful in understanding the best practice. I did not what I think is an error in Figure 10. The measurement for the courtyard X dimension should be 1.550 –(.35 +..275 +.15) *2 and not 1.7mm.

Thanks again!!

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