Tom Hausherr's Blog

New component package technology and CAD library standards.

23 June, 2011

PCB Breakaway Panels

 As PCB part placements get denser, it’s necessary to add breakaway panels that add additional board material (edge rails) to accommodate the assembly process. Two parallel edges are required for a PCB to be processed in the SMT line. This is to prevent skewing through the conveyor system. Also, all odd shaped PCB’s must have edge rails incorporated to meet this requirement. Custom reflow fixtures will be made, at an additional cost to you, if this requirement is not met. The breakaway tabs remain intact all the way through the assembly process and are removed at the final stage.

V-Grove Score and Tab Routing are two common methods used for creating breakaway tabs. Tab Routing uses perforated breakaway tabs (sometimes referred to as “Mouse Bites”). The breakaway tab closest to the PCB corner should be located between 10 mm and 12 mm from the edge to reduce sagging during reflow or wave soldering. It is also preferred to have at least one tab per side. If the PCB placement is too dense for a Tooling Hole, then it should be placed on the breakaway tab. See Figure 1 for the optimized breakaway tab solution.

Note: all dimensions in this paper are in millimeter units.

Figure 1 - Example of Breakaway Panel

 One important aspect is to have a clean edge after the breakaway tab is removed. Slight inset of perforation is preferred because it provides an edge which requires little to no additional labor to clean up. Figure 2 illustrates the perforation location preferences.

Figure 2 - Breakaway Perforation Locations

 The spacing between breakaway tabs can range from 60 mm to 90 mm, but I recommend 77 mm from center to center as shown in Figure 3. Try not to exceed 100 mm between tabs and try to evenly space them apart.

Figure 3 - Breakaway Tab Spacing

 The plane pull-back should be at least 1 mm from all slots and perforation holes. All trace routing needs to be over a plane for clean return path so keep all routing 1 mm from all slots and perforation holes. Keep components 2 mm – 3mm away from the routed slots. These rules help prevent components or trace damage during the de-paneling process. See Figure 4 to define the keep-out areas in the PCB layout.

Figure 4 - Plane & Component Spacing

 Tab routing is more precise than V-groove scoring and edge surfaces are smooth. The breakaway tab points require consideration for additional smoothing if necessary to comply with the fabrication drawing note regarding smooth edges. The dilled perforation provides a low stress break point on the tab and if the hole pattern is recessed within the printed board edge, secondary sanding or grinding can be avoided.

 It is not recommended to substitute perforation holes with a V-groove score as it does not provide a durable tab that will withstand handling. V-groove scoring can however be used in place of routing, but requires board edge grinding to smooth the surface. The V-groove feature is generally provided on both sides of the PCB and only in a straight line. A V-Groove depth that will provide a sturdy work-piece and still separate with light to moderate pressure after assembly is an important element in manufacturing. Many PCB fabrication shops recommend a V-grove depth that is 1/3 of the PCB thickness from both sides using Computer Numerical Control (CNC) equipment. The alignment or positional accuracy of the two grooves is critical for clean separation and minimizes post separation board edge smoothing. According to IPC-2222 Section 5.3.1, the alignment tolerance for the V-groove is ±80 µm. Figure 5 illustrates the 90° scoring option. It is important that all conductors be routed within a minimum distance of 1 mm from the top of the scoring edge to prevent damage during de-paneling. The inner layer planes should be pulled back 1 mm from the V-groove. The PCB designer should collaborate with the PCB fabrication shop on the V-groove angle option that they use.

Figure 5 - 90 Degree V-Groove Scoring

 Figure 6 illustrates the 30° scoring option and uses the same rules.

Figure 6 - 30 Degree V-Groove Scoring

 It is important to note that the 1/3 depth rule only applies to “Breakaway Panels”. V-Groove scoring inner web material can range from 0.15 mm to 0.4 mm for panel separation depending on the length of the score. If the score length is less than 25 mm, it can have a web thickness of 0.15 mm and scores that are 100 mm long can have a web thickness of 0.25 mm and scores that are longer than 100 mm can have a web thickness of 0.4 mm. These values are just guidelines and should be discussed with your assembly shop to confirm the web thickness for your printed circuit board design.

 

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13 June, 2011

Periphery Solder Joint Goals

When it comes to solder joint goals, we are familiar with the terms Toe, Heel and Side solder joint fillets, but IPC introduced the Periphery solder joint in the latest release of the IPC-7351B. Due to the indoctrination of several new component families like Dual Flat No-lead (DFN), Land Grid Array (LGA), Pull-back Quad Flat No-lead (PQFN), Pull-back Small Outline No-lead (PSON) and Column Grid Array (CGA), IPC created the Periphery solder joint goal to accommodate these “Bottom only terminal” lead forms as seen in Figure 1.

Figure 1 - Components with Bottom Only Terminal Leads

Figure 1 - Components with Bottom Only Terminal Leads

The flat leads of these component families are very compatible with lead-free solder, due to the fact that some lead-free solder alloys have low-flow wetting properties. The flat lead with a Periphery land area also improves assembly accuracy as the components have minimal “wander” movement during the reflow process. This is unlike the typical chip resistor & capacitor has a wrap-around component lead. Great caution must be taken into consideration because the J-STD-001D assembly standard allows for chip component overhang of up to 50% of the component width for Class 1 and Class 2 and 25% for Class 3 (the “A” dimension) as seen in Figure 2.

Figure 2 - Acceptable Wrap-around Lead Solder Joint

Figure 2 - Acceptable Wrap-around Lead Solder Joint

The new DFN component family has 2, 3 and 4 lead package styles and the body sizes range from 16 mm to 1 mm in size. The 2-pin DFN package is intended to replace wrap-around leaded chip resistors, diodes and capacitors. The component terminal leads for pin 1 and 2 can be different sizes. The DFN component package data is derived from the JEDEC MO-236A standard. The 3-pin DFN package is intended to replace gull wing leaded SOT23 and DPAK transistors and voltage regulators. The 4-pin DFN package is intended to replace a variety of different component families including oscillators, bridge rectifiers, LED’s, sensors, etc. The Periphery solder joint goals as seen in Table 1 are used for the DFN, PSON and PQFN component families.

Table 1 - DFN, PSON and PQFN Solder Joint Goals

Table 1 - DFN, PSON and PQFN Solder Joint Goals

The LGA component family usage is rapidly growing. The LGA component lead style can be a bump which is typically a round shape. The LGA component lead style can also be flat which can be round, square or irregular shape. The pin assignments typically follow the same JEDEC convention as BGA’s. The LGA component package data is derived from the JEDEC MO-270B standard. See Figure 3 for the LGA lead styles.

Figure 3 - LGA Lead Styles

Figure 3 - LGA Lead Styles

See Figure 4 for the LGA lead shapes.

Figure 4 - LGA Lead Shapes

Figure 4 - LGA Lead Shapes

The LGA land pattern only has one tier environment similar to the BGA however; the LGA land size is 1:1 scale of the lead size. See Table 2 for the LGA solder joint goals.

Table 2 - LGA Solder Joint Goals

Table 2 - LGA Solder Joint Goals

Multi-row & column LGA’s will require via-in-pad routing solutions for the inner rows of contacts because there is no room for the traditional “dog bone” via fanout. Figure 5 represents a 1.0 mm pitch LGA with 0.7 X 0.7 mm square lands with a flat lead. You can place 0.5 mm pad & 0.25 mm hole vias in the center of the lands and be able to route two 0.1 mm traces between the vias.

Figure 5 - LGA Via Fanout

Figure 5 - LGA Via Fanout

Unlike Pin Grid Arrays (PGA) that have been common to microprocessors, LGA’s do not utilize any pins but rather an array of bare gold plated copper pads that permit a direct electrical connection between the component substrate and the PCB. Compared to the PGA component family, LGA pad density can be significantly higher due to tighter spacing that is not hindered by the need to attach pins to the substrate.

Linear Technology is the world’s leading producer of LGA component packages. Linear uses unpopulated component leads in many of its component packages as seen in Figure 6.

Figure 6 - Linear LGA Packages with Unpopulated Leads

Figure 6 - Linear LGA Packages with Unpopulated Leads

The BGA land is considered the first “periphery” land introduced to the electronics industry. However, the collapsing BGA ball is the only land calculation that creates a smaller land than the component lead. Non-collapsing BGA balls require a larger land size than the ball size. Via-in Pad in a flat lead LGA produces better solder joint results than BGA technology because there are no “Voids” in the flat LGA component lead after reflow. Figure 7 is a BGA ball cross-section that illustrates trapped air hole using via-in-pad BGA void issues.

Figure 7 - BGA Void

Figure 7 - BGA Void

However, voids created by trapped air in blind or through-hole vias can be eliminated by plugging or filling the hole prior to the land plating process. Figure 8 illustrates various types of vias that contribute to trapped air and that causes voids in BGA balls.

Figure 8 - BGA Voids From Trapped Air

Figure 8 - BGA Voids From Trapped Air

The Pull-Back Small Outline No-lead package (PSON) is a rectangular semiconductor package with metal terminals along two sides of the bottom of the package. The Pull-back leads are typically 0.1 mm to 0.2 mm away from the component body edge. The body of the component is generally molded plastic and the plastic mold compound is present on all 4 sides of the terminal lead contact. The SON and PSON component families are intended to replace the leaded SOIC and takes up about 50% less PC board area footprint. The PSON is considered a leadless package design with a bottom paddle to conduct heat away from the package used stitch vias that attach to the GND plane.

The Pull-back component lead terminal shown in Figure 9 represents the Pull-back Small Outline No-lead (PSON) and Pull-back Quad Flat No-lead (PQFN) which have two different lead shapes, D-shape and rectangular. These illustrations are 0.8 mm pitch 5 mm X 5 mm body outline.

Figure 9 - PSON & PQFN Lead Shapes

Figure 9 - PSON & PQFN Lead Shapes

Note: the latest LP Wizard and LP Calculator 10.3.1 release introduces the D-shape land calculation and CAD export to tools that support D-shape lands.

See Table 1 for the IPC-7351B 3-Tier land pattern environments for PSON and PQFN component lead form with the Periphery solder joint goals.

Ceramic and Plastic Column Grid Arrays (CGA) solder column contacts are used for larger ceramic-based packages (32.0 mm to 45.0 mm). The package resembles the earlier plated through-hole pin-grid-array but with closer contact pin pitch. The column contact diameter is typically 0.5 mm for 1.0 mm pin pitch and 1.2 mm to 2.0 mm lead length. The columns are attached to the package either by eutectic (Pb37Sn63) solder or they are cast in place using 90% Pb and 10% Sn. Via-in-pad technology is popular with the 1.0 mm pitch CGA component family due to the lack of room for a typical bog-bone via fanout.

The longer columns typically increase solder joint reliability by absorbing the stresses created by the CTE mismatch between the ceramic package and the PC board. On the other-hand, longer columns may reduce electrical performance and will increase the overall package profile on the PCB. Also, the columns are not as rugged as a BGA solder joint and are susceptible to handling damage.

The Column Grid Array was grouped with the LGA component family solder joint goals in the IPC-7351B at 1:1 scale lead to land size, but the CGA solder goals were recently been updated so that the land size is 0.1 mm larger than the maximum lead diameter. Figure 10 illustrates the CGA solder joint goal with a periphery land to form a solder fillet and Table 3 has the solder joint goal data.

Figure 10 - CGA Solder Joint

Figure 10 - CGA Solder Joint

Table 3 - CGA Solder Joint Goals

Table 3 - CGA Solder Joint Goals

The DFN, PSON, PQFN, LGA, CGA and BGA have a different concept for developing a land pattern. Effectively, there are no toe, side or heel fillets; rather the land periphery is similar about the entire termination. Whether the component terminal shape is round, square, rectangle or D-shape, once the tolerance is assigned it applies to the periphery of the lands for that particular part. Thus the term “Periphery” is used to signify that the principles occur all around the component package termination contact.

Did you know that the LP Wizard fully supports all the component families listed in this article? You can download the free 10-day trial license for the newly released LP Wizard 10.3.1 that now produces D-shape land style for PQFN and PSON component families here – http://www.mentor.com/go/lpwizard

After the 10-day trial license ends, there is no need to uninstall the program as the LP Wizard will run in “Demo Mode” (without a license) as an IPC-7351B LP Calculator.

3 June, 2011
IPC introduced a new padstack naming convention in the IPC-7351B standard publication and it is used exclusively in the Mentor Graphics LP calculator. This article explains the breakdown of the new standard and its benefits.

The padstack consists of combinations of letters and numbers that represent shape, or dimensions of lands on different layers of printed boards or documentation. The name of the padstack needs to represent all the various combinations. These are used in combination with the land pattern conventions defined herein according to the rules established in the IPC-2220 Design standards.

The first part of the padstack convention consists of a land (pad) shape. There are six basic land shape identifiers. Note: All alphabetical characters are “lower case”. This helps discriminate numeric values.

Basic Land Shape Letters –

  • c = Circular
  • s = Square
  • r = Rectangle
  • b = Oblong
  • d = D-shape (Square on one end and full radius on the other end)
  • u = User defined contour (Irregular shape)

 The “b” was used for Oblong because the letter “o” can easily be confused with the character zero “0”.

 The next section of the naming convention addresses assumed defaults. This is to keep the default padstack name short and simple. Any deviations from these padstack defaults require the use of special modifiers.

  • Solder Mask is 1:1 scale of the land size
  • Paste Mask is 1:1 scale of the land size
  • The Assembly Layer land is 1:1 scale of the land size

  • Inner Layer Land is the same shape as the outer layer land

  • The Primary and Secondary lands are the same size

  • The inner layer land shapes are Circular

  • Vias are Circular

  • Thermal ID, OD and Spoke Width sizes follow the IPC Level A, B or C

  • Thermal Reliefs have 4 spokes

  • Plane Clearance Anti-pad size follows the IPC Level A, B or C

  • Mounting Holes are Circular

 Every board fabricator’s ability to register solder mask is different. The 1:1 scale solder mask default compensates for the variation, and so long as manufacturers are building to standard specifications such as the IPC-6012 that states you can’t have miss-registration of the solder mask. It’s important that when you are creating a CAD library that will be used for various trace/space combinations, that you leave the responsibility of the solder mask swell up to the fabrication CAM operator when they are panelizing your Gerber or ODB++ data. By having all of the solder mask sizes 1:1 scale of the land (pad) size, you are providing the manufacturer with a known starting point for them to work with.

I need to explain an exception to this rule for creating solder mask defined lands for BGA’s. IPC does not recommend solder mask defined BGA CAD library parts but some companies use this technique for very fine pitch parts that require a small diameter land size. In this case, the solder mask acts as an adhesive to secure the land to the PCB Prepreg to withstand drop testing for hand held electronic products. It has been proven in drop tests for hand held electronic devices that a fine pitch BGA solder joint is more secure than the land attachment to the Prepreg. i.e.: during drop testing, a fine pitch BGA pad will rip away from the PCB Prepreg material before the BGA solder joint fails. See the picture on the right side in Figure 1 as an example of a solder mask defined BGA land.   

Figure 1 - Solder Mask Defined BGA Land

Figure 1 - Solder Mask Defined BGA Land

 

 Solder mask defined lands are also used for Flexible circuit boards for the same reason, to hold the land (pad) to the PCB surface to prevent the land from ripping away from the PCB material. When you use solder mask defined lands you must indicate which parts deviate from the 1:1 scale solder mask rule in the fabrication drawing notes to notify the CAM operator not to swell these solder mask features.

 In the padstack naming convention there are illegal characters that should never be used. These include “ ” , ; : / \ [ ] ( ) . { } * & % # $ ! @ ^ =

 Examples utilizing the “Basic Land Shape Letters” (all padstack values are in metric units)

 Note: Every number goes two places to the right and as many places as needed to the left of the decimal

 Examples: 1150 = 11.50 mm or 11500 μm, 150 = 1.50 mm or 1500 μm, 15 = 0.15 mm or 150 μm

c150h90 - where “c” denotes a Circular land with a 1.50 diameter and H denotes a hole size of 0.90

v50h25 – where a “v” denotes a via with a 0.50 land (default Circular land) and H denotes a 0.25 hole

s150h90 – where “s” denotes a 1.50 Square land and H denotes a hole size of 0.90

s350 – where ‘s” denotes a square SMT land size of 3.50

r200_100 – where “r” denotes a Rectangular SMT land 2.00 land length X 1.00 land width

b300_150 – where “b” denotes a SMT Oblong land size of 3.00 X 1.50

b400_200h100 – where “b” denotes an Oblong land size of 4.00 length X 2.00 width and 1.00 hole

d300_150 – where “d” denotes land with one circular end and one square end (looks like a D) 3.00 X 1.50

v30h15l1-3 – where “v” denotes a 0.30 blind via with 0.15 Hole; 1 is the starting layer, 3 is the end layer

r200_100r5 – Rounded Rectangular 2mm X 1mm X 0.05mm radius corners

r200_100c10 – Chamfered Rectangular 2mm X 1mm X 0.1mm chamfered corners

v30h15l3-6 – where “v” denotes a 0.30 buried via with 0.15 Hole; 3 is the starting layer, 6 is the end layer

  Special modifiers are used when padstack features are different than the defaults. These are the “Variants” or “Modifiers” that go after the basic padstack naming convention.

 These are used when the User needs to change the padstack default values either by a different dimension or a different shape. In instances where shapes are different this becomes a two letter code with the modifier first followed by the land shape letter.

 

These are single letter modifiers –

n = Non-plated Hole

z = Inner Layer land dimension if different than the land on primary layer

x = Special modifier used alone or following other modifiers for lands on opposite side to primary layer land dimension

t­ = Thermal Relief; if different than IPC standard padstack – tid_od_sw for 4 spoke default      

m = Solder Mask if different than default 1:1 scale of land

p = Solder Paste if different than default 1:1 scale of land

a = Assembly surface land if different than default 1:1 scale of land

y = Plane Clearance (Anti-pad) if the value is different than the Thermal OD

o = Offset Land Origin

k = Keep-out

r = Radius for Rounded Rectangular Land Shape

c = Chamfer for Chamfered Rectangular Land Shape

 

These are double letter modifiers –  

ts = Thermal Square; if different than the top side land shape and dimensions

sw = Thermal spoke width

zs = Inner Layer Land Shape is Square (Note: The default is circular)

m0 = No Solder Mask

mxc = Solder Mask Opposite Side Circular

mx0 = Solder Mask Opposite Side No Solder Mask

xc = Opposite Side Circular

vs = Via with Square land

hn = Non-plated Hole

 

 Land shape change is the last letter in the string prior to the dimension.

 Examples of single letter modifiers with a Circular Plated Through-hole land –

c150h90 = Default padstack with a 1.50 circular land with a 0.90 hole (no modifiers used)

c150hn90 = Default padstack with a 1.50 circular land with a 0.90 non-plated hole (no modifiers used)

c150h90z140 = Inner layer land is smaller than external lands 1.40 or 0.10 smaller

c150h90z140x170 = Opposite side land is larger than top side land 1.70 or 0.20 larger

c150h90z140x170m165mx185 = Solder mask opening for top and bottom lands 0.15 larger for each

c150h90z140x170m165mX185a200 = Assembly drawing land in 0.50 larger than 1.50 primary land

c150h90z140x170m165mx185a200y300 = Plane clearance anti-pad diameter is 3.00

c150h90z140x170m165mx85 = Solder mask encroachment on opposite land by 0.65 smaller

c150h90m165 = adding a solder mask opening of 1.65 diameter or 0.15 larger than land

c150h90t150_180_40 = Thermal ID 1.50, OD 1.80, Spoke Width 0.40, Anti-pad 1.80

c150h90t150_180_40y200 = Anti-pad 2.00 (because the size is different than the Thermal OD)

c150h90t150_180_80_2 = Spoke Width 0.80 with 2 Spokes

c150h90m165t150_180_40 = Solder Mask 1.65

c150h90zc150 = where “c” is Circular 1.50 land with 0.90 Hole with 1.50 inner (Z) Layer Circular land

 

 Examples of single letter modifiers for an Oblong Surface Mount land –

b300_150 = Default padstack with a 3.00 length and 1.50 width land (no modifiers used)

b300_150m330_180 = Solder Mask is 0.30 larger than the land

b300_150m330_180p240_140 = Solder Paste is smaller by 0.10 width and 0.60 length

b300_150b-50 = Oblong Land 3.0mm X 1.5mm w/Offset Origin negative 0.5mm

r400_200po430_230 = Rectangle SMT land 4.00 X 2.00 with a Oblong Solder Paste size of 4.30 X 2.30

 

 Examples of a padstack with Oblong land with Slotted Hole –

Sample – b = Oblong Land Shape then “X” dimension (length) then Underscore _Y” dimension (width)

b400_200h300_100 = Oblong land 4mm length X 2mm width with slotted hole size 3mm X 1mm

b400_200hn300_100 = Oblong land 4mm X 2mm with non-plated slotted hole size 3mm X 1mm

 

 Chamfered & Rounded corner modifiers are used to indicate which corner(s) are modified.

 See figure 2 for the “order of precedence” that has been given to the first 4 modifiers.

Figure 2 - Chamfered Land Variations

Figure 2 - Chamfered Land Variations

 

 Modifiers:

  • bl = bottom left
  • br = bottom right
  • ul = upper left
  • ur = upper right
  • ulr = upper left & right
  • blr = bottom left & right
  • ubl = upper and bottom left
  • ubr = upper and bottom right

 Rounded and Chamfered lands in “one corner” Modifier Examples:

r100_200rbl50 = rectangular land 1.00 x 2.00 with 0.50 radius for rounded corner in bottom left corner

r100_200rbr50 = rectangular land 1.00 x 2.00 with 0.50 radius for rounded corner in bottom right corner

r100_200rul50 = rectangular land 1.00 x 2.00 with 0.50 radius for rounded corner in upper left corner

r100_200rur50 = rectangular land 1.00 x 2.00 with 0.50 radius for rounded corner in upper right corner

r100_200cbl50 = rectangular land 1.00 x 2.00 with 0.50 chamfer for chamfer corner in bottom left corner

r100_200cbr50 = rectangular land 1.00 x 2.00 with 0.50 chamfer for chamfer corner in bottom right corner

r100_200cul50 = rectangular land 1.00 x 2.00 with 0.50 chamfer for chamfer corner in upper left corner

r100_200cur50 = rectangular land 1.00 x 2.00 with 0.50 chamfer for chamfer corner in upper right corner

 

Chamfered and Rounded Rectangular with all four corners chamfered does not need a corner modifier.

Modifier Examples with Rounded Rectangle Land Shape: 

Rounded Rectangular Land Shape

Rounded Rectangular Land Shape

r200_100culr50 = rectangular land 2.00 x 1.00 with 0.50 chamfer for chamfered corners in 2 corners

r200_100c50 = rectangular land 2.00 x 1.00 with 0.50 chamfer for chamfered corners in all 4 corner

 

Modifier Examples with Chamfered Rectangle Land Shape: 

Chamfered Rectangular Land Shape

Chamfered Rectangular Land Shape

r100_200r50 = rectangular land 1.00 x 2.00 with 0.50 radius for rounded corners in all 4 corners

r200_100r50 = rectangular land 2.00 x 1.00 with 0.50 radius for rounded corners in all 4 corners

 

 Thermal pads can have a combination of chamfered and rounded corners however the typical application is 2 variations. The most prominent is a chamfered corner located near pin 1 and the second is a chamfered corner located near pin 1 with the other 3 corners rounded. These two variations are the default.

Square Configurations

Thermal Pad with 4 Square Corners

Thermal Pad with 4 Square Corners

s480p4s152 = 4.80mm Square Land with 4 Paste Mask Squares 1.52mm each

Thermal Pad with Chamfered Corner

Thermal Pad with Chamfered Corner

u480p4s152cul50 = 4.80mm Square Land with 4 Paste Mask Squares 1.52mm each with 0.50mm Chamfer in Upper Left corner

Thermal Pad With Chamfered Corner Rounded Corners

Thermal Pad With Chamfered Corner Rounded Corners

u480p4s152cul50r25 = 4.80mm Square Land with 4 Paste Mask Squares 1.52mm each with 0.50mm Chamfer in Upper Left corner with 0.25mm corner Radius

 

 Example of a Local Fiducial for Fine Pitch SMT Components:

c100m200k200 = Circular Land 1.00 with Solder Mask 2.00 with Keep-out 2.00

s100m200k200 = Square Land 1.00 with Solder Mask 2.00 with Keep-out 2.00

See Figure 3 for Local Fiducial application used for fine pitch components.  

Figure 3 - Local Fiducials

Figure 3 - Local Fiducials

 

 Did you know that you can download a free 10-day trial license for LP Wizard here – http://www.mentor.com/go/lpwizard

 After the 10-day trial license ends, the LP Wizard will run in “Demo Mode” as an IPC-7351B LP Calculator. The LP Calculator auto-generates padstack names using the convention mentioned in this article.  

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4 May, 2011

 Drafting elements in a CAD library part are not “Standardized” for specific values or sizes but there are recommendations that are coming out in the IPC-2610 series that include schematics, PCB assembly and fabrication. Documentation includes component outline and polarity markings for silkscreen and assembly. This article focuses on silkscreen and assembly Reference Designators.

 Every reference designator (Ref Des) originates in the schematic diagram and is transferred to the PCB layout via the netlist. They also appear in the Bill of Material that is exported from the schematic and passed to the assembly shop. The rules for reference designator assignment are established by the IPC-2512 publication. However the Ref Des size, font, CAD layer and placement location are left up to the EE engineer and/or PCB designer.

 Every CAD library part should have 2 distinct reference designators, one for the silkscreen and one for the assembly drawing. Both designators, in every CAD library part, are normally located in the center of the component body. The silkscreen reference designator is relocated outside the component body after the part placement is completed and approved by the design review panel. If via fanout and trace routing cause part placement nudging then it’s best to wait until that process is completed or duplication of effort will come into play. Also, if via hole sizes exceed 0.4 mm and they are not tented then it’s best to avoid placing the silkscreen reference designators over the via hole, as the ink will drop into the hole making the reference designator indistinguishable and eliminate the purpose of having the reference designator to begin with. If you are using large via hole sizes it’s best to wait until the PCB design passes the engineering routing review panel. Via sizes smaller than 0.4mm can be tented (covered) with solder mask and the placement of silkscreen designators can go directly on the via.

 The silkscreen reference designator height sizes are –

  • 1.0 mm – Minimum
  • 1.5 mm – LP Calculator Default
  • 2.0 mm – Nominal
  • 2.5 mm – Maximum

 The reference designator text line width is normally 10% of the height for good clarity and to prevent the characters from bleeding or blobbing together. The 0.15 mm height “Default” is what the LP Calculator uses but users can change the global setting values to any value or measurement system.  

 The assembly reference designators are different in the fact that they never get relocated outside the component body outline. Assembly reference designator height sizes are –

  • 1.5 mm – Default
  • 1.2 mm – 0.5 mm for miniature components

 Here are some chip component assembly ref des height sizes that scale down according to the body size  –   

  • 4520 (EIA 1808) = 1.5 mm
  • 3216 (EIA 1206) = 1.2 mm
  • 2013 (EIA 0805) = 1.0 mm
  • 1608 (EIA 0603) = 0.7 mm
  • 1005 (EIA 0402) = 0.5 mm
  • 0603 (EIA 0201) – 0.5 mm  

 Note: All assembly body outlines are 1:1 scale of the physical component with the exception of all micro-miniature parts smaller than 1.6 mm length. Parts less than 1.6 mm length are EIA 0402 and 0201. These 2 parts assembly outline has to be enlarged so that the 0.5 mm assembly ref des fits cleanly inside it.  

Also, most land patterns (CAD library parts) have the Lands (Pads) put on the assembly layer. This is true for all parts that are large enough to accommodate both the component leads and the assembly ref des without interfering with each other. When the component leads interfere with the assembly ref des, the component leads on the assembly layer are removed from the padstack. This includes all chip components, crystals, molded body parts and grid array parts with bottom only leads.  

 

 

See Figure 1 for a sample of a typical silkscreen with the reference designators relocated outside the part.

 

Example of Silkscreen Reference Designators

Figure 1: Example of Silkscreen Reference Designators

 

 See Figure 2 for a sample of a typical assembly drawing with the reference designators inside the part, exactly where they were put when the CAD library parts were built. While the silkscreen reference designators must be relocated to an optimized location after part placement is completed, the assembly reference designators do not require any movement or cleanup. Also notice in Figure 2 that the large parts have lands (pads) built into the padstack and the small chip components do not have lands (pads) on the assembly layer. The LP Calculator allows the user to turn on/off Land on Assembly because some people do not want any component leads on the assembly drawing; rather they only want closed polygons with reference designators inside.

 

 

Example of Assembly Reference Designators

Figure 2: Example of Assembly Reference Designators

 

 

 

 

Table 1 contains list of the standard reference designators from the IPC-2612 standard for schematic symbol generation.

 

Standard Reference Designators for Schematic Symbols

Table 1: Standard Reference Designators for Schematic Symbols

 

 *These class letters would not appear in a parts list as they are part of a PCB and not an active electronic component.

 **Not a class letter, but commonly used to designate test points for maintenance purposes.

 Note: The above list is not exhaustive. See the standard list of class designation letters in ANSI Y32.2/IEEE Std 315, Section 22 and the Index.

 

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6 April, 2011
 The Quad Flat No-lead (QFN) component family, as seen in Figure 1, is one of the newest electronic packages to be introduced into PCB design. The QFN has pins on 4 edges of the bottom surface of the package. The QFN can have either a square or rectangle body as well as symmetric or asymmetric terminal patterns. The QFN with symmetric pins is only available in millimeter pin pitches of 0.8 mm, 0.65 mm, 0.5 mm and 0.4 mm as per the standard JEDEC MO-220I. The QFN was introduced to replace the gull wing lead Quad Flat Package (QFP) because the component leads are embedded in the plastic and cannot be bent during handling to insure consistent assembly attachment. The embedded lead form is also compatible with high speed design as the die to lead bonding and PCB contact is much shorter. And due to the high speed aspect, the component generates a lot of heat. This is why most QFN packages have a Thermal Tab that is via stitched to the GND planes for heat dissipation.
QFN Component Package Pictures

Figure 1: QFN Component Package Pictures

 

 The Quad Flat No-lead (QFN) package is a CSP (plastic encapsulated package) with a copper lead frame substrate. The QFN is a leadless package where electrical contact to the PCB is made by soldering the leads on the bottom surface of the package to the PCB, instead of the conventional formed perimeter gull wing leads. The design of the QFN package has enhanced electrical performance that enables the standard 2 GHz frequency to be increased up to 10 GHz with some design considerations.

 The QFN leads are coated with a finish that provides environmental protection and maintains solderability. See Figure 2 for a cross-section internal view of the QFN package construction.

Figure 2 - QFN Construction

Figure 2 - QFN Construction

 

 The symmetric termination leads can be either rounded ends or rectangle ends. See Figure 3 for the 2 different lead styles.

Figure 3 - QFN Lead Shapes

Figure 3 - QFN Lead Shapes

 

 The QFN uses the “Flat No-lead Edge” component lead style. See Figure 4 for a side view of the component lead. The component lead terminals are embedded in the plastic body and sticks out 0.05 mm on the bottom and wraps up the component body side by 0.2 mm.

Figure 4 - Flat No-lead Edge Terminal Type

Figure 4 - Flat No-lead Edge Terminal Type

 

 There are 2 types of QFN component package styles, Standard & Flanged Type. The Standard package is commonly known as the “Saw Cut” package and the Flanged Type is known as “Molded Body”. See Figure 5 for the 2 types of component package styles.

Figure 5 - QFN Component Package Styles

Figure 5 - QFN Component Package Styles

 

  The Thermal Tab shape can have a chamfered corner closest to the location of Pin 1. The “Land Size” is identical to the maximum tolerance of the thermal tab size. The solder mask size is 1:1 scale of the land size. The thermal tab can also have corner radius on the other corners. See Figure 6 for an example of a thermal tab with chamfered and rounded corners.

Figure 5 - Thermal Pad with Chamfer & Rounded Corners

Figure 6 - Thermal Pad with Chamfer & Rounded Corners

 

 The Thermal Pad Paste Mask size needs to be between 40% and 60% of the land size and is broken up into a checkerboard pattern. The IPC LP Calculator is set to 40% paste mask reduction by default, but the reduction percentage is user definable. The checkerboard pattern does not start until the thermal pad size exceeds 4.5 mm because the minimum paste mask aperture opening for thermal pad paste mask is about 1 mm square. See Figure 6 for examples of thermal tab paste mask with a 40% reduction. The picture of the left has a thermal pad size of 4 mm and a single paste mask of 2.5 mm. The picture on the right has a thermal pad size of 4.5 mm and a matrix of 4 squares of paste mask of 1.4 mm.  

Figure 6 - Thermal Pad Paste Mask with 40% Reduction

Figure 7 - Thermal Pad Paste Mask with 40% Reduction

 

 If there was no reduction of paste mask, the physical component would float on top of 0.15 mm (the thickness of the paste mask stencil) of solder. During the reflow process users have observed that the liquidus solder lifts the device and creates a pivot point near the center of the Die Attach Pad (DAP). As the solder cools the device tends to tilt toward one side, often creating shorts in one area and opens in another. By reducing the paste mask stencil to 40% of the land size, the component will settle down evenly to allow for an adequate solder joints on the end termination leads. See Figure 8 for an example of excessive solder and reduced solder on the Die Attach Pad.

Figure 7 - Excessive Thermal Pad Paste Mask

Figure 8 - Excessive Thermal Pad Paste Mask

 

The primary purpose of the thermal tab is to conduct heat away from the die during operation. The best way to achieve this goal is to add stitch vias attached to the GND plane. The via hole size recommendation is 0.25 mm and should be plated, plugged and surface finished to prevent liquidus solder from entering the holes. By no means attempt to Tent the vias with dry film solder mask because this will reduce the solder volume area on the pad. The via padstack is 0.5 mm pad, 0.7 mm plane clearance, 0.25 mm hole and no thermal relief. Placing the vias on a 1 mm grid allows for two 0.1 mm trace/space routing technology on all inner layers and opposite side. In order to achieve the 1 mm via snap grid, the QFN must be placed on a 0.5 mm placement grid. See Figure 9 for an example of a via matrix in a thermal pad.

Figure 8 - QFN Thermal Pad Via Stitching

Figure 9 - QFN Thermal Pad Via Stitching

 

 Some QFN packages come in a variety of lead sizes and multiple thermal tabs. See Figures 10 – 12 for some unique QFN variations.

  Figure 10 has multiple lead lengths and “Deleted Pins”.

Figure 9 - QFN with Different Lead Lengths

Figure 10 - QFN with Different Lead Lengths

 

 Figure 11 QFN has multiple thermal tabs and “Hidden Pins”. Some QFN packages have 3 – 5 thermal tabs with various shapes and sizes.

Figure 10 - QFN with Multiple Thermal Tabs & Deleted Pins

Figure 11 - QFN with Multiple Thermal Tabs & Deleted Pins

 

 Figure 12 QFN has deleted pins and Pin 1 is lower left corner and pin order is Counterclockwise instead of the traditional Clockwise pin order.

Figure 11 - QFN with Deleted Pins & Pin 1 in Lower Left w-Counterclockwise

Figure 12 - QFN with Deleted Pins & Pin 1 in Lower Left w-Counterclockwise pin order numbering

 

 Figure 13 is a detailed picture of all the aspects that go into the construction of a QFN land pattern library part.

Figure 13 - QFN Land Pattern Details

Figure 13 - QFN Land Pattern Details

 

 The via fanout for the QFN component family is really easy for all pin pitches that are on even 0.1 mm increments. These are 0.8 mm, 0.5 mm and 0.4 mm pin pitch. All SMT components with a 0.65 mm pin pitch are not 100% compatible with the 0.05 mm universal grid system. It would be superior if the component manufacturer’s never created any pin pitch in 0.05 mm increments. It would be much better for the PCB designer if all pin pitches were in 0.1 mm increments. In this case, 0.65 mm pin pitch would be superior if it was 0.6 mm. Let’s take a look at some of the via fanout solutions to optimize routing channels. All of the routing solutions use the identical via size (0.5 mm pad, 0.7 mm anti-pad and 0.25 mm hole) and trace/space (0.1 mm) technology that is located in Figure 9.

 Figure 14 is a 0.8 mm QFN sample via fanout and routing channel solution. This routing solution provides for 1 trace between vias. The red traces are the opposite side and the green traces are the inner layer. The yellow annular ring on the via is the plane clearance. A 0.1 mm grid was used for the via fanout and trace snap grid.

Figure 14 - 0.8 mm Pitch QFN Via Fanout & Routing Solution

Figure 14 - 0.8 mm Pitch QFN Via Fanout & Routing Solution

 

 Figure 15 is a 0.65 mm QFN via fanout and routing channel solution. The 0.65 mm pitch fanout must use a 0.05 mm grid and 3 traces between vias. When there is an even number of pins on each side, you have to use a 0.025 mm grid system because the components are always placed on a 0.1 mm grid system and from the center of the 0.65 mm QFN to the center of the pad is 0.65 divided by 2 = 0.325 mm. This is why 0.65 mm pitch components are not optimized for the universal 0.05mm grid system.

Figure 15 - 0.65 mm Pitch QFN Via Fanout & Routing Solution

Figure 15 - 0.65 mm Pitch QFN Via Fanout & Routing Solution

 

  Figure 16 is a 0.5 mm QFN via fanout and routing channel solution. This routing solution provides for 2 traces between vias. A 0.1 mm grid was used for the via fanout and trace snap grid.

Figure 16 - 0.5 mm Pitch QFN Via Fanout & Routing Solution

Figure 16 - 0.5 mm Pitch QFN Via Fanout & Routing Solution

 

 Figure 17 is a 0.4 mm QFN via fanout and routing channel solution. This routing solution provides for 1 trace between vias. A 0.1 mm grid was used for the via fanout and trace snap grid.

Figure 17 - 0.4 mm Pitch QFN Via Fanout & Routing Solution

Figure 17 - 0.4 mm Pitch QFN Via Fanout & Routing Solution

 

 All the graphic pictures of land patterns in this post were created by the LP Wizard. Download a 10-day evaluation license for LP Wizard and see how many different “high quality” QFN library parts you can build – www.mentor.com/go/lpwizard   

 

 

 

31 March, 2011

Here are some tips about Metric Speak that all PCB designers need to know. “Metric” is not a unit of measure. Metric is a term that describes a measurement system. You use either millimeters or microns for your PCB design units. The proper terminology to describe your working units when using the metric measurement system is millimeters or microns, not metric. Example: When doing PCB layout in Inches or Mils you never refer to working in “Imperial Units”.

Millimeters allow finer (and greater) granularity in the PCB design grid system to optimize board real-estate, part placement, via fanout and routing trace/space features and snap grids. This will be very important in the future of PCB RF Micro-technology. PCB impedance measurements are more accurate in Micron units than “Ounces of Copper” and Mil core/Prepreg dielectric. Use Micron Units to achieve the highest level of accuracy for impedance calculations.

Unfortunately, PCB manufacturers are directly responsible for holding back the progress of the transition to metrication of our industry. When the PCB fabrication companies transitions to the metric system, the entire electronics industry will achieve the peak of “electronic product development automation”. Until then, we’ll plod along using dual units in the land of chaos.

Here is an example of the chaos in the Chip Component family. All Chip names refer to their body length and width. When EIAJ introduced the standard Chip and Molded body component dimensions, only millimeter units were used. A 3216 was 3.2 mm long and 1.6 mm wide. It was very simple. When the data was passed on to EIA in America, they changed all the chip names from millimeters to Inches and a 3216 was renamed 1206 or 0.125” length and 0.062” width (just drop the 3rd place number). Today most component manufacturers dimension all there component packages in millimeters see Table 1 that illustrates Metric vs. Imperial names. You can easily see the confusion in the dual measurement system.

Table 1 - Chip Component Names

Table 1 - Chip Component Names

Let’s start the transition process. 99% of all PCB layouts use vias. See Table 2 for an Inch to Millimeter chart for common via sizes starting with a 0.15 mm hole and growing in 0.05 mm increments. I’ll provide the entire padstack conversion. I intentionally did not add thermal relief data because vias should have a direct plane connection (no thermal relief is necessary). When transitioning from Imperial units to Metric units, always round-off the millimeter values in 0.05mm increments for normal resolution. If you’re working on extremely dense hand held device technology, round-off to the nearest 0.01 mm. For PCB design, there is no reason to go more than 2 places to the right of the decimal point for the present. 0.01 mm = 0.0003937”

Table 2 - Via Padstack Technology

Table 2 - Via Padstack Technology

 Table 3 illustrates 4 common inch based part placement grids and their millimeter equivalent.  The common rule in placing parts in millimeters is to always stay one place to the right of the decimal or 0.1 mm increments.

Table 3 - Component Placement

Table 3 - Component Placement

 Table 4 provides all the common trace/space technology and routing snap grids. The common rule when working in millimeters is to always use a 0.05 mm routing grid. Most component lead pin pitches are 0.05 mm increments and IPC-7351B land (pad) sizes and snap grids are in 0.05 mm increments. This totally optimizes trace routing and eliminates wasted PCB real-estate. Everything fits together tighter than Lego building blocks.  Notice that in the inch units, a gridless shape-based option is used, but in millimeters all objects can easily snap to a grid and still achieve maximum density solutions. I provide 3 various route snap grid solutions for the various trace/space rules.

Note: Inch based routing grids are evenly divisible into 0.100” while millimeter based routing grids are evenly divisible into 1 mm.

Table 4 - Trace Widths & Optimum Routing Grids

Table 4 - Trace Widths & Optimum Routing Grids

 Table 5 provides the PCB material equivalents. Note that the various columns are not related to each other. Each column describes a specific PCB feature. In the first column “Board Thickness” is common PCB finished material thicknesses and the metric equivalent rounded off to the nearest 0.1 mm. The second column is copper weight in ounces and their micron equivalent. Using microns to describe copper thickness is better than using weight. The third and forth columns go together. Column 3 defines the type of hole and column 4 provides the PCB fabrication tolerance for each different hole type in the chart.

Table 5 - PC Board Criteria

Table 5 - PC Board Criteria

 Table 6 is common plated through-hole padstacks for component leads and their inch to millimeter conversion. All hole, pad and plane clearance values are in 0.05mm increments. The Solder Mask is the same value as the outer layer pads. This padstack information was taken from the proportional padstack table and you can download it here under “Appnote 10836: Proportional Through-hole Padstacks” – http://www.mentor.com/products/pcb-system-design/library-tools/lp-wizard/import-docs

Note: this downloadable chart only contains millimeter values and not the inch equivalents in Table 6.

Table 6 - Common Plated Through-hole Padstacks

Table 6 - Common Plated Through-hole Padstacks

 Table 7 is common non-plated through-hole padstacks and their inch to millimeter conversion. All hole, pad and plane clearance values are in 0.05mm increments. The Solder Mask is the same value as the hole size to allow the PCB manufacturer to oversize it per their specific fabrication tolerances. Notice that the pad size for every padstack is 1.00 mm. Because the holes are not plated, the hole size is typically larger than the hole size. Also, there is no reason to have multiple pad sizes when the pad is eventually drilled away. The only reason for having a pad in a non-plated padstack is display a marker as a guide for the hole location. The PCB manufacturer does not need the pad in the padstack, but sometimes when there is no pad (but there is a drill hole) the manufacturer might question if the hole is valid. Of course there is no thermal relief required in non-plated hole padstacks.

Table 7 - Common Non-Plated Through-hole Padstacks

Table 7 - Common Non-Plated Through-hole Padstacks

I want to note that the LP Calculator automatically performs all of these through-hole padstack calculations for you and provides 5 different options –

  1. Proportional Environment
  2. IPC-7251 Most Environment
  3. IPC-7251 Nominal Environment
  4. IPC-7251 Least Environment
  5. User Defined Environment Rules 

You can get a free LP Calculator by signing up for a 10-day evaluation of LP Wizard here – http://www.mentor.com/products/pcb-system-design/library-tools/lp-wizard/lp-wizard-eval

After the LP Wizard 10-day evaluation is over, the LP Wizard program will run in “Demo Mode” as LP Calculator.

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23 March, 2011

If the French would have won the French & Indian War against the British (the 7 Year War from 1754 to 1763) Imperial Units or the English measurement system would not exist in society today. Even the British transitioned to the metric measurement system 46 years ago. America is the last stronghold for the Imperial measurement system and how much longer will it take for the world to become united under a single measurement system. This is what world standards and space age technology acceleration will require to fully automate all PCB processes.

One of the greatest secrets to PCB design perfection today in 2011 is the use of the metric unit system. From 1974 – 1991 we used Inch units for PCB layout. From 1991 – 2001 we used Mil units. From 2001 – 2011 we used millimeter units. I have to say that when we made the transition from Mils to millimeters our productivity levels slipped a bit during the learning curve. But after 5 or 6 PCB layouts our productivity was back to normal. After about 15 PCB layouts our productivity levels surpassed all previous results. If I was forced to go back to the Mil measurement system, my productivity levels would reverse backwards. There is no way in the world that anyone in 2011 using Mil units can outperform the same talent using Millimeter units because most component pin pitches are on a millimeter grid system (like the 1 mm pitch BGA) and metric units are vastly superior to work within the PCB design space because all the numbers are evenly divisible by 10 and there is no use for calculators for mathematical calculations. There is no one that I know of that has successfully transitioned to the metric unit system for PCB layout that wants to go back to the Imperial unit system. That statement alone tells it all.

As a matter of fact, there would not be Imperial units in the world today if the United States government (congress) fulfilled the commitment that they signed at the Treaty of the Meter back in 1875. I hear it all the time from corporations who will not convert – “We’re American and we have our own measurement system. We are not part of the European Union or Russia or Japan. We’re proud to be Americans and we believe in our way of life and the system and values that we use”.  Well, let me shine a little light on all those proud Americans who obviously do not know the historical facts. So before I go into PCB design details of why metric units are superior, I need to explain the historical background to set the stage.

Most Americans think that our involvement with metric measurement is relatively new. In fact, the United States has been increasing its use of metric units for many years, and the pace has accelerated in the past four decades. In the early 1800′s, under the presidency of Thomas Jefferson, the U.S. Coast and Geodetic Survey (the government’s surveying and map-making agency) used meter and kilogram standards brought from France. Abraham Lincoln was a strong proponent of the metric unit system and in 1866 (just 1 year after his assassination), Congress authorized the use of the metric system in America and supplied every state with a set of standard metric weights and measures.

 In 1875, the United States solidified its commitment to the development of the internationally recognized metric system by becoming one of the original seventeen signatory nations to the Treaty of the Meter. The signing of this international agreement concluded five years of meetings in which the metric system was reformulated, refining the accuracy of its standards. The Treaty of the Meter, also known as the “Metric Convention” established the International Bureau of Weights and Measures (BIPM) in Sèvres, France, to provide standards of measurement for worldwide use.

 In 1893, metric standards, developed through international cooperation under the auspices of BIPM, were adopted as the fundamental standards for length and mass in the United States. Our customary measurements — the foot, pound, quart, etc. — have been defined in relation to the meter and the kilogram ever since. The General Conference of Weights and Measures, the governing body that has overall responsibility for the metric system, and which is made up of the signatory nations to the Treaty of the Meter, approved an updated version of the metric system in 1960. This modern system is called Le Système International d’Unités or the International System of Units, abbreviated SI.

The United Kingdom began a transition to the metric system in 1965 to more fully mesh its business and trade practices with those of the European Common Market. The conversion of the United Kingdom and the Commonwealth nations to SI created a new sense of urgency regarding the use of metric units in the United States.

In 1968, Congress authorized a three-year study of systems of measurement in the U.S., with particular emphasis on the feasibility of adopting SI. The detailed U.S. Metric Study was conducted by the Department of Commerce. A 45-member advisory panel consulted with and took testimony from hundreds of consumers, business organizations, labor groups, manufacturers, and state and local officials.

The final report of the study, “A Metric America: A Decision Whose Time Has Come” concluded that the U.S. would eventually join the rest of the world in the use of the metric system of measurement. The study found that measurement in the United States was already based on metric units in many areas and that it was becoming more so every day. The majority of study participants believed that conversion to the metric system was in the best interests of the Nation, particularly in view of the importance of foreign trade and the increasing influence of technology in American life.

The study recommended that the United States implement a carefully planned transition to predominant use of the metric system over a ten-year period. Note: In 1975, the Australian continent also implemented its metric conversion act and successfully transitioned.  The United States Congress passed the Metric Conversion Act of 1975 “to coordinate and plan the increasing use of the metric system in the United States.” The Act, however, did not require a ten-year conversion period. A process of voluntary conversion was initiated, and the U.S. Metric Board was established. The Board was charged with “devising and carrying out a broad program of planning, coordination, and public education, consistent with other national policy and interests, with the aim of implementing the policy set forth in this Act.” The efforts of the Metric Board were largely ignored by the American public, and, in 1981, the Board reported to Congress that it lacked the clear Congressional mandate necessary to bring about national conversion. Due to this apparent ineffectiveness, and in an effort to reduce Federal spending, the Metric Board was disestablished in the fall of 1982.

The Board’s demise increased doubts about the United States’ commitment to metrication. Public and private sector metric transition slowed at the same time that the very reasons for the United States to adopt the metric system — the increasing competitiveness of other nations and the demands of global marketplaces — made completing the conversion even more important.

Congress, recognizing the necessity of the United States’ conformance with international standards for trade, included new encouragement for U.S. industrial metrication in the Omnibus Trade and Competitiveness Act of 1988. This legislation amended the Metric Conversion Act of 1975 and designates the metric system as the preferred system of weights and measures for United States trade and commerce.” The legislation states that the Federal Government has a responsibility to assist industry, especially small business, as it voluntarily converts to the metric system of measurement.

Federal agencies were required by this legislation, with certain exceptions, to use the metric system in their procurement, grants and other business-related activities by the end of 1992. While not mandating metric use in the private sector, the Federal Government has sought to serve as a catalyst in the metric conversion of the country’s trade, industry, and commerce.

The current effort toward national metrication is based on the conclusion that industrial and commercial productivity, mathematics and science education, and the competitiveness of American products and services in world markets, will be enhanced by completing the change to the metric system of units. Failure to complete the change will increasingly handicap the Nation’s industry and economy.

There is one thing that I would like to clarify to the reader that I’m not proposing that the American “way of life” change in our sports (football, baseball, golf, etc.) or cooking units in our kitchens, but rather our “industry” must change to increase our competitiveness with the rest of the world. However, America has an impact on other counties weights and measurement systems. The EU Metric Directive (80/181/EEC), that was scheduled to go into effect on January 1, 2010, has been modified to allow the continuation of both supplemental (U.S. customary, inch-pound) and metric units for consumer goods sold in the EU. The rule was published on May 7, 2009 in the Official Journal of the European Union.

The modified Directive instructs the European Commission to produce a report to the Parliament and Council regarding the smooth functioning of the internal market and international acceptance of SI units by December 31, 2019, including proposals where appropriate. Demonstrated progress will be important to achieve long-term acceptance of supplemental units in the EU. Modifying the U.S. Fair Package and Labeling Act (FPLA) to permit metric labeling is an example where greater international marketplace acceptance of SI units can be achieved. 

Next week I will present Imperial to Metric conversion charts as they apply to the PCB design industry. I will also post a short message on the proper terminology that I refer to as “Metric Etiquette”.

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18 March, 2011
Mounting holes are on every PCB design, but there is very little documentation about this subject matter. A Google or Wikipedia search on “Mounting Holes” renders no solutions to the PCB designer. Another issue that interferes with standardization is Imperial Unit ASNI hardware and ISO Metric hardware. So we’re going to have to explain both unit systems for clarity. But first let’s start with the basic fundamentals that both unit systems have in common.

Mounting hardware normally consists of these 4 items (See Figure 1) –

  1. Phillips Head Screw
  2. Hex Nut
  3. Flat Washer
  4. Lock Washer
Figure 1 - MTG Hardware

Figure 1 - MTG Hardware

There are 4 types of mounting holes –

  1. Supported – Plated through with annular ring
  2. Supported – Plated through with annular ring with vias
  3. Unsupported – Non-plated and with copper pads
  4. Unsupported – Non-plated and with no copper pads

     

     

 

The supported mounting hole usually gets tied to the GND plane without a Thermal Relief (a direct connection is best) and the supported hole w/vias gets both the main hole and the vias tied to the GND plane. Due to the fact that mounting hardware never gets soldered to the PCB, there is no reason for a Thermal Relief pattern and you connect all holes (including vias) directly to the plane. The unsupported (non-plated) hole has no connection to a GND plane layer and they require an outer layer keep-out defined that compensates for the hardware tolerances. See figure 2 for an illustration of the slop tolerance of a flat washer and the necessary copper keep-out sizing.

Figure 2 - Keepout

Figure 2 - Keepout

 There are two primary reasons for adding vias to the supported mounting hole. The first was to insure that if the screw threads stripped the copper plating from the main hole that the vias would still provide adequate ground connections. The second reason was for additional support to prevent the PCB from crushing when too much torque was used to tighten the nut. The average via hole size for mounting holes is 0.5 mm. See Figure 3 for a supported mounting hole with vias.

Figure 3 - Mounting Hole with Vias

Figure 3 - Mounting Hole w/Vias

See Table 1 for the most popular PCB hardware sizes for metric unit technology.

Table 1 - ISO (metric) Hardware

Table 1 - ISO (metric) Hardware

In Tables 2 and 4 there are 3 different padstack configurations for each metric screw size for land (pad) size calculations.

  1. No Washer – Pan Head Clearance
  2. Flat Washer

The land (pad) diameter is equal to the hardware diameter and a placement courtyard is added to compensate for the slop tolerance indicated in Figure 2.

Note: These Land (pad) and Placement Courtyard padstack values are in the “Least” material values. You can add 0.25 mm for “Nominal” or 0.5 mm for “Most” Land (pad) and Placement Courtyard environments. The hole sizes are for a loose fit.

Table 2 - ISO Loose Fit Mounting

Table 2 - ISO Loose Fit Mounting

Table 3 - ISO Tight Fit Mounting

Table 3 - ISO Tight Fit Mounting

See Table 3 for the most popular PCB hardware sizes for ANSI standards.

Table 4 - ANSI Hardware

Table 4 - ANSI Hardware

 

 

Table 5 - ANSI Loose Fit Mounting

Table 5 - ANSI Loose Fit Mounting

Table 6 - ANSI Tight Fit Mounting

Table 6 - ANSI Tight Fit Mounting

The “Loose Fit” mounting holes are normally used on large boards greater than 100 mm (4”) and the “Tight Fit” mounting holes are commonly used for smaller board sizes.

There are some differences in hardware manufacturer’s feature sizes, so make sure that the hardware you use is adequately covered with the correct pad size and/or keep-out.

There are 3-Tiers for the Mounting Hole family, but the only difference is the “Placement Courtyard Excess”:

  • Least – 0.1 mm annular
  • Nominal – 0.25 mm annular
  • Most – 0.5 mm annular

 

Note: All numeric values in the Tables are in millimeters

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28 January, 2011

The 3-Tier PCB library concept was originally created by IEC (International Electromechanical Commission) in 1999 and introduced to IPC in 2000. The concept had to be created as a solution for high density packaging for hand held devices to ruggedized military applications and everything in-between. The IPC-7351 and the IEC 61188-5-1 SMT land pattern standards for were specifically created to introduce this new concept in 2005. Before 2005, the IPC-SM-782 was a 1-Tier land pattern standard developed in 1985 and released in March 1987. The pad size of the IPC-SM-782 land pattern, compared to the new IPC-7351, fell in-between the Most and the Nominal environments.

The IPC-7251 land pattern standard for through-hole components is currently being developed. It also has a 3-Tier environment concept that apply to the hole sizes and annular rings.

Three land pattern geometry variations are supplied for each of the device families; Maximum Land Protrusion (Density Level A), Nominal Land Protrusion (Density Level B) and Least Land Protrusion (Density Level C). Here are the definitions for the 3-Tier (or 3 Level) PCB library system for both through-hole and SMD technology.

Density Level A: Maximum Land/Lead to Hole Relationship – The ‘maximum’ land pattern conditions have been developed to accommodate the most robust producability of the solder application method. The “Level A” land patterns are usually associated with low component density product applications. “Level A” land patterns accommodate wave or flow solder of leadless chip devices and leaded gull wing devices. The geometry furnished for these devices, as well as inward and “J”-formed lead contact device families, may provide a wider process window for reflow solder processes as well. “Level A” is used for ruggedized military applications and medical devices.

Density Level B: Nominal Land/Lead to Hole Relationship – Products with a moderate level of component density may consider adapting the ‘median’ land pattern geometry. The median land patterns furnished for all device families will provide a robust solder attachment condition for most soldering processes and should provide a condition suitable for wave, dip, drag or reflow soldering. “Level B” is primarily used for desktop applications, controlled environment devices and many consumer electronic products.

Density Level C: Least Land/Lead to Hole Relationship – High component density typical of portable and hand-held product applications may consider the ‘minimum’ land pattern geometry variation. Selection of the minimum land pattern geometry may not be suitable for all product use categories.
The use of classes of performance 1, 2, and 3 is combined with that of component density levels A, B, and C in explaining the condition of an electronic assembly. As an example, combining the description as Levels 1A or 3B or 2C, would indicate the different combinations of performance and component density to aid in understanding the environment and the manufacturing requirements of a particular assembly.

See Figure 1 for an example of the 3 different land pattern levels for chip components.

Figure 1 - 3-Tier for Chip Components

Figure 1 - 3-Tier for Chip Components

Let’s take a look at the IPC-7351B tables for the Chip Component family. Table 1 applies to all chip components equal to or larger than a 1608 (EIA 0603). The chip component family is referred to as “Rectangular or Square-End components for resistors, capacitors and inductors.

Table 1 - Chip Components Equal or Greater Than 1608 (EIA 0603)

Table 1 - Chip Components Equal or Greater Than 1608 (EIA 0603)

Notice in Table 1 that the Side Goal value for the Least Environment is -0.05 mm. This does not mean that the land will be smaller than the component lead. There are several other factors that go into the land size calculation like Fabrication and Assembly tolerances and Component Lead tolerance. So whenever you see a negative value in a solder joint goal table, it is only adjusting the land size to neutralize the fabrication tolerance.

Table 2 is for “Rectangular or Square-End components for resistors, capacitors and inductors smaller than a 1608 (EIA 0603). Notice that the “Toe” goal and placement courtyard excess are affected the most. Also, the round-off factor is in 0.02 mm increments.

Table 2 - Chip Components Less Than 1608 (EIA 0603)

Table 2 - Chip Components Less Than 1608 (EIA 0603)

See Figure 2 for an example of the 3 different land pattern levels for small outline package (SOP) components.

Figure 2 - 3-Tier for SOP Components

Figure 2 - 3-Tier for SOP Components

Let’s take a look at the IPC-7351B tables for the Gull Wing and Flat Ribbon L lead Component family. This component family includes Small Outline Diodes (SOD), Small Outline Packages (SOP) Small Outline Transistors (SOT) and Quad Flat Packages (QFP). Table 3 applies to all gull wing components with a pin pitch greater than 0.625 mm.

Table 3 - Gull Wing with Pin Pitch Greater than 0.625 mm

Table 3 - Gull Wing with Pin Pitch Greater than 0.625 mm

Table 4 is for Gull Wing and Flat Ribbon L lead Component family with a pin pitch less than 0.625 mm.

Table 4 - Gull Wing with Pin Pitch Less than 0.625 mm

Table 4 - Gull Wing with Pin Pitch Less than 0.625 mm

Notice in Table 4 that the only difference is in the “Side” solder joint goal. Also, Table 4 only represents the Small Outline Package (SOP) and the Quad Flat Package (QFP) component families.

There is a different IPC-7351B table for every component family lead type. The only component family group that only has one tier for the land size is the “Grid Array” components. Ball Grid Array (BGA), Land Grid Array (LGA), Column Grid Array (CGA and Pillar Column Grid Array (PCGA). This component family group has various placement courtyard excess sizes that are dependent on the lead size for the sole purpose of rework equipment access.

The “Bottom Only” leaded component families do not have a Toe, Heel or Side solder joint goal. Their solder joint goal is referred to as a “Periphery” and the land area is the same value on all sides. This includes “D-Shaped” leads for Pull-back lead QFN, Square and Rectangular leads for LGA’s and Round leads for BGA, CGA and LGA.

The SMT Land Pattern Naming convention has an M, N or L at the end of the name and the PTH Land Pattern Naming convention has an A, B or C at the end of the name to identify the Density Level with the exception of the Grid Array component families. The main reason why SMD land pattern names use L, N & M is because they can be used in all “Producibility Levels” -

  • Level A - General Design Producibility (Preferred)
  • Level B - General Design Producibility (Standard)
  • Level C - General Design Producibility (Reduced)

However, the PTH land pattern names use A, B & C because they are closely linked to the Producibility Levels for manufacturability due to drill hole tolerances and annular ring allowance for both outer and inner layers. Note: The IPC-7251 standard for through-hole technology is still in development and should be released later this year (2011).

There is also a “Proportional” environment for PTH libraries that uses a combination of IPC Level A, B and C depending on the hole size. Small holes use Level C, medium hole sizes use Level B and larger hole sizes use Level C or greater annular ring. Proportional meets IPC levels for smaller hole sizes and beats IPC levels for larger hole sizes.

21 January, 2011
0.5 mm Pitch BGA Routing Solution

There is a reasonable solution for via fanout and a routing solution for the 0.5 mm pitch BGA but we need to think outside the box. The board thickness is an important factor because it affects the hole plating aspect ratio. If you use a 1 mm PCB thickness and want to achieve a 7:1 aspect ratio (this is common among all manufacturers) then the smallest hole size is 0.15 mm (6 mil). There are manufacturer’s that can hard drill a 0.15 mm (6 mil) hole through a 1 mm PCB. There are manufacturers that claim they can easily handle 10:1 aspect ratios. This means that they can drill 0.15 mm (6 mil) holes through 1.57 mm (0.062”) thick PCB material and plate the hole without problems. Drilling all the way through the PCB is important because sequential lamination is an expensive process.

For all via-in-land technology, a thermal relief on the voltage and ground plane connections must be used to prevent cold solder joints. A direct via-in-land connection to the plane will dissipate the heat required to melt the solder around the BGA ball and this will result in a cold or cracked solder joint. The exception to this rule is if the via only contacts a single plane with ½ OZ. copper or less.

If traces are routed between pins of the 0.5 pitch BGA land, the solder mask must be a 1:1 scale to create a “solder mask defined” BGA land. In this way, the traces between the lands will be protected from exposure and possible short circuiting.

The 0.5 mm pitch BGA via-in-land drill hole through the PCB is leading edge technology. When laser drills are capable of producing 0.125 hole sizes entirely through the board and PCB manufacturers can accurately fill the holes with conductive metal epoxy, this technology will become mainstream.

Micro-via technology is the mainstream solution for 0.5 pitch BGA components when a 0.1 – 0.15 laser hole is drilled one, two or three layers deep. This involves sequential lamination but before we get to that subject let’s discuss the via fanout process. Using via-in-land technology, we must offset the drill holes to create adequate routing channels. This is the only routing solution that I know of to maintain manufacturability. See Figure 1 for a via fanout solution for the outer layer. Notice that you will have to add additional copper land for via annular ring.

Figure 1 – 0.5 mm Pitch BGA Via-in-Land

Figure 1 – 0.5 mm Pitch BGA Offset Via-in-Land

The vias are 0.05 mm offset from the land center and grouped together.

See Figure 2 for a via fanout solution for the inner layers. The most important feature here is the 0.1 mm (4 mil) trace width & 0.1 mm space between Trace to Via and Via to Via.

Figure 2 – 0.5 mm Pitch BGA fanout Inner Layers

Figure 2 – 0.5 mm Pitch BGA fanout Inner Layers

 

 

 

Depending on how many rows and columns in the BGA will determine the number of routing layers required.  

Sequential lamination process requires the inner layers to be laminated, drilled and plated in Phase 1 and then add 2 additional outer layers and back through lamination, drill and plate in Phase 2. Then add 2 additional outer layers and back through lamination, drill and plate in Phase 3. See Figure 3 for the various phases of sequential lamination.

Figure 3 - Sequential Lamination

Figure 3 - Sequential Lamination

Let me try to explain why sequential lamination is so expensive and why most people avoid it unless they absolutely need it for high volume production. The PCB inner layer manufacturing goes through the entire fabrication process in Phase 1. Then the first HDI layers that are added to the PCB have to go through the entire fabrication process over again. This basically doubles the cost in Phase 2. Then the second HDI layers that are added to the PCB have to go through the entire fabrication process over again. This basically triples the cost in Phase 3 and the manufacturer’s say that they are basically building the same PC board 3 times.

There are 2 methods of via drilling for sequential lamination. Staggered vias and stacked vias. See Figure 4 for the staggered micro-via process.

Figure 4 – Staggered Micro-vias

Figure 4 – Staggered Micro-vias

Notice in the Staggered Micro-via picture that the via plugging color is green. This could be an epoxy fill because the vias are staggered and there is no manufacturing stress. Discuss staggered vs: stacked vias with your manufacturer to find out if one technique is less expensive than the other. See Figure 5 for the stacked micro-via process.

Figure 5 – Stacked Micro-vias

Figure 5 – Stacked Micro-vias

The Stacked Micro-vias must be filled with conductive metal to prevent the outer laser drill from damaging the inner layer hole. See Figure 6.

Figure 6 – Stacked Micro-via Conductive Fill

Figure 6 – Stacked Micro-via Conductive Fill

The latest generation technology developed by Dow Electronic Materials for advanced via fill plating, MICROFILL™ EVF Via Fill provides enhanced via filling, with simultaneous through-hole plating, at surface thicknesses unattainable. Formulated to operate in existing equipment over a broad range of operating conditions, MICROFILL™ EVF Copper Via Fill is suitable for HDI applications. It is proved by sufficient experience that MICROFILL™ EVF could help to reduce 20% plating thickness and helps to improve varied plating defects. See Figure 7 for stacked micro-via conductive fill techniques. To read more on this topic see:  http://www.rohmhaas.com/wcm/information/em/interconnect/microfill/index.page

Figure 7 – Stacked Micro-via Conductive Fill

Figure 7 – Stacked Micro-via Conductive Fill

Notice the lower right image in Figure 7 that shows a 0.15 mm via hole going all the way through a 1 mm thick PCB with 20um (0.000787”) or ½ OZ. copper plating thickness. The normal hole plating thickness on an average PCB is 25um (0.001″) or 1 mil.

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