DVCon: Wally Rhine’s Keynote

“50 years from today, every man, woman and child in India will be required to run an HDL simulator”.

As Wally Rhines explained in his DVCon keynote today, this is the absurd conclusion you reach if you extrapolate data showing that between 2007 and 2010 the average verification team size grew by a whopping 58%. Indeed the conclusion is absurd, but the image is strikingly powerful.  Verification complexity grows at a faster pace than we can keep up with, and we’d better do something about it.

 

Reflecting on what happened in the last few years, Rhines observed that the focus has been to increase the “volume” of verification. This has been achieved by the adoption of verification techniques such as assertions, code coverage, functional coverage or emulation. The use of assertions has grown from 37% in 2007 to 69% in 2010. Similarly, functional coverage grew from 40% to 72% over the same period of time. 

However, as design complexity also increased during that time, this aggressive adoption of advanced functional verification techniques barely helped contain the problems. 66% of projects are still behind schedule. 45% of chips require two silicon passes and 25% require more than two passes.

Citing more survey results, Rhines highlighted that 52% of chip failures were still due to functional problems. The issue as already been discussed on this blog: RTL design is where most errors are being introduced. But can it be a surprise given that RTL design is mostly a manual effort?

Continuing, Wally Rhines explained that the industry needs to look beyond the mere “volume” of verification, and now needs to improve and emphasize the “velocity” of verification. In other words, accelerating verification closure with techniques such as intelligent testbench automation, transaction-based hardware acceleration and by adopting ESL and higher levels of abstraction.

So for the sake of India’s population, it is time we change the direction of verification and shift from adding cycles of verification to maximizing the verification per cycle.

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