SystemC and UVM, one step closer

This morning Intel’s Eric Lish, OSCI chair, kicked-off the North American SystemC User Group collocated at DVCon. In his presentation, Eric covered the evolution of SystemC as well as recent and upcoming milestones. It is quite remarkable to see how much effort went into developing the language and the progress made since its debuts, 12 years ago.

12 years may seem like a very long time, but as I listened to Eric’s presentation it struck me how these changes actually accompanied the shift in the type and nature of the systems we are designing. When SystemC was first launched, back in 1999, the mainstream part of the industry was still in the ASIC/IC era. At the time, SystemC offered HDL-like signals and processes. Today we live in the times of MP-SoC and SystemC now brings TLM for complex switch fabrics and even AMS extensions for the RF parts of the system.

Of course, the big SystemC topic “du jour” is P1666 the IEEE standardization project meant to enhance and complement the current SystemC 1666-2005 standard of which 27,000 copies of the LRM have already been downloaded.  P1666 will be a major milestone for SystemC. It will incorporate the TLM2.0 libraries, add support for the so-called “process control extensions” (asynchronous resets, at last!) and the Synthesis Working Group (SWG) is currently realigning the proposed synthesizable subset to comply with the new IEEE standard.

But real good news reaches beyond SystemC. Accelera has adopted TLM as part of its new UVM1.0 standard. This is promise of interoperability and the end of counterproductive language wars and debates. It doesn’t have to be SystemC or SystemVerilog. Moving forward it can be both, as already exemplified in the TSMC Reference Flow 11. Standards are good as long as they are not mutually exclusive. We can thank Accelera for bringing SystemC and SystemVerilog one step closer.

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