Ramping up with C Synthesis, part 2

Recent testimonials and success stories from engineers at STMicroelectronics, Texas Instruments or Fujitsu give a pretty good idea of what can be accomplished with C synthesis. If you are interested in gaining a deeper understanding of how C synthesis really works and what synthesizable C code looks like, I can only recommend this upcoming web seminar:

• Mobile Chip Design Using High-Level Synthesis

Hardware for mobile devices has some of the most intricate design constraints of any ASIC development flow. The hardware is constrained by tight area and power requirements and design cycles are often less than a year, requiring tradeoffs to be made quickly without exploring all the possible solutions. Hidden away in most of the mobile devices manufactured this year you’ll find hardware built using high-level synthesis. Usually it is focused on the wireless modem, and sometimes in the custom hardware for video and audio processing. This webinar discusses how HLS has been used successfully in mobile devices based on real-world experience. This will include best practices and the key technologies that make HLS a reality in mobile device design. [click here to register].

My colleague Dan Gardner, who also runs his own high-level synthesis blog, will walk you through a 64 QAM decoder example, including complete C++ source code description. In relationship to the source code, Dan will explain how synthesis constraints such as loop merging or loop unrolling can be used to achieve an optimal RTL implementation given a 30Mbps throughput requirement.

Catapult C can help you achieve significant productivity gains, but getting there requires a ramp up phase. Dan Gardner will help you take the first step on November 3rd. Mark your calendars!

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