User Interview: Designing a Set-Top-Box IP with Catapult C

In a recent presentation at the Mentor User2User conference in Dallas, TI’s Karl Renner gave a very detailed presentation on how he used Catapult C to design a set-top-box IP. With only two engineers working on a tight 6 months schedule, Catapult C proved a necessity to complete the project in time.

Karl Renner works as a systems engineer at Texas Instruments in Dallas and over the past 12 years he has been primarily working on analog and digital video chips. After his presentation, Karl was kind enough to answer a couple of questions for this blog.

Q: What kind of design did you create with Catapult C?

The design is an audio/video RF modulator for a set-top-box application. The audio comes at a low-frequency rate, the video at a high frequency rate. The system does filtering, BTSC compression on the audio, AM and FM modulation and combines the modulated audio and video to generate the final RF outputs which correspond to channel 3 and channel 4 frequencies – these are your old analog TV frequencies. The purpose of all this is to provide a connection on the set-top-box to people who have analog TV sets.

Q: Can you give us a sense of the complexity of the resulting hardware?

This design was a full sub-system comprising 6 hierarchical blocks: 2 for video, 3 for audio and 1 for generation of the RF samples. The total area was 240k gates with a clock frequency of 216Mhz.

Q: What was the design flow during this project?

We started with Matlab to quickly evaluate and design a floating-point version of the RF modulator. Once that model was working, we carried it to a fixed point model in C++ with the help of the Catalytic/Agility tools. Fixed-point C++ is much faster than anything comparable in Matlab, and the AC data types made fixed point modeling very easy.

We compared the output of the C++ model with the output of the Matlab model and we also generated data samples that were fed into a Techtronix arbitrary waveform generator to test the audio and video on TV sets in the lab.

We used Catapult C to synthesize Verilog RTL from the C++ fixed-point model.

Q: Can you describe your experience with Catapult?

This was my first design with the tool and I found running Catapult C quite straightforward. Tony Van Dinh from Mentor Graphics helped us with the initial configuration and some coding style guidance. Achieving proper throughput was an essential aspect of this design, and we were able to use Catapult C’s pipelining constraint to obtain what we wanted.

After looking at different ways of implementing the RF modulator, I was rapidly able to arrive at an optimal implementation. The Gantt chart view was very helpful. It lets you look at the scheduling, if there are problems with it and where to improve the design for performance or area.

Most importantly, the SCVerify flow automatically checks the RTL against the C++ code. With the SCVerify flow I was assured that the RTL output was correct. Being able to look at the input and output signal waveforms and see that the input are being read at the proper intervals and outputs occurring every clock was very important.

The RF modulator was a pretty significant development with a short timeframe. The BTSC encoder and stereo separation proved particularly challenging. We spent a lot of time tuning this part of the design in the lab. For that matter, being able to make quick iterations on the RTL was critical. Catapult C and its ease of use was essential for us to meet our design goals

Q: Have you done other projects since then?

I did do another designer: a jitter pre-correction filter that is applied to the RF modulator output to compensate for jitter of the clock. For this design, and after the experience gathered on the first project, I was up and running on my own.

Q: What’s next?

I am now involved in ultra low-power processor design and one thing I want to do is use the latest Catapult version and try out the new low-power optimizations.

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