46th DAC / STMicroelectronics designs a Frequency Domain Processor out of pure C++

 

A couple of hours after Hitachi Telecom’s inspiring presentation on a 2 million gate enhanced Forward-Error Correcting (FEC) system designed with Catapult C, Nitin Chawla of STMicroelectronics gave extensive details on his experience with C synthesis for complex signal processing applications.

• Differentiating the high-level synthesis input languages

Chawla opened his talk by comparing the merits of the various languages available for high-level synthesis. C, C++ and SystemC are often bundled together as if they all were the same. The truth is that these languages, despite their common DNA, are very different. The language choice will actually have big consequences. According to Nitin Chawla, “structural languages restrict implementations to few solutions in close proximity” as they embedded architectural details embedded in the source. Restricted ANSI C on the other hand doesn’t hardcode the structural details, but without support for classes and object oriented programming, reuse is limited, coding style is complicated and the bit-accurate modeling and numerical refinement is made more difficult. Nitin Chawla views pure ANSI C++ as “extremely compact, allowing object oriented hardware reuse and enabling optimization through interactive constraints”; in short, the right language for high-level synthesis.  

The design presented was a frequency domain processor with real time 1GSamples/sec interfaces. While the algorithmic nature of the application is obvious, the design also involved sophisticated control to manage “interleaved processing”. Chawla explained how the entire system was modeled in pure C++, providing details on how the above mentioned control was also described and synthesized.

The complexity of the system, including its 2048-point FFTs is simply mind-boggling. The ability of explore both the architectural and the algorithmic design space with a C-based methodology proved to be an absolute must for the project’s success. 

• Linking C Synthesis and Physical Design

This was confirmed in the later phases of the project when physical design started. Chawla pointed that “in ASIC technologies of 65nm and below path delays are wire dominated”. His design, like most signal processing applications, use a lot of compiler generated memory cuts. At the system-level, memory architecture choices tend to be made on the simple basis of bandwidth and ports. But, continued Chawla, “memory cuts create routing blockages and wire detours”. Using the C synthesis flow, different memory architectures could be easily produced, and a multi-bank memory solution could quickly be found to reduce routing congestions.

• A “production-worthy” solution

In his conclusion, Nitin Chawla was very affirmative of the benefits and the maturity of C synthesis solution such as Catapult C. C synthesis provides increased productivity, more flexibility as well as better quality of results. And to quote Chawla one last time: “C synthesis can successfully build production worthy multi million gate complex application engines from untimed C/C++ algorithmic models”.

 

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