Simon’s DFM Corner
DAC: Veni, vidi, steti
Taking liberties with Latin and Caesar’s “Veni, vidi, vici” line, I can say “Veni, vidi, steti.” I came, I saw, I stood. :=) While the main Mentor booth seemed to be quite busy the whole time, I was elsewhere working booth duty at the TSMC OIP pavilion. It was a nice, open space kind of like the vendor area at a TSMC tech forum. The TSMC booth was very busy on Monday, with a lot of people representing that large company known as “Self” (groan), but the rest of the week was very light. People did come through in waves as general sessions ended. I was there to give demos. I talked to a number of people who wanted a 5-minute education on DFM. That’s OK, because we need more people to know about DFM, but 5 minutes is only enough to convince them that either they need to know more, or it’s something they don’t need at this time. I gave maybe 4-5 real demos to seriously interested people all week. I had 6 demo time slots per day, so yes, I stood around most of the time.
I had two good meetings with current DFM customers, one scheduled, one impromptu. Both meetings were of high value to all involved. When traffic is slow, the real value of DAC is being able to meet with people you might not otherwise have in one place and time. That’s getting quality time with quality people.
The one place at DAC I would not like to have been in is the Magma booth. On Monday, as the show opened, there was buzz about the financial community raising “going-concern” doubts. The Magma booth at the TSMC pavilion was empty most of the week. It wasn’t even staffed full-time. The main Magma booth was extremely small, given their past history. Remember the volcano? Those days are long gone. Will Magma survive the downturn? Only time will tell.
In contrast, TSMC’s neighbor at DAC was Apache Design Solutions, which seemed to be doing very well. Their traffic was helped by having a great giveaway (plush bear toy). They seemed to be having a very productive and busy DAC. On the other hand, they are still a private company, and people who have been there a while still haven’t collected anything on their stock options. Who’s going to go public in this climate?
Some people at DAC were wondering if DAC will survive. Some wondered if EDA will survive. One person even projected that EDA will be dead and gone in 5 years. I don’t believe that. I think EDA will surely survive. Just think of all those Calibre licenses! :=) I don’t know about DAC, though. It certainly doesn’t provide as much value as it used to. I happen to like DAC, I’ve worked quite a few. Let’s see what happens next year. It’s probably a safe bet that Anaheim in June will at least be warmer than San Francisco in July.
What do you mean by mandatory?
TSMC and Mentor Graphics recently held a joint Marketing seminar (06/25/09) for mutual customers to go over the new DFM requirements at 45/40 nm. (In my first post, I mused about the implications of making some DFM analysis steps mandatory.) When the presentations at the seminar ended, and the Q&A began, two customers basically asked the same question, “What do you mean by mandatory?” Of course, TSMC wasn’t going to stand over them and say, “Mandatory means mandatory, what part of mandatory don’t you understand?” :=) TSMC admitted that they haven’t changed the tape-out checklist to forcibly include the DFM checks (CMP and LPC). This is what begs the question, what do you mean by mandatory?
What it really comes down to is this: if you tape out without these checks at 45/40 nm, you are taking a risk. If the design has yield issues and you didn’t run these checks, TSMC might wave the design off and insist that you take ownership of the yield issues. This is a huge risk. If the part comes out and has zero yield, and they find out it’s because of a level 1 hotspot in litho, or bridging due to CMP that you didn’t check for, then you have to eat the cost of a respin. Most design teams doing large designs count on a certain number of respins before full production anyway, but to have to do one before you have any functional parts is a disaster. If you get parts that yield, but yield poorly, it can be just as bad, because these things can take a long time to find using traditional Low Yield Analysis, or FA. As someone who once had to re-spin a custom design due to a flaw in the incoming spec, the worst thing management can ask you before a re-spin is, “Are you sure that’s all that’s wrong with the design?” That one is guaranteed to cause sleepless nights.
TSMC pointed out that they have very little history on the 45/40 process at this time. This means there might be yield issues, and there is a definite need to do DFM analysis at this point in time. TSMC also pointed out that DFM analysis might not be mandatory once the process is considered stable. I think that by that time, the next process node will be in the hands of the early adopters, and DFM will be mandatory for that node, so the need for DFM won’t be going away anytime soon. According to this article and this article on the web, the yield issues are real. Considering the total cost of developing a chip in 45/40 nm and the risks of really low yields, DFM tools seem like cheap insurance.
Conclusion? Buy DFM tools from Mentor Graphics. You’ll sleep better. :=)
So, why not just write better rules?
In my previous post about TSMC making some DFM analysis steps mandatory at 45nm, I ended with a question about why the foundries can’t just write better design rules (and rule decks) to make sure all designs yield well. This is a topic that has been discussed elsewhere, but here’s my take on it.
If we take a step back for a moment, there is something generic about DFM analysis that needs to be considered. Each type of DFM analysis has a “sphere of influence” in its scope. For CMP analysis, the analysis window size is around 20um. That’s large compared to a standard cell. For Critical Area Analysis (my favorite tool), the analysis scope is the size of the largest random particle to be considered, typically anywhere from 2um to 10um diameter. For Lithography analysis (LFD), the scope is a little smaller, roughly 1-2um.
How does this get back to rules? What’s the scope of a generic DRC rule? A shape all by itself, or a shape within a shape, or a shape and its nearest neighbors. In common practice, that’s about it in DRC land. Mentor has eqDRC, an extension of the Calibre nmDRC product that allows you to write equations to express rules instead of using fixed values, but you still can’t easily get past the nearest neighbor in a DRC rule. Yes, you can write complex rules to go one or two shapes past the nearest neighbors, but the complexity of the rule and its runtime will go up exponentially, the farther you try to go from the original shape. What this means is that it will be difficult if not impossible to write rules that take into account enough of the context of the shape being checked. DFM tools automatically take context into account. That’s the big advantage of model-based, over rule-based analysis.
At this point, DRC is “necessary but not sufficient.” The more “not sufficient” it becomes, the greater the need for DFM tools that see the extended context of all shapes in the design that are close enough to have any adverse effect. Of course, the farther upstream you find and fix a DFM issue, the easier it is to fix. That’s why I expect this trend of pushing the designers to do DFM analysis to continue, and for more foundries to follow TSMC’s lead.
By the way, the comment about DRC being necessary but not sufficient is not meant to belittle DRC. DRC is of course, mandatory at all nodes. DRC is also absolutely necessary in a DFM flow because for one thing, all DFM tools assume the design to be (essentially) DRC clean. If you get too far outside the allowed range of analysis in DFM because the design is not clean, the results can be inaccurate.
Ah, but Restricted Design Rules (RDRs) are going to fix everything, right? We won’t even need DRC or DFM anymore, right? Not so fast…
– Simon
TSMC’s DFM Announcement
If you are a TSMC customer, no doubt you have heard that TSMC has announced that for 45nm (and presumably beyond), LPC and VCMP are mandatory for block/chip. What does this mean? It means that TSMC is requiring lithography and planarity analysis for all 45nm designs. Their website says customers can either run it themselves, or contract TSMC services to do it. The most cost-effective way would be for the customers to run it themselves, but some might not have the resources to do that. Of course, by the time you pay TSMC to do it 3 or 4 times, you could have bought some tools and run it yourself. That’s good for Mentor and other EDA vendors, right? Probably, but there has to be more to it than that.
So, what’s really behind this? TSMC isn’t generally known for making things easy for EDA vendors. Why make a new step mandatory like DRC is? Is it because they’re having real yield issues at 45nm, and they want the customers to find and fix issues themselves? Possibly. Is it because the DFM tools are finally mature enough to be a required part of the flow? Well, maybe they are, but that’s probably not the reason.
I think it has to do with money. As they say, “Follow the money.” Having low-yielding parts in the fab doesn’t do anybody any good. Most TSMC customers buy wafers at a pre-negotiated price. If the part yields poorly, the customer will likely have to buy more wafers to make up the volume, and will try to renegotiate the price. How is it bad for TSMC if they buy more wafers? Because that makes TSMC’s production starts more unpredictable. A small company with one product could go out of business if good die are costing them too much as a result of low yield. Orders from medium-sized companies could fluctuate wildly. That would really make things unpredictable for TSMC. Low yield would also hurt TSMC’s reputation. They like being #1 in the foundry business. They like being thought of as the best. Having lots of customers complaining about price and yield puts that at risk. Not only that, but to resolve low yields, TSMC would have to devote more resources to these problem chips, which would cost them real money. Even worse, some large customers actually buy good die. Low yield for those customers would directly impact TSMC’s bottom line, as TSMC would have to make up the difference. Follow the money. Having happy customers who sell more product, make more money, and come back for more high-yielding wafers probably makes the most sense for TSMC. The trend seems to be to make the customers more responsible for DFM. Expect other foundries to follow suit.
So why can’t the foundry just write better rules to make sure that all designs yield well? Hmmmm….
– Simon
About Simon’s DFM Corner
Technical aspects of DFM, DFM use models, applications and solutions.
Latest Posts
- DAC: Veni, vidi, steti
- What do you mean by mandatory?
- So, why not just write better rules?
- TSMC’s DFM Announcement