Thermal Design Perfection Starts with the use of FloTHERM PACK

‘Plagiarism saves time’ as can be seen in the title of this blog, a nod to Tom Hausherr’s excellent blog series, particularly Part 15 that focuses on QFNs. Whereas the internal construction of a package is of little interest when defining CAD library symbols, from a thermal simulation perspective they are absolutely critical. FloTHERM PACK can be seen as a ‘pre-processor’ for FloTHERM, enabling the specification and generation of thermal models to be used in full 3D FloTHERM simulations. Supporting the parametric definition of a wide range of package styles, it can drastically reduce the time required to build an IC package thermal representation (not as much as getting a validated one from your supplier but that’s another story).

qfn_1Numerical generation of an accurate thermal model representation of an IC package requires the package geometry and materials to be known a-priori. To simulate a temperature rise of a die over ambient temperature all the thermal resistances the heat experiences as it passes from the die through the die attach, pad, leadframe, PCB, chassis etc. need to be considered. For a QFN (and all other FloTHERM PACK supported package styles) this is done via a few choice parameters shown in the adjacent figures.

qfn_explodedOnce entered then either a geometrically ‘detailed’ model can be created or a CTM (compact thermal model, kind of a thermal SPICE model). The detailed model with have 3D geometric items representing each part of the package. Once you have that your simulations will provide a complete overview of the heat loss paths and resulting temperature gradients.

The least a thermal simulation will do is to indicate if the junction temperature of a package exceeds the maximum rated value. An observatory approach to thermal verification. A simulation was conducted of this QFN sitting on a 4 layer board with the thermal vias connected to the ground plane and the entire board edge cooled. Power dissipation = 1W, ambient temperature = 35degC.

qfn_temp1

The package and vias are defined to facilitate the conduction of heat down to the internal ground plane where the heat can be efficiently removed (i.e. lots of Watts shifted with little temperature rise penalty). Examining the heat flux budget you can quantify that, in this case, the vias take about 98% of the heat. Graphically you can show this by animating the heat flux field, introducing heat flux ‘particles’ at the die:

qfn_heat_flux

The particles are coloured by our new Bottleneck (BN) parameter, indicating where the heat experiences thermal bottlenecks characterised by a lot of heat flow AND difficulty in heat flow. Check out this Bottleneck webinar for more details! In this case the bottlenecking effects of the vias and ground plane far outweigh any bottlenecks inside the package. So, if you’re going to do anything to lessen the temperatures then do it in the board, not in the package (though of course beyond package selection, who has the freedom to do both?).

Be it LP Wizard, FloTHERM, Expedition PCB or HyperLynx; the Board Systems Division in Mentor is the market leading one stop shop for all your PCB design needs.

April 8th 2011, Ross-on-Wye

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About Robin Bornoff's blog

Views and insights into the concepts behind electronics cooling with a specific focus on the application of FloTHERM to the thermal simulation of electronic systems. Investigations into the application of FloVENT to HVAC simulation. Plus the odd foray into CFD, non-linear dynamic systems and cider making. Robin Bornoff's blog

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Commented on April 18, 2011 at 4:04 am
By Robin Bornoff

FloTHERM PACK creates 2-R and DELPHI compact thermal models, both based on published JEDEC standards. Unfortunately those standards only involve the determination of steady state thermal resistance values, not thermal capacitances. We have to ensure that FloTHERM PACK uses only recognised standard approaches that will be accepted by the industry. When standards appear that result in transient compact thermal models then FloTHERM PACK will adopt them.

Commented on May 8, 2011 at 9:15 am
By Robert Tso

I see two issues with FloThermPack:
Unless we are the manufacturer of the QFN device (or whatever package)
1. We typically don’t know the die size
2. We typically don’t know how power density across the die so we typically have hotspots that will limit reliability
So how useful will this tool really be in predicting reliability?

Commented on May 9, 2011 at 1:17 am
By Robin Bornoff

Robert, point 1 – the age old primary problem facing the thermal engineer, lack of data. First option, ask your supplier. Second option, acid etch away the encapsulant to find out. Third option, x-ray. If thermal reliability is important enough you will find a way to find out die size.

Point 2 – for many years thermal engineers have been assuming constant power dissipation distribution on the die and making thermal reliability decisions based on the predicted junction temperature. FloTHERM PACK does have the ability to define a power map distribution but the challenge is obtaining that information from your power engineers/EEs.

You have two choices: 1) do no thermal simulation and run a high risk of thermal reliability issues in your final product. 2) do some thermal simulation, with known assumptions/lack of data, to get some idea of possible thermal issues. I would advise 2).

Yours
Robin.

[...] To220 detailed model was created using FloTHERM PACK. This involved a parametric definition of its construction and then pressing the ‘download [...]

Commented on June 12, 2013 at 6:44 am
By paulo luiz

The thermal resistance from junction to board (Rjb) in a 2R CTM is obtained experimentally based in a JEDEC PCB standard .
When I use a 2R model in thermal simulation softwares, like the HyperLynx Thermal, that models the pcb in more detail, (e.g. with thermal vias and thermal pads), will not this fact mask the results of junction temperatures of the components?

Commented on June 12, 2013 at 7:15 am
By Robin Bornoff

Rjb is experimentally measured as defined the the JEDEC standard JESD51-8. The point at which the board temperature is measured, for leaded packages is on a foot of a lead, half way down the width of the package. For an array type package it’s 1mm from the package side on a trace on the test board. This does include a thermal resistive affect of the board under the package itself. I’d advise that you check out section 7 of JESD51-8 for some good advice about the use of Rjb. The point being that if no other thermal data is available then it’s the best that can be done. If you have access to either DELPHI type models, or geometrically detailed models, and a tool that can utilize them, then that would provide even greater accuracy.

Commented on June 12, 2013 at 10:20 am
By paulo luiz

Hi Robin
Thanks for your clarification.
I used the Flotherm four years ago in the company Nokia-Siemens. Now in the company Datacom the thermal simulations are carried out by Flow simulation (the same software FloEFD of Mentor Graphics). Flow simulation supports only a 2R CTM.
For better accuracy can I model underneath of a SO-8 package 2R model, a thin copper foil on the top side of the 10-layers PCB board to represent the area of thermal pads?

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