VHDL-AMS Stress Modeling – Part 2

In Part 1 of this series I started work on a simple resistor model as a way to illustrate some of the flexibility the VHDL-AMS language offers when creating simulation models. Recall that one of the advantages of VHDL-AMS is adding detail to models – a benefit not available with all modeling languages or methods. With VHDL-AMS, it’s possible to get your model and simulator to report performance details not available with other tools. To illustrate this flexibility, my resistor model will include a power dissipation calculation, and a comparison of the result with a user defined power limit to determine stress conditions.

Before jumping into the next model piece, however, I’ll tie up a loose end I left dangling in my earlier post. I mentioned the use of “==” when formulating device equations in a VHDL-AMS model. And at that time I said to simply interpret the syntax as “equal to”. But that definition doesn’t quite cover what’s going on inside the simulator. The “==” is more accurately interpreted as “balance both sides of the equation”. Once the simulator generates a matrix of equations that represent the system, the unknowns are adjusted during simulation, through a series of iterations, until all equations are solved within a user defined accuracy.

Now back to my resistor model. I’m going to jump right into the next architecture, so if you need a review (or a preview) of the model so far, take a quick look at Part 1. Up to this point it’s a basic Ohm’s Law-based resistor: voltage across the resistor is directly proportional to the product of the current and resistance. Now it’s time to add commands to calculate the power.

Recall once again from your first physics or electric circuits class that the power dissipated in a resistor is dependent on any two of its three operating parameters: voltage, current, resistance. There are a few different combinations of these parameters that calculate power, but I’ll use the following:

   power = voltage x current

Based on this equation, here is the next section in my model:

   1: architecture power1 of resistor is

   2:   quantity vres across ires through p1 to p2;

   3:   quantity pwr : power;

   4: begin

   5:   vres == ires*res;

   6:   pwr == v*i;

   7: end architecture power1;

Here I’ve created a new architecture named “power1” for the resistor model. This architecture is the same as the “basic” architecture in my earlier post, except that its name is changed and Lines 3 and 6 are added to setup the power calculation. Line 3 defines a new quantity named “pwr” (remember that a quantity is an analog element in a model) with an assigned VHDL-AMS type of “power”. Note that pwr is not directly associated with the p1 and p2 ports of the model. Therefore the type assignment simply determines what units will be used (in this case “watts”) to plot the pwr quantity. Line 6 calculates pwr as the product of the voltage across the resistor and the current through it, as define in the standard power equation above. This architecture can be added to the model in Part 1 to create a resistor model with one entity and two architectures (recall that a VHDL-AMS model can only have one entity, but multiple architectures). When I use the resistor model in a SystemVision schematic, I can select which architecture to use for that resistor instance. If I choose the power1 architecture, the resistor’s power is calculated at each time or frequency step during the simulation, and becomes a waveform I can plot when the simulation is finished.

Now that my basic resistor is complete, I can add details that will determine if the power exceeds a user defined power rating. In Part 3 of this series I’ll create another new architecture that detects when the resistor’s power exceeds a user defined limit, and notifies me when there is a problem.

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Posted January 28th, 2013, by

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