VHDL-AMS Model Portability — Fact or Fiction?
Once in awhile I work with customers who want to move VHDL-AMS models between multiple simulators. The ability to do so is one of the great promises of standard modeling languages and, at face value, should be an easy task. After all, if a language is an industry standard, and multiple simulation tools claim to support it, then moving models between tools should be a plug-and-play process, right? Well, the answer is both “yes” and “no”. Sometimes it truly is plug-and-play with models working well across multiple simulators. But more often than not, moving VHDL-AMS models between simulators from different vendors isn’t as easy as you might think. The problem is not in the language itself, but in how the vendor interprets and implements language features.
Standard languages are typically supported by a standards body which, with the help of its members, defines language functionality and documents required features in a Language Reference Manual (LRM). LRMs are weighty documents, usually several hundred pages long, containing everything there is to know about a language. The latest version of the VHDL-AMS LRM (IEEE STD 1076.1-2009) stretches on for 340+ pages. For the average reader, even someone with a background in modeling and simulation, it is not a light read.
To support a language standard, tool vendors must first interpret the LRM as accurately as possible, then implement their interpretation in a simulation program. Problems relating to model portability start with LRM research and generally take one or two forms. First, the tool vendor needs to determine which language features to support. It shouldn’t come as a surprise that developing simulation support for a new language is not an overnight task. Supporting a new language often takes several man years of development work, especially if language support first requires a new simulator. A simulator won’t be viable in the market until it first supports a core set of language features, but opinions about what constitutes a core feature set vary a bit between tool vendors. This leads to language features supported in one simulator that are not supported in another.
Once a tool vendor determines which language features to support, the next model portability stumbling block results from language feature implementation. In other words, once a tool vendor decides which features to support, the next step is determining exactly how to support each feature. Hopefully, the LRM is written well enough to limit implementation errors. But errors do creep in. Tool vendors exacerbate this problem when they are lax in strict adherence to LRM requirements. As an example, some simulators allow non-standard syntax that might cause errors in tools that more strictly interpret the LRM. Once again, this leads to models that work in the parent simulator but possibly not in others.
Language standards are not new to the simulation tool industry. Nor is the ability to move models between tools from different vendors. Users have successfully done so with standards-based digital models for years (think simulation models based on the popular VHDL and Verilog logic modeling languages). Mixed-technology language standards, however, lag logic modeling languages in model portability, but are gaining popularity. As mixed-technology languages like VHDL-AMS grow in popularity, so will their broader acceptance. And as acceptance grows, so will multi-vendor simulation support until seamless model portability is a reality.