Source Netlist Creation for LVS

Hopefully you’ll find the current and future content posted here interesting enough that you’ll come back and share own opinions, thoughts and ideas. Please let me know if there are specific topics you’re interested in. Maybe we can look at these in the future…

Today, I’d like to explore the task of creating a trusted source netlist that is used as the template for comparison to prove that your layout is good. The actual proof of comparing two dis-similar, yet equivalent SPICE netlists is handled pretty well by layout versus schematic (LVS) tools. Over the years a nice solid methodology for this comparison has been developed and the mechanics of LVS are well understood by many. But getting to the point where you have that trusted source netlist to take to comparison still seems as much experience and art, as it is about the technology. Especially for a complex mixed-signal design. A good dose of faith in your process, trust in your LVS tool, and experience to tie it all together seem to be a common (and winning) strategy that many often use.

So, how do you go about managing the complexities of putting together your trusted source netlist? Single language designs from SPICE or Verilog may seem easy enough, at least conceptually, while mixed-signal designs require a bit more fiddling – So how do you know your done? In Calibre land, there are some utilities to aide with the transformation. Do they suffice? Or are you using something internal, or looking for more?

Let me know your thoughts and opinions…

 

Matt.

Post Author

Posted May 22nd, 2009, by

Post Tags

, , , , , , , , , , ,

Post Comments

1 Comment

About Matthew Hogan's Blog

Physical and Circuit verification of today's multi-billion gate designs is hard. Heck, even verification of what's considered a "small" design today is hard. The complex work we do day-to-day to make silicon function is akin to magic for most of the population on this planet. What do you do to make things simpler, easier and more efficient? What are the trends you're seeing? Best Practices? Got ideas to make things simpler, more robust and more efficient? Come join in, and share... Matthew Hogan's Blog

Comments

One comment on this post | ↓ Add Your Own

Commented on July 8, 2009 at 10:07 am
By Tony Liao

Hi Matt,

Great subject your brought up here!

Indeed, the creation of a reliable source netlist is getting more challenging. Nowadays, the boundary of source and layout is getting more and more vague. It might not be a one shop LVS any more. We should chat more on this, especially for mixed-signal and nanometer designs.

Add Your Comment