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For customers who were unable to attend DAC this year, we are hosting Mentor @ DAC Extended. The registration is at: http://www.mentor.com/events/mentor-dac-extended/
What is Mentor @ DAC Extended?
Mentor @ DAC Extended is an online presentation of 22 of our DAC 2010 suite sessions. Each 50 minute presentation includes:
• presentation by technology area experts
• live Q&A
• an archive of the session emailed to you
The session for Calibre xACT 3D is on July 14th, 9 am US/Pacific
Here is the abstract for it:
When doing parasitic extraction, designers have long faced a performance versus accuracy dilemma. That is, to get high accuracy, they had to pay a prohibitive performance penalty. For high-performance, tradeoffs in capacitance accuracy had to be made. Calibre xACT 3D is a next generation field solver technology that solves the problem by delivering reference-level accuracy along with the performance and functionality necessary for production design flows.
We hope that you can attend!
Mentor Graphics is excited to announce the launch of their new fast field solver for IC design, Calibre xACT 3D http://www.mentor.com/calibre-xact. This new tool is based Mentor Graphics’ acquisition of Pextra Corporation last year. This deterministic field solver has break-through performance, and excellent scalability, which enables the efficient use of multiple CPUs to achieve the fast turn-around-time. Since it is fully integrated into the Calibre environment, it works seamlessly with Calibre LVS, and with Calibre Interactive and RVE, which lets customers easily run the tool in their design environment using foundry rule decks.
In Mentor’s press release at http://www.mentor.com/company/news/calibre-xact-3d , Stephen Fu of UMC states: “Our customers require reference-level extraction accuracy to ensure realistic simulation of complex devices manufactured at 45nm and beyond.” It is the combination of field solver accuracy, high performance, and modeling of advanced process effects and process variation that provides value for our customers.
The largest design that I have personally run on this field solver is a one million net SRAM, which ran in slightly more than 4 hours doing flat RCC extraction with 4 CPUs. This to me seems quite reasonable, considering you can also run in hierarchical mode, which would greatly speed up the extraction run. I think that field solvers are very useful, because you can attain a high level of accuracy, and with the accelerated performance and ability to use multiple CPUs, run time is less of an issue.
Do you currently use a field solver? Why or why not? What do you use it for?
More and more digital processing functions isolated into multiple power domains, hundreds or thousands of analog-digital interconnections, operating frequencies always closer to pure RF — clearly, genuine full-chip verification of complex mixed-signal systems-on-chip (SoCs) calls for careful planning and organization, as well as flexible simulation technologies. Whether you are verifying a power-management circuit, a single-chip multi-standard radio transceiver, or a mobile communications processor, different strategies are required. Technologies that allow transparent and efficient combinations of analog/RF descriptions, analog/mixed signal (AMS) behavioral models, and pure digital descriptions — all interoperating under a common verification platform — can help maximize full-chip, mixed-signal verification.
Mixed signal design starts are increasing. An AMS SoC designer applies various design formats for the different blocks, with different levels of abstraction. The different formats are typically classified into either digital or analog design. For purely digital designs, many production-proven tools are available for standard cell creation, behavioral language simulation, synthesis, and place and route. For analog designs, traditional tools are used for schematic entry, accurate device-level simulation, handcrafted layout, and interactive wiring.
How do you integrate the design blocks at the chip level and complete the testing and verification? Do the blocks really fit together at the top level? Will the design function as planned? To ensure a working design, an AMS/SoC chip-level design needs to be verified in its entirety. For this purpose, digital/analog (D/A) integration is mandatory. Shrinking manufacturing processes require inclusion of parasitics for analysis, and the integration of parasitic data adds yet another level of complexity to this problem. However, a post-layout simulation netlist can be created that includes parasitics and handles various data formats and that will effectively re-simulate the design using layout parasitic effects to maintain signal integrity.
Yield problems and multiple spins are caused by missed deep submicron effects. Mixed-signal SoC designs require full-chip timing analysis as well as full-chip signal integrity analysis. Unfortunately, flat full-chip parasitic netlists are huge and impossible to simulate with traditional flat SPICE-type simulators.
How do you deal with these issues?
Thanks everyone for voting on my posting:
Since I didn’t exactly get consensus on what topic I should work on next, I thought I’d pick two topics that a few of you wanted. Here it goes:
Topic 15: Why my previous car was named Bob?
My old white Toyota Camry was called Bob, because it was sooooooo boring that I named it the most boring name I could think of. Unfortunately, Bob is also my father-in-law’s name. But it’s not commentary on him at all, just the car.
My husband’s red Ford F-150 is called “Cotton-Eyed Joe” because it’s a hick name for a hick truck.
My current white Ford Escape is nameless. It did originally have the name “The Cloud Car” because it housed my Care Bears and it was white, but it just didn’t have the right vibe. Hey, maybe I’ll have a “Name My White Ford Escape” contest. What do you think I should name it? The winner will get a lovely Calibre prize package, including a white Calibre dress shirt, Calibre golf balls, and a Calibre stopwatch. Just respond to this blog with your suggested name, and you’ll be entered into the contest.
Now for something a little more serious…
Topic 11: Process variation – the use of in-die variation
Process variation refers to the thickness and width variation that occurs during the chip fabrication process. If the in-die process variations are not modeled accurately, the potential for silicon failure is very high. When doing extraction at the cell and block level, it is possible to complete extraction with process variation models such as in-die variation tables, but since metal fill is only inserted at the full-chip level, calculations such as density only make sense at the full chip. Therefore, in the design flow, at the early stages of cell and block level, using estimated density to calculate in-die variation makes sense. Then after full-chip metal fill insertion, a more accurate extraction can take place.
Parasitic resistance, capacitance, and inductance are calculated based on the drawn dimensions of the polygons, and on the process information such as metal thickness, dielectric thickness, and the dielectric constant. But control of fabrication tolerances have not kept up with the fast rate of technology shrink. Chemical mechanical polishing (CMP) is a technique used to manufacture copper interconnect. Because a slurry is used to grind down the copper, conductors that are wider will have more copper loss than conductors that are skinnier. Since the thickness has changed because of the CMP process, the parasitic resistance, capacitance and inductance of that metal will shift.
Another cause of the manufactured interconnect being different from the drawn dimensions is due to the limitations of the manufacturing process. It is limited in part by the wavelength of light used in photolithography. In order to overcome this limitation, optical proximity correction (OPC) is used. OPC is a method used to manufacture structures with dimensions less than the wavelength of the light used to illuminate the wafer. Even with the use of OPC, the manufactured dimensions will vary from the drawn dimensions. Like CMP, OPC effects will also alter the parasitic resistance, capacitance, and inductance of the interconnect.
There are three main methods used to feed process variations into a parasitic extraction engine: process corners, in-die variation, and statistical analysis.
With process corners, there will be several different extraction rule files that are created, depending on the changes to the process layer information. For example, the metal, polysilicon and dielectric layers will have a minimum and maximum thickness, depending on the variability of the process. Using combinations of the typical, minimum and maximum thicknesses, different extraction rule files can be created. Then using these different process corner files, several extraction and re-simulation runs can be completed.
The next method is to use either table-based or equation-based in-die variation. These tables or equations model the changes to both the manufactured conductor width and thickness due to three different factors: drawn conductor width, spacing to the nearest conductor, and local density. The tables or equations are built from metrics measured from test chips. For the local density measurements, it only makes sense to do local density calculations after metal fill has been inserted. Therefore, it is important for a parasitic extraction tool to be able to both insert an estimated local density, and to calculate actual local density with the real metal fill polygons. Metal fill prevents slumps in the vacant areas, but impacts capacitance. Therefore, it is also important to compute floating net coupling capacitance between two signal lines across fill.
The third method is to use a statistical approach for modeling manufacturing variations. The process parameter variables to consider are gate length, thickness of the gate oxide, metal width, thickness and dielectric thickness. Transistor-level simulation with Monte Carlo analysis can be done using a normal distribution of the process variables. This type of approach would require parasitic information as well as process variability information. In addition to the Monte Carlo simulation approach, there are two additional approaches specific to statistical static timing analysis: path-based approach, and topological approach. All three of these methods aim to find the statistical distribution of the delay values for all of the critical nets.
Here’s a question for everyone:
Are you concerned about in-die variation? If you are, what are you doing to model in-die variation?
Just in case you were wondering how you can get your picture to show up by your name in the comments and posts, Mentor Graphics blogs uses Gravatar. It checks that database for your email address, and sees if there’s a picture associated with it.
Go to http://en.gravatar.com/ and create a globally recognized avatar image of yourself. This thumbnail image will be displayed next to your name and when commenting on blog posts. The gravatar work off your email address.
Hi everyone, and welcome to my first blog entry. When I found out that I was going to be writing a blog on parasitic extraction, my first thoughts were:
Blog = fun, edgy, exciting
Parasitic extraction = geeky, techie, boring
Blog ≠ Parasitic Extraction
How was I going to make this work? How am I going to make model order reduction and stochastic integral equation solvers and nanometer technology interesting? I decided to enlist the help of my husband, who gets to hear me talk about accuracy and nanometer technology all the time, and here’s what he came up with.
Merrill as Karen Chow:
Welcome to my first blog entry about parasitic extraction (accurate, nanometer). This is very exciting for me because I get to share with you, the blog reader, about what I think about all day. I think it is ACCURATE to say that parasitic extraction is the cutting edge of today’s computer chip development technology. What is the first thought that comes to your mind when you think about parasitic extraction? That’s right!.. Nanometer technology. Just think about that for a while. Nanometer technology is like micrometer technology but BETTER!!
So please come visit here soon and often for next installments of my parasitic blog, for I have so much exciting, extreme, edgy, and accurate things to talk about with you. And for those who have nothing to do this Saturday, coming to Portland to see the Pistol Kitties ROCK THE HOUSE!!
Okay, so that was my husband’s attempt. Nice use of CAPS, I love SHOUTING!!! And I love the blatant, unadulterated plug for our band! But it’s not very helpful. I thought I’d ask you, my highly valued blog reader, about what topics you think would be interesting for future blog posts. Here are my thoughts so far.
1.The link between parasitic extraction and lithography
2.Parasitic extraction and CMP effects
3.Mixed-signal extraction and simulation
4.Statistical process corners
5.Tips and tricks in running Calibre xRC
7.Parasitic Extraction Accuracy: How Much Is Enough?
8.Size, speed and accuracy trade-offs in parasitic extraction
9.Managing the interface between device and interconnect parasitics (How do I know the tool is not double counting?)
10.Using the new MIPT format for specifying process stacks for xCalibrate
11.Process variation – the use of in-die variation
12.Setting up your xcell list to control extraction hierarchy
13.Explaining the three steps for extraction (PHDB, PDB, and FMT)
14.Review of recently published parasitic extraction papers in IEEE
15.Why my previous car was named Bob
Which of these topics would be useful and interesting to you?
YOUR OPINION IS IMPORTANT TO ME, HELP MAKE THIS PARASITIC EXTRACTION BLOG THE MOST AMAZING EXTRACTION BLOG EVER!!!!!!
About Karen Chow's Calibre Blog
This blog talks about the latest advances in Calibre, and also covers news in the high tech industry.
- On-line session covering the DAC presentation for Calibre xACT 3D
- New Product Announcement: Calibre xACT 3D (Field Solver)
- Mixed-Signal SoC Verification
- Process Variation: The Use of In-Die Variation
- Having your picture show up in Mentor Blogs comments and posts
- Fun and edgy parasitic extraction blog?
- June 2010 (2)
- June 2009 (3)
- May 2009 (1)