Posts Tagged ‘power integrity’

13 June, 2012

Well, of course you do – most engineers are pretty good people.  Actually, as much as I’d like to brag about acing my ethics training course (one of those fun corporate things we do every year), that wasn’t really what I was referring to…

Integrity in engineering means that something is as it is supposed to be.  Kind of like structural integrity – there are no holes in it.  For signal integrity, it means that the 1s and 0s you sent from the driver are the same 1s and 0s at the receiver.  For power integrity, it means that the volts and amps you sent to the IC pretty much all got there, for all frequencies of interest – “from DC to daylight.”
I talk more about what this means in my recent article in Electronic Design:

What happens if you don’t have integrity?  Well, in buildings, anyway, it can all come crashing down.  Printed circuit boards aren’t much different… crosstalk, loss, and impedance mismatches are all like termites trying to eat away at your signal integrity.  Using an analysis tool like HyperLynx can help keep your 1s and 0s safe.  Simulating to understand design margins ensures that you are designing a strong PCB, that will stand the test of time, just like a good building.


12 June, 2012

Impedance is an important concept in many different realms of engineering.
We often see it in our everyday life, especially if you’ve ever hooked up a home entertainment system.  From 8-ohm speaker wire to 75-ohm coaxial cable, the right impedance is crucial to watching things explode on your TV and making sure they sound good too.

Simply stated, impedance describes a relationship between voltage and current.  For a resistor, that is a pretty simple relationship: V = IR.  For a transmission line, however, the relationship is a bit more complicated, since energy is travelling in fields between the incident and return path, usually a trace and a plane.  The characteristic impedance of a transmission line must be calculated using a field solver, and serves as the basis for signal integrity analysis.  For a signal, trace impedance is targeted to “match” the driver and receiver impedance.
For power, impedance should always be at a minimum.  For DC power delivery, that means low resistance, or as much metal as possible (planes, vias, traces).  For AC power delivery, that means very low-inductance connections to a large number and range of decoupling capacitors.  This is one of the fundamental differences between signal integrity and power integrity analysis. 
Check out the article below to find out more:

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11 June, 2012

In my previous blog, I talked about how a printed circuit board is nothing more than a path for signals and power to travel to and from ICs.  For a long time, the path was “short” enough to not even matter.  Then signals became fast enough that the board became a signficant part of the circuit, and the realm of analysis known as “signal intgrity” was born.  Really, signal integrity is just the analysis of analog characteristics of digital busses.  Which is a little funny, since many “analog” simulations will ignore the board characteristics (although that trend is changing, as speeds of “analog” busses are ever-increasing).

But the other aspect of design spawning the need for new analysis is the size of the ICs.  There are so many power-hungry transistors on the ICs nowadays that you need to analyze the power feeding them as well.  Just getting the appriopriate DC voltage to these ICs is a challenge, as I discussed last week.  But the AC aspect is also a challenge; decoupling analysis can be pretty tricky.  However, the consequence for ignoring these problems is design failure.

I talk more about the unique aspects of these different kinds of analysis, and compare and contrast them, in my recent article in Electronic Design magazine:
Take a peek…


6 June, 2012

What?  Isn’t that backwards?  Technically, yes.  The board is merely a pathway through which ICs talk to each other, and receive power to do so.  However, if the power distribution network (PDN) of the board is inadequately designed, it can actually be heating up the ICs.

ICs are supposed to be the main source of heat on a PCB.  Heat is conducted from the ICs to the board through their pins.  Sometimes a metal slug or thermal glue is placed at the base of the component to enhance this effect.  This method of component cooling is sufficient for most components.  (The really power-hungry components will also require a heat sink to help cool them).  So this means that the hottest locations on the board are right beneath the components.  What is beneath the component?  In the case of a BGA, there is usually a dense pinfield.  This pinfield creates a web of copper which will choke the current feeding the IC.  The current has to find its way through narrow pathways created by the “swiss cheese effect” of all the pinfield anitpads in the power and ground planes.  These areas of high current density will start emitting power in the form of heat, which means a drop in voltage for the IC as well as additional heat in that area of the board.

This article discusses the problem in more detail:

Don’t heat up your ICs even more by designing an inadequate PDN. 
How do you avoid that?  Simulate it!

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4 June, 2012

Simulation is a way of predicting reality.  The more information we put into the simulation, the better our prediction of what is really going to happen.  Certain aspects of electrical simulation, like signal integrity, can be simulated relatively “independently” of other influencing forces.  Sure, there are some temperature dependencies on silicon behavior, and those are typically represented by IBIS models created at different temperatures for fast, typical, and slow silicon behavior.  And also, the issues of vias tend to complicate things, as they blur the world between traditional signal integrity and power integrity as well as 3D electromagnetic simulation.  However, no two disciplines are more closely related than thermal analysis and power integrity, more specifically DC Drop.

The voltage drop across a plane is determined by the conductivity of the copper.  Copper conductivity changes 4% for every 10degC of temperature change.  That equates to a 32% change for an 80degC temperature rise, which is pretty significant.  So, in order to find an accurate measure of the voltage drop, temperature needs to be included.  The other interesting aspect of this is that drops in voltage mean power is being dissipated by the plane, power that is being dissipated as heat.  So, the results of each of these analyses will affect one another.  Hence, the need for PI/Thermal Co-simulation.

You can read more about this in my recent article in Printed Circuit Design and Manufacturing Magazine:

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19 August, 2011

This past week, HyperLynx took it’s first steps into cyberspace with the introduction of HyperLynx PI Virtual Labs! What is a virtual lab you may ask? If you’ve ever wanted to give HyperLynx PI a try, but haven’t had time to go through the steps to make it happen – this is for you! No software download or installs, no license request or setup – it’s as easy as clicking a few buttons and launching into HyperLynx PI. The virtual labs give you a self-guided tour of the HyperLynx PI product with hands-on experience in the real software (no “demo version” or AVI’s here). The labs investigate common issues in power integrity design from problems related to DC drop and current density, which are commonplace in today’s high density PCBs, to decoupling design for managing voltage ripple on supply rails.

Interested in trying it out for yourself?  Hit the link below to find out how:

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26 May, 2011

At the very minimum, a good board stackup has solid reference planes for signal routing.  Power demands now pretty much require that you have at least one power/ground sandwich in your stackup as well.  Ideally, you would have all the power and ground planes on the top layers in a big PWR-GND-PWR-GND alternating “Big Mac” where they were nice and close to the ICs and all the caps were mounted on the top.  But that would also require symmetry to the bottom of the board and that’s a lot of layers just for power.  But you should really have at least one power/ground sandwich somewhere in the board, especially if you are running some very low voltages with high current demands.  The reason is that embedded capacitance in the board really helps reduce the higher-frequency pieces of the power distribution network (PDN) impedance.  More-so, it provides a low-impedance path for energy to propagate between the decoupling caps and the IC power pins.

You might think that as long as your caps are connected to solid planes you are fine, but in reality you need to have a plane pair in order for the caps to have a nice low-inductance connection.  If they are not connected to a plane pair, they are rendered almost useless.  Kind of like routing a trace without a reference plane.

To read more about stackup design, check out my article in PCD&F:

And to learn more about power integrity, take a look at some of the great materials on our web site:

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23 May, 2011

Proper stackup design is the key to ensuring maximum performance for your PCB design.  Electromagnetic compatibility, signal integrity, power integrity – even proper thermal performance – can all be ensured with the proper stackup design.  Given the high route density of most boards nowadays, you try to pack as many routing layers as possible into a given thickness.  For most large-scale consumer products, cost is even more important than thickness, and often the number of route layers is the bare minimum just to connect everything.  But that doesn’t mean that you have to sacrifice performance or reliability. 

Probably the most important aspect of your stackup design is ensuring your signals have a solid reference.  That is best accomplished by having solid ground planes throughout the stackup, but that is not always possible, especially given the large power needs of modern ICs.  So if you also have a bunch of power planes, they can also be used as a reference, but you need to make sure the signals using that power are the ones references to that plane, or piece of the plane.  This is usually not too difficult to implement, since the power pins for I/Os usually sit next to the I/O pins themselves in the IC pinfield.

You can read all about stackup design in my latest article in the PCD&F designers notebook at:

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4 October, 2010

I talk with a lot of customers about their designs and what’s needed to get their products out the door and for the most part, they have many of the same challenges across all industries.  One of the new areas that has been challenging digital designers the most has been in power.  Not necessarily designing power supply circuits, but actually looking at power delivery on the PCB (i.e. power planes, area fills, capacitors).

So why is it a challenge suddenly?  There are a variety of reasons that I could list, but here are a few of the main reasons:

1.  Low voltage cores and I/O in ICs

2.  Low power initiatives in IC design

3. Cheaper board costs (component and layer count)

Ultimately, we’re talking about what lies at the core of most engineering work – trading off cost vs. performance (including reliability).   It’s a tough trade-off sometimes and without the proper tools, it’s hard to know what you can trade-off against.  How do you know if you remove a power layer and go will positive planes with area fills that you are going to be providing enough copper?  How do you decide if you burying  power planes in the middle of the board vs. using the outer, what the better solution is?  How do you select which capacitors you put on the board and where?  Most designers don’t have the real estate to put them down as many as the IC manufacturer recommends, much less exactly the way they recommend it.

All of these can be tough answers to come-by but you can build some intuition about good design practices with the right set of tools as well as validate the design intent.  My next few posts, I’ll look into this subject a bit further and discuss how these trends are impacting board design.

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20 July, 2010

Last week we released the official version of HyperLynx 8.1. If you’ve been a beta tester (I know there are a lot of you out there), make sure you go to SupportNet and get this latest release!

This release includes new technology in both HyperLynx SI and PI.  Some key things in the release worth taking a look at if you haven’t been beta testing:

- Tons of new capabilities in HyperLynx PI but the most significant of these is post route decoupling analysis and plane noise simulation

- Significant new technology for SERDES analysis that includes native support for IBIS-AMI, the new algorithmic modeling standard for handling things like pre-emphasis and equalization

- Cool 3D visualization capabilities for eye diagram analysis that will captivate anyone’s attention

-DDRx Wizard supports new architectures for LPDDR and registered DIMMs

That’s just a few of the things you’ll find in HyperLynx 8.1.  Check out the release hightlights on the SupportNet site to find out more!

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