Posts Tagged ‘parallel’

7 March, 2012

Parallel busses are a pain to implement.  They really are.  Sure, they are slower than blazing-fast SERDES busses, but they introduce a lot more problems.  SERDES busses introduce a new set of problems because they are so fast, but they are also differential and serial, which eliminates a bunch of problems.  Parallel busses are single-ended, so they tend to draw a lot more power.  So that means you have to worry about designing a good power distribution network (PDN), and worry about things like simultaneous switching noise.  Any layer transitions require ample stitching vias (or stitching capacitors) as well, so the vias and PDN are inter-related.  Not to mention all the complicated timing relationships that need to be maintained…

The original DDR was probably the toughest parallel bus to implement successfully.  DDR2 got faster, but also implemented a number of changes to make implementation easier – changes like using slew-rate derating to get a better picture of your timing margin, and allowing for 2T timing on the heavily-loaded address bus.  And DDR3 added the new fly-by address routing and write-leveling.  Really, these changes were necessary to operate at faster speeds, but also helped make things easier.  Easier, that is, if you understand how to include all of them in your analysis of the bus.

If you are interested in finding out more about the challenges facing DDR3/4 and SERDES busses, take a look at this article in New Electronics magazine:
http://www.newelectronics.co.uk/electronics-technology/the-challenges-of-designing-high-speed-interfaces-at-the-board-level/40549/

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