Posts Tagged ‘equalization’

6 March, 2012

Interconnect loss modeling?  Check. 
Signal conditioning modeling?  Check. 
Ability to simulate multiple S-parameter models for things like connectors and packages and vias correctly in the time domain?  Oooh…. that’s a tough one.  Check!
Ability to include all sources of deterministic and random jitter, worst-case bit patterns, and worst-case crosstalk in the analysis?  Wow!  Check.
3D via modeling?  Check!
HyperLynx 8.2 is fully equipped to handle every SERDES problem you can throw at it.  Really, any signal integrity problem you can throw at it.  Power integrity too.

In general, SERDES designs are a lot easier to implement than parallel busses.  You have a smaller number of problems to worry about, but the problems that are there are considerable.  They are basically problems of fast edges and low margins.  The fast edges require careful attention to detail in all aspects of the layout, and bring about the need to analyze pieces of the interconnect that could be ignored with slower edges, most notably vias.  And the low margins necessitate a greater understanding of when the bus will actually fail.  So in order to be successful in the analysis of these busses, care must be taken to include everything that is needed to understand the limits.

Read more about it in my recent article in New Electronics magazine: 
http://www.newelectronics.co.uk/electronics-technology/the-challenges-of-designing-high-speed-interfaces-at-the-board-level/40549/

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5 March, 2012

“A man’s got to know his limitations” … true, and so does a digital bus.  Clint Eastwood’s quote to conclude the movie Magnum Force in 1973 also applies to digital busses.  Of course, back then, signal edge rates were slow enough that most people didn’t have to care too much about signal integrity.  And now, in sharp contrast, we’ve progressed to the point where we try to validate busses down to bit error rate (BER) levels of 10^-15.  And things are moving so fast now that you can’t rely on measurement to know your margins, or your limits.  Even parallel busses like DDR3 require simulation in order to appropriately understand the margins of the bus.  Probing at the pin on such busses yields little more than very ugly waveforms, so simulation allows a unique perspective into the limits of the bus. 

For SERDES busses, this is especially true.  With receiver equalization becoming very common, it is very important to know what the signal looks like inside the IC.  And, in order to ensure the bus will work to the required performance standards, you have to run simulations that predict performance for trillions of bits, and include effects of deterministic and random jitter.

You can read about this in greater detail in my recent article in New Electronics magazine on page 25:
http://journal-download.co.uk/digitalmagazines//ne/ne28feb2012fullne.pdf

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