Archive for Patrick Carrier

20 July, 2015

This is the first in a three-part series discussing PCB design EMI reduction.

How can you tell if a fence is goat-proof? Throw a bucket full of water at it, and if any makes it through, the goat can get through the fence. That is one of the many pieces of “folksy” wisdom I have gotten over the years from my father-in-law, and one of the many benefits that comes along with marrying a girl from Texas.

But, all kidding aside, trying to contain EMI can actually be a lot like trying to keep a goat inside a fence. It is one of the topics I discuss in “Options for Reducing EMI on a PCB Design,” my recent article on Printed Circuit Design & Fab.

The most obvious method of containing radiated emissions is to put your PCB inside some kind of metal box. If you need holes for ventilation, those holes need to be small enough to contain your highest frequency of concern. If you need to be able to open the box, the openings need to have EMI gaskets so that the box still acts like a Faraday cage to contain your emissions.

If you don’t want to go through that hassle, you might try containing EMI at the PCB level, by turning your PCB into a Faraday cage. This can be done by routing a thick trace around the periphery of the board on each layer (or at least the outer layers), and stitching them together periodically with vias.  Such a structure can be verified by using the “Edge Shield” DRC, one of the standard rules in HyperLynx.

Contain the PCB Design EMI Beast

Depiction of Faraday cage on a board; side view of resulting apertures; results from running Edge Shield DRC in HyperLynx DRC

12 November, 2014

For most busses, length-matching a group of signals to 5 mils is a bit of overkill.  But, if length-matching to 5 mils is as easy for your layout personnel as length-matching to 100 mils, why not get the extra margin?  However, for very fast serial links, length-matching the two sides of a differential pair is absolutely crucial.  That is one of the key steps I discuss in my article “Ten Steps to Ten GigHertz“.
But length-matching the total length to a tight tolerance isn’t the only length-matching requirement.  Of course, the two halves of a differential pair need to be tightly length-matched so that both halves of the signal arrive at the same time.  But it is also important that the two halves of the signal travel together as well – in other words, the + and – signal should be in phase with one another throughout the route.  That means at any given location, the trace lengths are matched.  This is especially important at vias, where the matching of the signals is incredibly important to ensure that the signals pass through the vias in a purely differential mode, as this will limit the amount of energy radiated by the signals, as well as limit the amount of noise that the signals pick up.  This is especially crucial for 10GHz signals where margins are very tight.
This type of length-matching can be achieved by using phase-matching routing, like that implemented in Xpedition VX.  My colleague Charles discussed this the other day in his blog.  Click here to take a look if you are interested.

6 November, 2014

My grandma always told me not to sweat the small stuff, and since she just celebrated her 100th birthday, I am inclined to take her advice.  Unfortunately, that advice does not extend well to 10GHz serial links on a PCB, where you really DO need to sweat the small stuff.  With edge rates on the order of 50ps (that’s about 300 mils long on a PCB), 10GHz signals get affected by almost any discontinuity on a board, even those less than 100 mils.  So, special care must be taken to ensure that the entire differential path is free from discontinuities.

The biggest discontinuity faced by a 10GHz signal is a via.  That means your differential via pair must be designed to as close to 100ohms as possible.  This can be achieved by using smaller barrels, removing non-functional pads, and spacing the vias an appropriate distance apart.  The best way to design and simulate a differential via pair is by using a full-wave 3D electromagnetic simulator, like the one integrated into the LineSim GHz via modeler.  Minimizing or preferably eliminating via stubs is also an essential part of the design.  This means selecting the right routing layers, or employing the use of backdrilling, or even using blind and/or buried vias.

I discuss this and other topics related to the successful implementation of 10GHz serial links in my article “Ten Steps to Ten GigHertz“.  Take a look if you are interested in learning more.

5 November, 2014

When designing the trace configuration for your differential pairs, you are typically targeting 100 ohms differential.  That means each trace would be a 50-ohm trace, if there were no coupling between the traces.  But, you usually want some decent coupling between the traces, so a good single-ended impedance target for each trace is between 60 and 75 ohms.  That means that the differential pairs will have the highest-impedance traces on a given layer.  That also means they will have the narrowest trace width.  Typically that trace width will be 4 or 5 mils, to maximize routing density while maintaining a reasonable design cost.  However, differential pairs are typically running very fast, in the GHz range, so a very narrow trace width can limit the length of the pair to just a few inches.  By using wider traces, the copper losses can be reduced, allowing the differential pair to be routed over a longer distance.  However, wider traces also mean thicker dielectrics to maintain a 100-ohm differential impedance, and thicker dielectrics mean more spacing from other signals is required to minimize crosstalk.  So, basically, loss and routing density are at odds.  This can be offset somewhat by using a lower-loss dielectric, but the cost of doing so might be more than just adding additional layers to make up for the loss of routing density.  This is where high-speed analysis and simulation can be of great benefit in allowing you to make the right design tradeoffs.

I discuss this and other issues of working with high-speed differential pairs in my article “Ten Steps to Ten Gigahertz“, in Printed Circuit Design and Manufacture magazine.

9 September, 2014

I have recently been blogging about signal and power integrity, how the two are related, and how they can cross over.  This was prompted by an article I recently wrote for the DesignCon branch of EDN.  Twenty years ago, one of the biggest barriers to designing high-speed PCBs was ensuring signal integrity.  About ten years ago, power integrity started becoming a serious issue.  So what is next?  Is there another type of “integrity” we need to start analyzing?

No – at this point we pretty much have everything covered.  No more integrities on the horizon.  But what likely will change is how much we analyze in each of these analysis types…  For instance, if we look at vias, they used to be short enough to just model as a simple capacitor, then a simple L-C, and now for high-speed differential signals we need a full-wave 3D EM model of the via to properly characterize it for simulation.  For single-ended vias, we need to know the entire PDN to get an accurate signal model for the via.  And that is another trend that is permeating analysis needs – the impending crossover between signal and power integrity.  Eventually integrity analysis will encompass both, as well as other disciplines, all on the way to being able to create “virtual prototypes” of our PCBs, being able to predict their performance in a number of realms before the first prototype is manufactured.

8 September, 2014

There are a lot of reasons to mix SI and PI analysis – trying to figure out a worst-case stimuli to determine PDN performance, trying to see the effect of a poor PDN on signals due to SSN issues, or just being able to properly analyze a single-ended via.  In fact, to get an accurate model of a single-ended via, you have to mix SI and PI.  The reason is that the power distribution network, or PDN – decoupling capacitors, stitching vias, and plane pairs – make up the signal return path for a single-ended via, thus determining the “impedance”, delay, and crosstalk characteristics of the via.  This is especially crucial when modeling very fast, single-ended signals like DDR3 and DDR4 signals.  In HyperLynx, you can extract via models which include the PDN; this is achieved by the PI engine running in the background during the via model extraction.  The result is a very accurate wideband single-ended via model that properly captures the via’s electrical characteristics.  Once extracted, this model can be used in other simulations again and again.  Another option is to use the SI/PI co-simulation option, which generates these models on-the-fly.

To learn more about mixing SI and PI, take a look at this article in EDN:
http://www.edn.com/design/designcon/4433827/Signal-integrity-and-power-integrity-in-high-speed-design

3 September, 2014

Power integrity (PI) is an analysis discipline that has been around for years.  Signal integrity (SI) has been around for a few more years.  Basically, they both deal with the proper analog operation of digital circuits.  So why these specific realms of analysis?  The main issue is that there is no such thing as “digital” – what we call “digital” data transmission is really just voltages compared to thresholds, so making sure we have the right voltages at the right times is the essence of signal integrity.  Power integrity is a bit more broad in its scope, but a “power integrity” failure usually leads to the same results as a signal integrity failure – some kind of erroneous data.  It is tempting to try to analyze everything in a PCB design as one big “virtual prototype”, but modeling and computing limitations keep that from being practical.  Furthermore, the design process is made a bit easier by dividing up these problems.  For instance, a signal integrity problem can be solved by changing the line impedance, adding termination, or adjusting spacing to control crosstalk.  It is helpful to be able to analyze just the signal integrity of a circuit to look for these types of solutions.  Similarly, for power integrity, possible solutions might be adding more metal to control a DC Drop problem or changing the way capacitors are mounted to improve the PDN performance at higher frequencies.
For more information, check out the following article in EDN: Signal Integrity and Power Integrity in High-Speed Design.

Whatever your chosen flavor of integrity, be sure to simulate it early in the design cycle, otherwise you might get left with a bad taste in your mouth…

28 July, 2014

Earlier this year I wrote an article on maximizing capacitor effectiveness.  I have since received a number of inquiries on mounting capacitors directly to a power via on the opposite side of the board from the IC.  This is actually a fairly common design practice that I have seen on many boards.  And, the question is, is this better than mounting the capacitors around the outside of the IC on the top side of the board?  What do you think?

It is a question easily answered by spending a few minutes in the PDN Editor in LineSim.  If you don’t have a license for HyperLynx PI, you can try it out for free in the HyperLynx Virtual Lab:

http://www.mentor.com/pcb/product-eval/hyperlynx-online-trial

It seems like the best place to mount a capacitor would be directly to a power via, as it is the closest you an get to those power pins.  Will that always be better than mounting the capacitor on the same side of the board as the IC?  Well, like anything else in signal and power integrity, it depends.  In this case, the answer depends on where in the stackup your power/ground plane pair lies.  Using the same example stackup that I used in the above-mentioned article, I used the PDN editor in LineSim to look at the mounted impedance of a 220nF 0402 capacitor mounted 1 inch away from the power pin on the top of the board, and also mounted directly to the power via on the opposite side of the board.  With the power/ground plane pair closest to the top (VCC1/GND1 in the reference stackup), the capacitor mounted an inch away on the top actually exhibited a much lower impedance than the capacitor directly connected to the power via on the opposite side of the board.  This is shown in the pic below: the impedance of the top-side cap is shown in yellow, while the cap connected to the power via is shown in pink.

top_side_v_back_side

That may seem non-intuitive, since the opposite-side cap is only 62 mils (the board thickness) away from the IC, whereas the same-side cap is 1000 mils away!  But the key factor is inductance, not distance.  Even if we use an 0402 cap and via-in-pad, the distance between the mounting vias is still 40 mils.  Compared to the 3-mil spacing between the planes, that creates a much larger loop area, and much higher inductance.  The plane-pair connection is much lower inductance, so much so that even for a much longer connection distance, it still creates a lower-impedance connection for the capacitor.

5 May, 2014

I guess that all depends on what you are talking about… for Signal Integrity, trace width is very important, as it is one of the main factors in determining the characteristic impedance of a trace.  For Power Integrity, trace width becomes important the longer your traces are.  But in general, when you say “long traces” and “power integrity” in the same sentence, you are headed for some problems.  A great way to figure out how bad your problems might be is to run some simulations – and that is where the PDN Editor in LineSim is an indispensable tool.  You can modify things like trace width and see how much your DC voltage drop changes.  You can also see the effect trace width will have on your decoupling capacitors.  Earlier this year I blogged about an article I wrote for PCD and F, where I explored some more common capacitor mounting methods and their effect on the PDN impedance.  I actually found that adjusting the spacing between the capacitor vias had a much more dramatic effect than the width of the traces connecting the capacitor to the vias.  Obviously this is best achieved by using via-in-pad.  But this effect can be further enhanced by using reverse-aspect-ratio capacitors, like 0204s.
So, in this case, no, trace width did not matter much.  But don’t take my word for it – experiment yourself using the PI Virtual Lab, available at:
http://www.mentor.com/pcb/product-eval/hyperlynx-online-trial
There are a number of tutorials that walk through the process of analyzing power integrity on a PCB, and you can open up the LineSim PDN Editor and experiment with things like trace width, via spacing, number of vias, number of capacitors, capacitor values, stackup, plane spacing, and more to really quantify different design tradeoffs in designing a PCB power distribution network.

13 January, 2014

Capacitors are the backbone of a board power distribution network, or PDN.  However, just as important as having the capacitors connected to the PDN is how they are connected.  If you think that connecting them with inch-long 5-mil traces is a good idea, you might want to reconsider (or maybe you are still living in the ’70s?).  Obviously that is an extreme example, but there are a number of nuances to connecting capacitors to the board to maximize their effectiveness as part of the PDN.  I actually analyzed and quantified some common capacitor mounting methods in the following article: http://www.pcdandf.com/pcdesign/index.php/current-issue/241-designer-s-notebook/9233-designers-notebook-1401

Among the variables explored are the connections to the planes, and that doesn’t just mean the connections themselves, but the plane configuration.  This can have a huge effect on the mounted inductance of the capacitor.  The separation between the power and ground planes is probably the most important.  Planes which are very close together are actually much more effective in minimizing the mounted inductance of the capacitor than planes which are further apart but closer to the capacitor (like in layers closer to the top).  In fact, that is one of the many tradeoffs you can analyze in the PDN editor in HyperLynx LineSim when trying to plan your PDN design.

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