Archive for Patrick Carrier

28 July, 2014

Earlier this year I wrote an article on maximizing capacitor effectiveness.  I have since received a number of inquiries on mounting capacitors directly to a power via on the opposite side of the board from the IC.  This is actually a fairly common design practice that I have seen on many boards.  And, the question is, is this better than mounting the capacitors around the outside of the IC on the top side of the board?  What do you think?

It is a question easily answered by spending a few minutes in the PDN Editor in LineSim.  If you don’t have a license for HyperLynx PI, you can try it out for free in the HyperLynx Virtual Lab:

It seems like the best place to mount a capacitor would be directly to a power via, as it is the closest you an get to those power pins.  Will that always be better than mounting the capacitor on the same side of the board as the IC?  Well, like anything else in signal and power integrity, it depends.  In this case, the answer depends on where in the stackup your power/ground plane pair lies.  Using the same example stackup that I used in the above-mentioned article, I used the PDN editor in LineSim to look at the mounted impedance of a 220nF 0402 capacitor mounted 1 inch away from the power pin on the top of the board, and also mounted directly to the power via on the opposite side of the board.  With the power/ground plane pair closest to the top (VCC1/GND1 in the reference stackup), the capacitor mounted an inch away on the top actually exhibited a much lower impedance than the capacitor directly connected to the power via on the opposite side of the board.  This is shown in the pic below: the impedance of the top-side cap is shown in yellow, while the cap connected to the power via is shown in pink.


That may seem non-intuitive, since the opposite-side cap is only 62 mils (the board thickness) away from the IC, whereas the same-side cap is 1000 mils away!  But the key factor is inductance, not distance.  Even if we use an 0402 cap and via-in-pad, the distance between the mounting vias is still 40 mils.  Compared to the 3-mil spacing between the planes, that creates a much larger loop area, and much higher inductance.  The plane-pair connection is much lower inductance, so much so that even for a much longer connection distance, it still creates a lower-impedance connection for the capacitor.

5 May, 2014

I guess that all depends on what you are talking about… for Signal Integrity, trace width is very important, as it is one of the main factors in determining the characteristic impedance of a trace.  For Power Integrity, trace width becomes important the longer your traces are.  But in general, when you say “long traces” and “power integrity” in the same sentence, you are headed for some problems.  A great way to figure out how bad your problems might be is to run some simulations – and that is where the PDN Editor in LineSim is an indispensable tool.  You can modify things like trace width and see how much your DC voltage drop changes.  You can also see the effect trace width will have on your decoupling capacitors.  Earlier this year I blogged about an article I wrote for PCD and F, where I explored some more common capacitor mounting methods and their effect on the PDN impedance.  I actually found that adjusting the spacing between the capacitor vias had a much more dramatic effect than the width of the traces connecting the capacitor to the vias.  Obviously this is best achieved by using via-in-pad.  But this effect can be further enhanced by using reverse-aspect-ratio capacitors, like 0204s.
So, in this case, no, trace width did not matter much.  But don’t take my word for it – experiment yourself using the PI Virtual Lab, available at:
There are a number of tutorials that walk through the process of analyzing power integrity on a PCB, and you can open up the LineSim PDN Editor and experiment with things like trace width, via spacing, number of vias, number of capacitors, capacitor values, stackup, plane spacing, and more to really quantify different design tradeoffs in designing a PCB power distribution network.

13 January, 2014

Capacitors are the backbone of a board power distribution network, or PDN.  However, just as important as having the capacitors connected to the PDN is how they are connected.  If you think that connecting them with inch-long 5-mil traces is a good idea, you might want to reconsider (or maybe you are still living in the ’70s?).  Obviously that is an extreme example, but there are a number of nuances to connecting capacitors to the board to maximize their effectiveness as part of the PDN.  I actually analyzed and quantified some common capacitor mounting methods in the following article:

Among the variables explored are the connections to the planes, and that doesn’t just mean the connections themselves, but the plane configuration.  This can have a huge effect on the mounted inductance of the capacitor.  The separation between the power and ground planes is probably the most important.  Planes which are very close together are actually much more effective in minimizing the mounted inductance of the capacitor than planes which are further apart but closer to the capacitor (like in layers closer to the top).  In fact, that is one of the many tradeoffs you can analyze in the PDN editor in HyperLynx LineSim when trying to plan your PDN design.

9 January, 2014

A common question when designing a PDN (power distribution network) for a printed circuit board is which capacitor values to use.  A common practice is to use values in each decade – values like 10uF, 1uF, 0.1uF, and 0.01uF… and there is some reasoning behind that, but a little knowledge of decoupling capacitors can help you pick values that make more sense.  There is a great deal of information on designing a PDN in the following article:

Printed Circuit Design & Fab: Maximizing Capacitor Effectiveness

One of the items discussed is picking capacitors that have the most capacitance for a given body size.  The reasoning behind this is that the limiting factor for a capacitor’s performance is the inductance.  Capacitors with smaller body sizes have the least inductance, and also allow for the least amount of mounted inductance.  An 0402 capacitor, for example, typically comes in values up to 0.22uF.  So, using 0.22uF 0402 capacitors is a better idea than using 0.1uF capacitors, as you get over twice the capacitance for the same amount of inductance.  But in order to get a significant amount of capacitance, you need to use a large number of these capacitors in parallel.  These are the “high-frequency” capacitors of the PDN, because they are the capacitors that are effective at higher frequencies, because of their small inductance.  Axial-leaded caps, on the other hand, have much larger capacitance, but also large inductance, and thus are only effective at decoupling lower frequencies.  You can play with different capacitor values to optimize your PDN using the HyperLynx PDN Editor.

3 July, 2013

When designing a PCB, part of the design process is making sure the PCB works correctly.  At the very least, someone does some functional testing.  But what happens if problems are found?  A more detailed look at the design must be performed.  And in fact, the best way to end up with a working design is to check the performance during the design process.

So if you have to choose between simulating or measuring your boards, which would you choose?  I would say the best answer is to make time for both.  Don’t choose: simulate your cake and measure it, too.

Most people would be tempted to say just measure the board, because that will always be the closest to reality.  But that is not always the case, especially with the fast busses used on PCB designs today.  Edge rates are so fast that measuring the actual system is not practical, because you would really have to measure inside of the chip to get an accurate view of the performance.  Measurements need to be taken on test boards or with special test fixtures, which may not represent the actual system.  This is where simulation is indispensable, as it can allow you to look in places the probes can’t touch.

If you are interested in more on this topic, please take a look at the following article:


28 June, 2013

We go through great pains to ensure that our analysis tools give highly accurate answers in the most efficient manner possible.  That requires accurate field solving – in both 2 dimensions and 3 dimensions, as appropriate – as well as accurate simulation.  Accurate simulation includes simulation of S-parameters in the time domain, which requires appropriate handling of causality and passivity issues, proper concatenation of multiple S-parameters, and the avoidance of common pitfalls from brute-force methods like convolution (we use complex pole-fitting instead, which is accurate and efficient).  It also means appropriately handling all determinsitic and random jitter sources by utlizing worst-case bit sequences to accurately predict BER down to 10^-18 and beyond.  All of this becomes crucial at multi-GBs SERDES speeds.  An example of SERDES simulation/measurement correlation can be found in the following article:

It is important to make sure that all of your inputs into the simulation are accurate.  That starts with something as simple as getting the board stackup and trace widths to match what is actually manufactured – take a look at the references at the end of the article above (or some of my previous blogs) for more info.  For SERDES speeds specifically, that means making sure any models used, like SPICE and S-parameters, have the the appropriate bandwidth, and that all the pieces of the channel have been solved with the appropriate field solver.  Even for PI, it is important to make sure that capacitor ESL is appropriately understood and the correct method of modeling ESL is used, as this can have a dramatic effect on the results of a PI analysis.

If you take the time to make sure you are feeding HyperLynx the right information, it will give you the answers you seek about the true performance of your design.

26 June, 2013

A few months ago my colleague Chuck Ferry posted a blog about a correlation study he did for DesignCon, where he compared results from a multi-Gbs SERDES simulation to some measured results and showed excellent correlation.  If you are interested, scroll down and you can find that blog, or you can click on this link:

Correlating simulation and measurement is not a particularly “easy” task, since it requires advanced knowledge of simulation as well as measurement.  Very often designers will rely on one more than the other, usually depending on their expertise.  But going through the exercise of comparing the two will be of great benefit to anyone designing a PCB, as it can reveal limitations in simulation as well as measurement, and what steps need to be taken to ensure that simulations match measurements, and measurements match simulations.  An understanding of the difference between them is a good first step, and can be found in the following article:
Some of the material from Chuck’s correlation study was used for the article.

Simulation and measurement technology continue to evolve to meet the needs of ever-increasing performance of our electronics designs, and understanding how to utilize them in the design process can lead to more reliable products.  At today’s speeds, running “blind” and using neither will almost surely result in design failure.

9 January, 2013

If signal integrity engineers had the power to make their jobs as easy as possible, every signal in an electronic device would have its own coaxial cable to connect driver to transmitter.  But then electronics would be the size of buildings again and certainly wouldn’t fit in your pocket.  So instead, we try to cram as much stuff as possible onto a little PCB and make it work at 100s and 1000s of MHz.   And, for the most part, we are successful, even when faced with cost reductions and crazy form factors that make our jobs even harder.

A consequence of that is trying to control all the coupling that occurs between signals, and to the outside world.  Something like a via transition makes that really hard to do.  Ideally, every signal via transition would be surrounded by as many vias as possible, all conected together to mimic the shield of a coaxial cable.  But that is pretty unrealistic, so we usually add a couple of transition vias around the signal via.  Some people only add one, and some don’t add any!!  How many do you need?  Well, you can answer that by running SI-PI co-simulations using Hyperlynx SI/PI.  It allows you to experiment with different configurations of stitching vias, or stitching capacitors (necessary if the via is transitioning between layers that reference different planes of different voltages).  Once you’ve determined what configuration works for your stackup and your signals, you can use the Vertical Reference Plane Change DRC in HyperLynx DRC to verify that it was done correctly, and that your board will be free from all the coupling that occurs from signals transitioning through vias.

Read this article to find out more:

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7 January, 2013

One of the nice things about newer, faster busses like DDR3 and DDR4 is on-die termination.  They are nice because you don’t have a bunch of components clogging up your routing layers, and I would say more importantly, it limits your required layer transitions which can help make your boards quieter.  So take advantage of the fact that you don’t have to route out to a terminator and try to keep your layer transitions limited to underneath the IC.  The area under the IC is a particularly exciting location on the board, and also happens to be the best place for layer transitions.

In a recent aricle in Printed Circuit Design and Fabrication Magazine, I discuss the EMI problems associated with layer transitions.  The article can be found here:
Bascially, a stitching via is needed anywhere you transition a signal between layers, to provide a continuous return current path for the signal.  I have discussed return current paths in several previous blogs, but to summarize, broken return path = radiating signal.  This is why a stitching via is needed when a signal transitions between layers.  Well, more precisely, a stitching “thingy” – in the case that the different return paths are planes with the same voltage (usually ground), a via will work.  But if they are at different potentials, a capacitor should be used.  Where on the board are there the most vias and capacitors?  Just around the IC.  This makes it the best place to do any layer transitioning.

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4 January, 2013

In the past I have blogged about crossing splits in reference planes.  This is probably the most glaringly obvious of reference plane changes, and will of course result in radiation from the signal. 

But another type of reference plane change which is more common, and usually much less avoidable, is when a signal transitions layers through a via.  In such a case, the reference planes will change and the return current will need to find a path to accomodate the change.  This is probably best explained with a picture, which can be seen (along with a more complete explanation) in my recent article in PCDandF:
This problem is most severe for very fast, single-ended signals like DDR3 or DDR4, which will have all their return current present in their reference planes, and require a very close-by stitching via (or capacitor) in order to ensure minimal radiation of signal energy and minimal resulting signal degradation.  The further away the stitching via (or cap), the more energy that will radiate and the more degraded the signal will become.   SERDES signals, although much faster, also happen to be differential, which means that they tend to have mostly self-contained, zero net return current (since they consist of equal and opposite signals).

So, every time you transiton between signal layers, try to add a stitching via as well.  If you are wondering how many un-stitched transitions you have in your design, run the Vertical Reference Plane Change DRC in HyperLynx DRC and it will find them for you…

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