I guess that all depends on what you are talking about… for Signal Integrity, trace width is very important, as it is one of the main factors in determining the characteristic impedance of a trace. For Power Integrity, trace width becomes important the longer your traces are. But in general, when you say “long traces” and “power integrity” in the same sentence, you are headed for some problems. A great way to figure out how bad your problems might be is to run some simulations – and that is where the PDN Editor in LineSim is an indispensable tool. You can modify things like trace width and see how much your DC voltage drop changes. You can also see the effect trace width will have on your decoupling capacitors. Earlier this year I blogged about an article I wrote for PCD and F, where I explored some more common capacitor mounting methods and their effect on the PDN impedance. I actually found that adjusting the spacing between the capacitor vias had a much more dramatic effect than the width of the traces connecting the capacitor to the vias. Obviously this is best achieved by using via-in-pad. But this effect can be further enhanced by using reverse-aspect-ratio capacitors, like 0204s.
So, in this case, no, trace width did not matter much. But don’t take my word for it – experiment yourself using the PI Virtual Lab, available at:
There are a number of tutorials that walk through the process of analyzing power integrity on a PCB, and you can open up the LineSim PDN Editor and experiment with things like trace width, via spacing, number of vias, number of capacitors, capacitor values, stackup, plane spacing, and more to really quantify different design tradeoffs in designing a PCB power distribution network.
Archive for Patrick Carrier
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